4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
10 from ifacebase
import InterfacesBase
11 from bsv
.peripheral_gen
import PFactory
12 from bsv
.peripheral_gen
import axi_slave_declarations
13 slowfactory
= PFactory()
17 """ pin interface declaration.
18 * name is the name of the pin
19 * ready, enabled and io all create a (* .... *) prefix
20 * action changes it to an "in" if true
23 def __init__(self
, name
,
32 self
.enabled
= enabled
35 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
36 self
.outenmode
= outenmode
38 # bsv will look like this (method declaration):
40 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
41 (*always_ready,always_enabled,result="io"*) method
42 Action io0_inputval (Bit#(1) in);
45 def ifacefmt(self
, fmtfn
):
49 status
.append('always_ready')
51 status
.append('always_enabled')
53 status
.append('result="io"')
56 res
+= ','.join(status
)
61 name
= fmtfn(self
.name
)
65 res
+= ' (%s in)' % self
.bitspec
67 res
+= " %s " % self
.bitspec
72 # sample bsv method definition :
74 method Action cell0_mux(Bit#(2) in);
79 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
82 fmtname
= fmtinfn(self
.name
)
84 res
+= fmtdecfn(self
.name
)
85 res
+= '(%s in);\n' % self
.bitspec
86 res
+= ' %s<=in;\n' % fmtname
89 fmtname
= fmtoutfn(self
.name
)
90 res
+= "%s=%s;" % (self
.name
, fmtname
)
92 # sample bsv wire (wire definiton):
94 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
97 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
98 res
= ' Wire#(%s) ' % self
.bitspec
100 res
+= '%s' % fmtinfn(self
.name
)
102 res
+= '%s' % fmtoutfn(self
.name
)
103 res
+= "<-mkDWire(0);"
107 class Interface(object):
108 """ create an interface from a list of pinspecs.
109 each pinspec is a dictionary, see Pin class arguments
110 single indicates that there is only one of these, and
111 so the name must *not* be extended numerically (see pname)
113 # sample interface object:
115 twiinterface_decl = Interface('twi',
116 [{'name': 'sda', 'outen': True},
117 {'name': 'scl', 'outen': True},
121 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
122 self
.ifacename
= ifacename
123 self
.ganged
= ganged
or {}
124 self
.pins
= [] # a list of instances of class Pin
125 self
.pinspecs
= pinspecs
# a list of dictionary
128 slow
= slowfactory
.getcls(ifacename
)
137 if p
.get('outen') is True: # special case, generate 3 pins
139 for psuffix
in ['out', 'outen', 'in']:
140 # changing the name (like sda) to (twi_sda_out)
141 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
142 _p
['action'] = psuffix
!= 'in'
143 self
.pins
.append(Pin(**_p
))
144 # will look like {'name': 'twi_sda_out', 'action': True}
145 # {'name': 'twi_sda_outen', 'action': True}
146 #{'name': 'twi_sda_in', 'action': False}
147 # NOTice - outen key is removed
149 _p
['name'] = self
.pname(p
['name'])
150 self
.pins
.append(Pin(**_p
))
152 # sample interface object:
154 uartinterface_decl = Interface('uart',
156 {'name': 'tx', 'action': True},
160 getifacetype is called multiple times in actual_pinmux.py
161 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
162 Purpose is to identify is function : input/output/inout
165 def getifacetype(self
, name
):
166 for p
in self
.pinspecs
:
167 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
168 # print "search", self.ifacename, name, fname
177 def pname(self
, name
):
178 """ generates the interface spec e.g. flexbus_ale
179 if there is only one flexbus interface, or
180 sd{0}_cmd if there are several. string format
181 function turns this into sd0_cmd, sd1_cmd as
182 appropriate. single mode stops the numerical extension.
185 return '%s_%s' % (self
.ifacename
, name
)
186 return '%s{0}_%s' % (self
.ifacename
, name
)
188 def busfmt(self
, *args
):
189 """ this function creates a bus "ganging" system based
190 on input from the {interfacename}.txt file.
191 only inout pins that are under the control of the
192 interface may be "ganged" together.
195 return '' # when self.ganged is None
198 for (k
, pnames
) in self
.ganged
.items():
199 name
= self
.pname('%senable' % k
).format(*args
)
200 decl
= 'Bit#(1) %s = 0;' % name
203 for p
in self
.pinspecs
:
204 if p
['name'] not in pnames
:
206 pname
= self
.pname(p
['name']).format(*args
)
207 if p
.get('outen') is True:
208 outname
= self
.ifacefmtoutfn(pname
)
209 ganged
.append("%s_outen" % outname
) # match wirefmt
211 gangedfmt
= '{%s} = duplicate(%s);'
212 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
213 return '\n'.join(res
) + '\n\n'
215 def wirefmt(self
, *args
):
216 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
220 def ifacefmt(self
, *args
):
221 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
222 return '\n' + res
# pins is a list
224 def ifacefmtdecfn(self
, name
):
225 return name
# like: uart
227 def ifacefmtdecfn2(self
, name
):
228 return name
# like: uart
230 def ifacefmtdecfn3(self
, name
):
232 return "%s_outen" % name
# like uart_outen
234 def ifacefmtoutfn(self
, name
):
235 return "wr%s" % name
# like wruart
237 def ifacefmtinfn(self
, name
):
240 def wirefmtpin(self
, pin
):
241 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
244 def ifacefmtdecpin(self
, pin
):
245 return pin
.ifacefmt(self
.ifacefmtdecfn
)
247 def ifacefmtpin(self
, pin
):
248 decfn
= self
.ifacefmtdecfn2
249 outfn
= self
.ifacefmtoutfn
250 # print pin, pin.outenmode
252 decfn
= self
.ifacefmtdecfn3
253 outfn
= self
.ifacefmtoutenfn
254 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
257 def ifacedef(self
, *args
):
258 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
259 res
= res
.format(*args
)
260 return '\n' + res
+ '\n'
262 def slowimport(self
):
265 return self
.slow
.importfn().format()
267 def slowifdecl(self
, count
):
270 return self
.slow
.ifacedecl().format(count
, self
.ifacename
)
272 def axi_reg_def(self
, start
, count
):
275 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
277 def axi_slave_idx(self
, start
, count
):
280 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
283 class MuxInterface(Interface
):
285 def wirefmt(self
, *args
):
286 return muxwire
.format(*args
)
289 class IOInterface(Interface
):
291 def ifacefmtoutenfn(self
, name
):
292 return "cell{0}_mux_outen"
294 def ifacefmtoutfn(self
, name
):
295 """ for now strip off io{0}_ part """
296 return "cell{0}_mux_out"
298 def ifacefmtinfn(self
, name
):
299 return "cell{0}_mux_in"
301 def wirefmt(self
, *args
):
302 return generic_io
.format(*args
)
305 class Interfaces(InterfacesBase
):
306 """ contains a list of interface definitions
309 def __init__(self
, pth
=None):
310 InterfacesBase
.__init
__(self
, Interface
, pth
)
312 def ifacedef(self
, f
, *args
):
313 for (name
, count
) in self
.ifacecount
:
314 for i
in range(count
):
315 f
.write(self
.data
[name
].ifacedef(i
))
317 def busfmt(self
, f
, *args
):
318 f
.write("import BUtils::*;\n\n")
319 for (name
, count
) in self
.ifacecount
:
320 for i
in range(count
):
321 bf
= self
.data
[name
].busfmt(i
)
324 def ifacefmt(self
, f
, *args
):
326 // interface declaration between %s-{0} and pinmux'''
327 for (name
, count
) in self
.ifacecount
:
328 for i
in range(count
):
329 c
= comment
% name
.upper()
331 f
.write(self
.data
[name
].ifacefmt(i
))
333 def wirefmt(self
, f
, *args
):
334 comment
= '\n // following wires capture signals ' \
335 'to IO CELL if %s-{0} is\n' \
337 for (name
, count
) in self
.ifacecount
:
338 for i
in range(count
):
341 f
.write(self
.data
[name
].wirefmt(i
))
343 def slowimport(self
, *args
):
345 for (name
, count
) in self
.ifacecount
:
346 ret
.append(self
.data
[name
].slowimport())
347 return '\n'.join(list(filter(None, ret
)))
349 def slowifdecl(self
, *args
):
351 for (name
, count
) in self
.ifacecount
:
352 for i
in range(count
):
353 ret
.append(self
.data
[name
].slowifdecl(i
))
354 return '\n'.join(list(filter(None, ret
)))
356 def axi_reg_def(self
, *args
):
358 start
= 0x00011100 # start of AXI peripherals address
359 for (name
, count
) in self
.ifacecount
:
360 for i
in range(count
):
361 x
= self
.data
[name
].axi_reg_def(start
, i
)
362 print ("ifc", name
, x
)
366 return '\n'.join(list(filter(None, ret
)))
368 def axi_slave_idx(self
, *args
):
371 for (name
, count
) in self
.ifacecount
:
372 for i
in range(count
):
373 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
374 print ("ifc", name
, rdef
, offs
)
377 ret
.append("typedef %d LastGen_slave_num" % (start
- 1))
378 decls
= '\n'.join(list(filter(None, ret
)))
379 return axi_slave_declarations
.format(decls
)
382 # ========= Interface declarations ================ #
384 mux_interface
= MuxInterface('cell',
385 [{'name': 'mux', 'ready': False, 'enabled': False,
386 'bitspec': '{1}', 'action': True}])
388 io_interface
= IOInterface(
390 [{'name': 'cell_out', 'enabled': True, },
391 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
392 {'name': 'cell_in', 'action': True, 'io': True}, ])
394 # == Peripheral Interface definitions == #
395 # these are the interface of the peripherals to the pin mux
396 # Outputs from the peripherals will be inputs to the pinmux
397 # module. Hence the change in direction for most pins
399 # ======================================= #
402 if __name__
== '__main__':
404 uartinterface_decl
= Interface('uart',
406 {'name': 'tx', 'action': True},
409 twiinterface_decl
= Interface('twi',
410 [{'name': 'sda', 'outen': True},
411 {'name': 'scl', 'outen': True},
414 def _pinmunge(p
, sep
, repl
, dedupe
=True):
415 """ munges the text so it's easier to compare.
416 splits by separator, strips out blanks, re-joins.
421 p
= filter(lambda x
: x
, p
) # filter out blanks
425 """ munges the text so it's easier to compare.
427 # first join lines by semicolons, strip out returns
429 p
= map(lambda x
: x
.replace('\n', ''), p
)
431 # now split first by brackets, then spaces (deduping on spaces)
432 p
= _pinmunge(p
, "(", " ( ", False)
433 p
= _pinmunge(p
, ")", " ) ", False)
434 p
= _pinmunge(p
, " ", " ")
440 for p1
, p2
in zip(l1
, l2
):
446 ifaces
= Interfaces()
448 ifaceuart
= ifaces
['uart']
449 print (ifaceuart
.ifacedef(0))
450 print (uartinterface_decl
.ifacedef(0))
451 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
453 ifacetwi
= ifaces
['twi']
454 print (ifacetwi
.ifacedef(0))
455 print (twiinterface_decl
.ifacedef(0))
456 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)