4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
10 from ifacebase
import InterfacesBase
11 from bsv
.peripheral_gen
import PeripheralIface
12 from bsv
.peripheral_gen
import PeripheralInterfaces
16 """ pin interface declaration.
17 * name is the name of the pin
18 * ready, enabled and io all create a (* .... *) prefix
19 * action changes it to an "in" if true
22 def __init__(self
, name
,
33 self
.enabled
= enabled
36 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
37 self
.outenmode
= outenmode
39 # bsv will look like this (method declaration):
41 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
42 (*always_ready,always_enabled,result="io"*) method
43 Action io0_inputval (Bit#(1) in);
46 def ifacepfmt(self
, fmtfn
):
50 name
= fmtfn(self
.name_
)
55 res
+= "#(%s) %s;" % (self
.bitspec
, name
)
58 def ifacefmt(self
, fmtfn
):
62 status
.append('always_ready')
64 status
.append('always_enabled')
66 status
.append('result="io"')
69 res
+= ','.join(status
)
74 name
= fmtfn(self
.name
)
78 res
+= ' (%s in)' % self
.bitspec
80 res
+= " %s " % self
.bitspec
85 # sample bsv method definition :
87 method Action cell0_mux(Bit#(2) in);
92 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
95 fmtname
= fmtinfn(self
.name
)
97 res
+= fmtdecfn(self
.name
)
98 res
+= '(%s in);\n' % self
.bitspec
99 res
+= ' %s<=in;\n' % fmtname
102 fmtname
= fmtoutfn(self
.name
)
103 res
+= "%s=%s;" % (self
.name
, fmtname
)
105 # sample bsv wire (wire definiton):
107 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
110 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
111 res
= ' Wire#(%s) ' % self
.bitspec
113 res
+= '%s' % fmtinfn(self
.name
)
115 res
+= '%s' % fmtoutfn(self
.name
)
116 res
+= "<-mkDWire(0);"
120 class Interface(PeripheralIface
):
121 """ create an interface from a list of pinspecs.
122 each pinspec is a dictionary, see Pin class arguments
123 single indicates that there is only one of these, and
124 so the name must *not* be extended numerically (see pname)
126 # sample interface object:
128 twiinterface_decl = Interface('twi',
129 [{'name': 'sda', 'outen': True},
130 {'name': 'scl', 'outen': True},
134 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
135 PeripheralIface
.__init
__(self
, ifacename
)
136 self
.ifacename
= ifacename
137 self
.ganged
= ganged
or {}
138 self
.pins
= [] # a list of instances of class Pin
139 self
.pinspecs
= pinspecs
# a list of dictionary
147 if p
.get('outen') is True: # special case, generate 3 pins
149 for psuffix
in ['out', 'outen', 'in']:
150 # changing the name (like sda) to (twi_sda_out)
151 _p
['name_'] = "%s_%s" % (p
['name'], psuffix
)
152 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
153 _p
['action'] = psuffix
!= 'in'
154 self
.pins
.append(Pin(**_p
))
155 # will look like {'name': 'twi_sda_out', 'action': True}
156 # {'name': 'twi_sda_outen', 'action': True}
157 #{'name': 'twi_sda_in', 'action': False}
158 # NOTice - outen key is removed
160 _p
['name_'] = p
['name']
161 _p
['name'] = self
.pname(p
['name'])
162 self
.pins
.append(Pin(**_p
))
164 # sample interface object:
166 uartinterface_decl = Interface('uart',
168 {'name': 'tx', 'action': True},
172 getifacetype is called multiple times in actual_pinmux.py
173 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
174 Purpose is to identify is function : input/output/inout
177 def getifacetype(self
, name
):
178 for p
in self
.pinspecs
:
179 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
180 # print "search", self.ifacename, name, fname
189 def pname(self
, name
):
190 """ generates the interface spec e.g. flexbus_ale
191 if there is only one flexbus interface, or
192 sd{0}_cmd if there are several. string format
193 function turns this into sd0_cmd, sd1_cmd as
194 appropriate. single mode stops the numerical extension.
197 return '%s_%s' % (self
.ifacename
, name
)
198 return '%s{0}_%s' % (self
.ifacename
, name
)
200 def busfmt(self
, *args
):
201 """ this function creates a bus "ganging" system based
202 on input from the {interfacename}.txt file.
203 only inout pins that are under the control of the
204 interface may be "ganged" together.
207 return '' # when self.ganged is None
210 for (k
, pnames
) in self
.ganged
.items():
211 name
= self
.pname('%senable' % k
).format(*args
)
212 decl
= 'Bit#(1) %s = 0;' % name
215 for p
in self
.pinspecs
:
216 if p
['name'] not in pnames
:
218 pname
= self
.pname(p
['name']).format(*args
)
219 if p
.get('outen') is True:
220 outname
= self
.ifacefmtoutfn(pname
)
221 ganged
.append("%s_outen" % outname
) # match wirefmt
223 gangedfmt
= '{%s} = duplicate(%s);'
224 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
225 return '\n'.join(res
) + '\n\n'
227 def wirefmt(self
, *args
):
228 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
232 def ifacepfmt(self
, *args
):
233 res
= '\n'.join(map(self
.ifacepfmtdecpin
, self
.pins
)).format(*args
)
234 return '\n' + res
# pins is a list
236 def ifacefmt(self
, *args
):
237 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
238 return '\n' + res
# pins is a list
240 def ifacepfmtdecfn(self
, name
):
243 def ifacefmtdecfn(self
, name
):
244 return name
# like: uart
246 def ifacefmtdecfn2(self
, name
):
247 return name
# like: uart
249 def ifacefmtdecfn3(self
, name
):
251 return "%s_outen" % name
# like uart_outen
253 def ifacefmtoutfn(self
, name
):
254 return "wr%s" % name
# like wruart
256 def ifacefmtinfn(self
, name
):
259 def wirefmtpin(self
, pin
):
260 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
263 def ifacepfmtdecpin(self
, pin
):
264 return pin
.ifacepfmt(self
.ifacepfmtdecfn
)
266 def ifacefmtdecpin(self
, pin
):
267 return pin
.ifacefmt(self
.ifacefmtdecfn
)
269 def ifacefmtpin(self
, pin
):
270 decfn
= self
.ifacefmtdecfn2
271 outfn
= self
.ifacefmtoutfn
272 # print pin, pin.outenmode
274 decfn
= self
.ifacefmtdecfn3
275 outfn
= self
.ifacefmtoutenfn
276 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
279 def ifacedef(self
, *args
):
280 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
281 res
= res
.format(*args
)
282 return '\n' + res
+ '\n'
285 class MuxInterface(Interface
):
287 def wirefmt(self
, *args
):
288 return muxwire
.format(*args
)
291 class IOInterface(Interface
):
293 def ifacefmtoutenfn(self
, name
):
294 return "cell{0}_mux_outen"
296 def ifacefmtoutfn(self
, name
):
297 """ for now strip off io{0}_ part """
298 return "cell{0}_mux_out"
300 def ifacefmtinfn(self
, name
):
301 return "cell{0}_mux_in"
303 def wirefmt(self
, *args
):
304 return generic_io
.format(*args
)
307 class Interfaces(InterfacesBase
, PeripheralInterfaces
):
308 """ contains a list of interface definitions
311 def __init__(self
, pth
=None):
312 InterfacesBase
.__init
__(self
, Interface
, pth
)
313 PeripheralInterfaces
.__init
__(self
)
315 def ifacedef(self
, f
, *args
):
316 for (name
, count
) in self
.ifacecount
:
317 for i
in range(count
):
318 f
.write(self
.data
[name
].ifacedef(i
))
320 def busfmt(self
, f
, *args
):
321 f
.write("import BUtils::*;\n\n")
322 for (name
, count
) in self
.ifacecount
:
323 for i
in range(count
):
324 bf
= self
.data
[name
].busfmt(i
)
327 def ifacepfmt(self
, f
, *args
):
329 // interface declaration between {0} and pinmux
330 (*always_ready,always_enabled*)
331 interface PeripheralSide{0};'''
332 for (name
, count
) in self
.ifacecount
:
333 f
.write(comment
.format(name
.upper()))
334 f
.write(self
.data
[name
].ifacepfmt(0))
335 f
.write("\n endinterface\n")
337 def ifacefmt(self
, f
, *args
):
339 // interface declaration between %s-{0} and pinmux'''
340 for (name
, count
) in self
.ifacecount
:
341 for i
in range(count
):
342 c
= comment
% name
.upper()
344 f
.write(self
.data
[name
].ifacefmt(i
))
346 def wirefmt(self
, f
, *args
):
347 comment
= '\n // following wires capture signals ' \
348 'to IO CELL if %s-{0} is\n' \
350 for (name
, count
) in self
.ifacecount
:
351 for i
in range(count
):
354 f
.write(self
.data
[name
].wirefmt(i
))
357 # ========= Interface declarations ================ #
359 mux_interface
= MuxInterface('cell',
360 [{'name': 'mux', 'ready': False, 'enabled': False,
361 'bitspec': '{1}', 'action': True}])
363 io_interface
= IOInterface(
365 [{'name': 'cell_out', 'enabled': True, },
366 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
367 {'name': 'cell_in', 'action': True, 'io': True}, ])
369 # == Peripheral Interface definitions == #
370 # these are the interface of the peripherals to the pin mux
371 # Outputs from the peripherals will be inputs to the pinmux
372 # module. Hence the change in direction for most pins
374 # ======================================= #
377 if __name__
== '__main__':
379 uartinterface_decl
= Interface('uart',
381 {'name': 'tx', 'action': True},
384 twiinterface_decl
= Interface('twi',
385 [{'name': 'sda', 'outen': True},
386 {'name': 'scl', 'outen': True},
389 def _pinmunge(p
, sep
, repl
, dedupe
=True):
390 """ munges the text so it's easier to compare.
391 splits by separator, strips out blanks, re-joins.
396 p
= filter(lambda x
: x
, p
) # filter out blanks
400 """ munges the text so it's easier to compare.
402 # first join lines by semicolons, strip out returns
404 p
= map(lambda x
: x
.replace('\n', ''), p
)
406 # now split first by brackets, then spaces (deduping on spaces)
407 p
= _pinmunge(p
, "(", " ( ", False)
408 p
= _pinmunge(p
, ")", " ) ", False)
409 p
= _pinmunge(p
, " ", " ")
415 for p1
, p2
in zip(l1
, l2
):
421 ifaces
= Interfaces()
423 ifaceuart
= ifaces
['uart']
424 print (ifaceuart
.ifacedef(0))
425 print (uartinterface_decl
.ifacedef(0))
426 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
428 ifacetwi
= ifaces
['twi']
429 print (ifacetwi
.ifacedef(0))
430 print (twiinterface_decl
.ifacedef(0))
431 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)