7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
203 ret
.append("//%s %s %s %s %s" % (name
, ptyp
, typ
, pname
, stype
))
205 sname
= self
.get_iname(count
)
206 ps
= "slow_peripherals.%s" % sname
208 sname
= self
.peripheral
.iname().format(count
)
209 ps
= "pinmux.peripheral_side.%s" % sname
210 n
= self
.get_iname(count
)
212 n
= "{0}.{1}".format(n
, stype
)
213 ps_
= "{0}.{1}".format(ps
, pname
)
214 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
215 pname
, ps_
, n
, stype
)
216 return '\n'.join(ret
)
218 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
219 pname
, ps
, n
, fname
):
221 ck
= self
.get_clock_reset(name
, count
)
223 if ck
== PBase
.get_clock_reset(self
, name
, count
):
224 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
225 .format(ps
, n
, fname
))
227 n2
= "{0}{1}".format(name
, count
)
228 sync
= '{0}_{1}_sync'.format(n2
, pname
)
229 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
231 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
232 .format(sync
, n
, fname
))
233 elif ctype
== 'outen':
234 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
237 if ck
== PBase
.get_clock_reset(self
, name
, count
):
238 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
241 n2
= "{0}{1}".format(name
, count
)
242 sync
= '{0}_{1}_sync'.format(n2
, pname
)
243 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
245 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
250 def _mk_clk_con(self
, name
, count
, ctype
):
252 ck
= self
.get_clock_reset(name
, count
)
253 if ck
== PBase
.get_clock_reset(self
, name
, count
):
256 spc
= self
.get_clk_spc(ctype
)
259 ck
= self
.get_clk_spc(ctype
)
261 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
263 for p
in self
.peripheral
.pinspecs
:
267 if typ
== 'out' or typ
== 'inout':
268 fname
= self
.pinname_out(pname
)
271 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
272 n_
= "{0}{1}".format(n
, count
)
275 n_
= '{0}_{1}'.format(n_
, pname
)
276 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
277 if typ
== 'in' or typ
== 'inout':
278 fname
= self
.pinname_in(pname
)
281 #fname = self.pinname_in(pname)
282 n_
= "{0}{1}".format(n
, count
)
283 n_
= '{0}_{1}'.format(n_
, pname
)
284 #n_ = self.ifname_tweak(pname, 'in', n_)
285 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
286 return '\n'.join(ret
)
288 def get_clk_spc(self
, ctype
):
290 return "sp_clock, sp_reset"
292 return "core_clock, core_reset"
294 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
295 ck
= self
.get_clock_reset(name
, count
)
296 if ck
== PBase
.get_clock_reset(self
, name
, count
):
299 spc
= self
.get_clk_spc(ctype
)
302 ck
= self
.get_clk_spc(ctype
)
304 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
307 n_
= "{0}{1}".format(name
, count
)
308 n_
= '{0}_{1}'.format(n_
, pname
)
309 if typ
== 'in' or typ
== 'inout':
311 return template
.format(bitspec
, n_
, ck
, spc
)
314 def mk_cellconn(self
, *args
):
317 def mkfast_peripheral(self
, size
=0):
320 def mkslow_peripheral(self
, size
=0):
323 def mksuffix(self
, name
, i
):
326 def __mk_connection(self
, con
, aname
, fabricname
):
327 txt
= "mkConnection ({2}.v_to_slaves\n" + \
328 " [fromInteger(valueOf({1}))],\n" + \
331 print "PBase __mk_connection", self
.name
, aname
334 return txt
.format(con
, aname
, fabricname
)
336 def __mk_master_connection(self
, con
, aname
, fabricname
):
337 txt
= "mkConnection ({0}, {2}.v_from_masters\n" + \
338 " [fromInteger(valueOf({1}))]);\n"
340 print "PBase __mk_master_connection", self
.name
, aname
343 return txt
.format(con
, aname
, fabricname
)
345 def mk_master_connection(self
, count
, fabricname
, typ
, name
=None):
346 if not self
.has_axi_master():
350 print "PBase mk_master_conn", self
.name
, count
351 aname
= self
.axi_master_name(name
, count
, typ
)
352 con
= self
._mk
_connection
(name
, count
, True).format(count
, aname
)
353 return self
.__mk
_master
_connection
(con
, aname
, fabricname
)
355 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
358 print "PBase mk_conn", self
.name
, count
359 aname
= self
.axi_slave_name(name
, count
, typ
)
360 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
361 return self
.__mk
_connection
(con
, aname
, fabricname
)
363 def _mk_connection(self
, name
=None, count
=0):
366 def pinname_out(self
, pname
):
369 def pinname_in(self
, pname
):
372 def pinname_outen(self
, pname
):
375 def ifname_tweak(self
, pname
, typ
, txt
):
378 def pinname_tweak(self
, pname
, typ
, txt
):
384 def mk_plic(self
, inum
, irq_offs
):
386 print "mk_plic", self
.name
, inum
, irq_offs
387 niq
= self
.num_irqs()
389 return ('', irq_offs
)
390 name
= self
.get_iname(inum
)
391 res
.append("// PLIC rules for {0}".format(name
))
392 for idx
in range(niq
):
393 plic_obj
= self
.plic_object(name
, idx
)
394 print "plic_obj", name
, idx
, plic_obj
395 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
397 irq_offs
+= 1 # increment to next irq
398 return ('\n'.join(res
), irq_offs
)
400 def mk_ext_ifacedef(self
, iname
, inum
):
403 def extfastifinstance(self
, name
, count
):
406 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
410 pname
= self
.get_iname(count
)
414 sname
= self
.peripheral
.iname().format(count
)
415 template
= "interface {0}{3} = {2}{1}{4};"
416 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
418 def extifinstance2(self
, name
, count
):
421 def extifinstance(self
, name
, count
):
422 return self
._extifinstance
(name
, count
, "",
423 "pinmux.peripheral_side.")
427 rule rl_connect_{0}_to_plic_{2};
428 if({1} == 1'b1) begin
429 ff_gateway_queue[{2}].enq(1);
430 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
435 axi_master_declarations
= """\
436 typedef 0 Dmem_master_num;
437 typedef 1 Imem_master_num;
439 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
441 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
443 typedef TAdd#(DMA_master_num,1)
447 axi_fastslave_declarations
= """\
449 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
450 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
452 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
454 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
456 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
458 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
460 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
461 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
463 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
466 axi_slave_declarations
= """\
467 typedef 0 SlowMaster;
469 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
471 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
473 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
475 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
478 pinmux_cellrule
= """\
479 rule connect_select_lines_pinmux;
485 class CallFn(object):
486 def __init__(self
, peripheral
, name
):
487 self
.peripheral
= peripheral
490 def __call__(self
, *args
):
491 #print "__call__", self.name, self.peripheral.slow, args
492 if not self
.peripheral
.slow
:
494 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
497 class PeripheralIface(object):
498 def __init__(self
, ifacename
):
500 slow
= slowfactory
.getcls(ifacename
)
501 print "Iface", ifacename
, slow
503 self
.slow
= slow(ifacename
)
504 self
.slow
.peripheral
= self
505 for fname
in ['slowimport',
507 'extifinstance2', 'extifinstance', 'extifdecl',
508 'slowifdecl', 'slowifdeclmux',
511 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
513 'mk_plic', 'mk_ext_ifacedef',
514 '_mk_clk_con', 'mk_ext_ifacedef',
515 'mk_connection', 'mk_master_connection',
516 'mk_cellconn', '_mk_pincon']:
517 fn
= CallFn(self
, fname
)
518 setattr(self
, fname
, types
.MethodType(fn
, self
))
520 #print "PeripheralIface"
523 def mksuffix(self
, name
, i
):
524 if self
.slow
is None:
526 return self
.slow
.mksuffix(name
, i
)
528 def axi_reg_def(self
, start
, count
):
531 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
533 def axi_master_idx(self
, start
, count
, typ
):
534 if not self
.slow
or not self
.slow
.has_axi_master():
536 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
538 def axi_slave_idx(self
, start
, count
, typ
):
541 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
543 def axi_fastaddr_map(self
, count
):
546 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
548 def axi_addr_map(self
, count
):
551 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
554 class PeripheralInterfaces(object):
556 self
.fastbusmode
= False
558 def slowimport(self
, *args
):
560 for (name
, count
) in self
.ifacecount
:
561 #print "slowimport", name, self.data[name].slowimport
562 ret
.append(self
.data
[name
].slowimport())
563 return '\n'.join(li(list(filter(None, ret
)), 4))
565 def extfastifinstance(self
, *args
):
567 for (name
, count
) in self
.ifacecount
:
568 for i
in range(count
):
569 iname
= self
.data
[name
].iname().format(i
)
570 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
571 if self
.is_on_fastbus(name
, i
):
573 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
574 return '\n'.join(li(list(filter(None, ret
)), 8))
576 def extifinstance2(self
, *args
):
578 for (name
, count
) in self
.ifacecount
:
579 for i
in range(count
):
580 iname
= self
.data
[name
].iname().format(i
)
581 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
582 return '\n'.join(li(list(filter(None, ret
)), 8))
584 def extifinstance(self
, *args
):
586 for (name
, count
) in self
.ifacecount
:
587 for i
in range(count
):
588 iname
= self
.data
[name
].iname().format(i
)
589 if not self
.is_on_fastbus(name
, i
):
591 ret
.append(self
.data
[name
].extifinstance(name
, i
))
592 return '\n'.join(li(list(filter(None, ret
)), 8))
594 def extifdecl(self
, *args
):
596 for (name
, count
) in self
.ifacecount
:
597 for i
in range(count
):
598 if not self
.is_on_fastbus(name
, i
):
600 ret
.append(self
.data
[name
].extifdecl(name
, i
))
601 return '\n'.join(li(list(filter(None, ret
)), 8))
603 def slowifdeclmux(self
, *args
):
605 for (name
, count
) in self
.ifacecount
:
606 for i
in range(count
):
607 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
608 return '\n'.join(li(list(filter(None, ret
)), 8))
610 def fastifdecl(self
, *args
):
612 for (name
, count
) in self
.ifacecount
:
613 for i
in range(count
):
614 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
615 if self
.is_on_fastbus(name
, i
):
617 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
618 return '\n'.join(li(list(filter(None, ret
)), 4))
620 def slowifdecl(self
, *args
):
622 for (name
, count
) in self
.ifacecount
:
623 for i
in range(count
):
624 if self
.is_on_fastbus(name
, i
):
626 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
627 return '\n'.join(list(filter(None, ret
)))
629 def axi_fastmem_def(self
, *args
):
630 return self
._axi
_reg
_def
(0x50000000, *args
)
632 def axi_reg_def(self
, *args
):
633 return self
._axi
_reg
_def
(0x00011100, *args
)
635 def _axi_reg_def(self
, start
, *args
):
637 for (name
, count
) in self
.ifacecount
:
638 for i
in range(count
):
639 if self
.is_on_fastbus(name
, i
):
641 x
= self
.data
[name
].axi_reg_def(start
, i
)
642 #print ("ifc", name, x)
646 return '\n'.join(list(filter(None, ret
)))
648 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
650 for (name
, count
) in self
.ifacecount
:
651 for i
in range(count
):
652 if self
.is_on_fastbus(name
, i
):
655 fn
= self
.data
[name
].axi_master_idx
657 fn
= self
.data
[name
].axi_slave_idx
658 (rdef
, offs
) = fn(start
, i
, idxtype
)
659 #print ("ifc", name, rdef, offs)
662 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
663 decls
= '\n'.join(list(filter(None, ret
)))
664 return template
.format(decls
)
666 def axi_slave_idx(self
, *args
):
667 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
670 def axi_fastslave_idx(self
, *args
):
671 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
674 def axi_master_idx(self
, *args
):
675 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
678 def axi_fastslave_idx(self
, *args
):
679 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
682 def axi_fastaddr_map(self
, *args
):
684 for (name
, count
) in self
.ifacecount
:
685 for i
in range(count
):
686 if self
.is_on_fastbus(name
, i
):
688 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
689 return '\n'.join(li(list(filter(None, ret
)), 8))
691 def axi_addr_map(self
, *args
):
693 for (name
, count
) in self
.ifacecount
:
694 for i
in range(count
):
695 if self
.is_on_fastbus(name
, i
):
697 ret
.append(self
.data
[name
].axi_addr_map(i
))
698 return '\n'.join(li(list(filter(None, ret
)), 8))
700 def mkfast_peripheral(self
, *args
):
702 for (name
, count
) in self
.ifacecount
:
703 for i
in range(count
):
704 if self
.is_on_fastbus(name
, i
):
706 #print "mkfast", name, count
707 x
= self
.data
[name
].mkfast_peripheral()
709 suffix
= self
.data
[name
].mksuffix(name
, i
)
710 ret
.append(x
.format(suffix
))
711 return '\n'.join(li(list(filter(None, ret
)), 8))
713 def mkslow_peripheral(self
, *args
):
715 for (name
, count
) in self
.ifacecount
:
716 for i
in range(count
):
717 if self
.is_on_fastbus(name
, i
):
719 #print "mkslow", name, count
720 x
= self
.data
[name
].mkslow_peripheral()
722 suffix
= self
.data
[name
].mksuffix(name
, i
)
723 ret
.append(x
.format(suffix
))
724 return '\n'.join(li(list(filter(None, ret
)), 8))
726 def _mk_connection(self
, fabric
, typ
, indent
, master
, *args
):
728 for (name
, count
) in self
.ifacecount
:
729 for i
in range(count
):
730 if self
.is_on_fastbus(name
, i
):
733 txt
= self
.data
[name
].mk_master_connection(i
, fabric
, typ
)
735 txt
= self
.data
[name
].mk_connection(i
, fabric
, typ
)
739 return '\n'.join(li(list(filter(None, ret
)), indent
))
741 def mk_master_connection(self
, *args
):
742 return self
._mk
_connection
("fabric", "fast", 8, True, *args
)
744 def mk_fast_connection(self
, *args
):
745 return self
._mk
_connection
("fabric", "fast", 12, False, *args
)
747 def mk_connection(self
, *args
):
748 return self
._mk
_connection
("slow_fabric", "", 8, False, *args
)
750 def mk_cellconn(self
):
753 for (name
, count
) in self
.ifacecount
:
754 for i
in range(count
):
755 if self
.is_on_fastbus(name
, i
):
757 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
760 (txt
, cellcount
) = res
762 ret
= li('\n'.join(list(filter(None, ret
))), 4)
763 return li(pinmux_cellrule
.format(ret
), 4)
766 return self
._mk
_pincon
("slow")
768 def mk_fast_pincon(self
):
769 return self
._mk
_pincon
("fast")
771 def _mk_pincon(self
, typ
):
773 for (name
, count
) in self
.ifacecount
:
774 for i
in range(count
):
775 if self
.is_on_fastbus(name
, i
):
777 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
779 return '\n'.join(li(list(filter(None, ret
)), 4))
781 def mk_dma_irq(self
):
789 for (name
, count
) in self
.ifacecount
:
791 for i
in range(count
):
792 if not self
.is_on_fastbus(name
, i
):
794 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
798 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
799 ifacerules
.append(txt
)
800 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
802 ifacerules
= list(filter(None, ifacerules
))
804 txt
= "rule synchronize_%s_interrupts;" % name
807 rules
.append("endrule")
809 cnct
= list(filter(None, cnct
))
811 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
812 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
815 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
817 cnct
.append(" dma.interrupt_from_peripherals(\n" +
818 " lv_interrupt_to_DMA);")
819 cnct
.append("endrule;")
821 ret
= list(filter(None, sync
+ rules
+ cnct
))
823 return '\n'.join(ret
)
825 def num_dmachannels(self
):
826 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
828 def mk_ext_ifacedef(self
):
830 for (name
, count
) in self
.ifacecount
:
831 for i
in range(count
):
832 if self
.is_on_fastbus(name
, i
):
834 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
836 return '\n'.join(li(list(filter(None, ret
)), 8))
840 irq_offs
= 8 # XXX: DMA scovers 0-7?
841 for (name
, count
) in self
.ifacecount
:
842 for i
in range(count
):
843 if self
.is_on_fastbus(name
, i
):
845 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
848 (txt
, irq_offs
) = res
850 self
.num_slow_irqs
= irq_offs
851 return '\n'.join(li(list(filter(None, ret
)), 4))
853 def mk_sloirqsdef(self
):
854 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
856 def mk_fastclk_con(self
):
857 return self
._mk
_clk
_con
("fast")
859 def mk_slowclk_con(self
):
860 return self
._mk
_clk
_con
("slow")
862 def _mk_clk_con(self
, ctype
):
864 for (name
, count
) in self
.ifacecount
:
865 for i
in range(count
):
866 if self
.is_on_fastbus(name
, i
):
868 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
870 return '\n'.join(li(list(filter(None, ret
)), 8))
872 def is_on_fastbus(self
, name
, i
):
873 #print "fastbus mode", self.fastbusmode, name, i
874 iname
= self
.data
[name
].iname().format(i
)
876 return iname
not in self
.fastbus
877 return iname
in self
.fastbus
880 class PFactory(object):
881 def getcls(self
, name
):
882 from uart
import uart
883 from quart
import quart
884 from sdmmc
import sdmmc
886 from eint
import eint
887 from rs232
import rs232
889 from eint
import eint
890 from jtag
import jtag
891 from spi
import spi
, mspi
892 from qspi
import qspi
, mqspi
893 from gpio
import gpio
894 from rgbttl
import rgbttl
895 from flexbus
import flexbus
897 for k
, v
in {'uart': uart
,
913 if name
.startswith(k
):
918 slowfactory
= PFactory()
920 if __name__
== '__main__':
924 i
= PeripheralIface('uart')
926 i
= PeripheralIface('gpioa')