7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
23 class MMapConfig(object):
25 def get_mmap_configs(self
):
27 for cfg
in self
.peripheral
.configs
:
28 res
.append(cfg
.get('mmap', None))
29 # XXX HACK! assume all configs same for each peripheral!
32 def map_to_idx(self
, cfg
, idx
):
33 if isinstance(idx
, int):
35 for (i
, c
) in enumerate(cfg
):
38 assert "config name %s not found" % s
40 def get_mmap_cfg_start(self
, idx
):
41 cfg
= self
.get_mmap_configs()
43 nregs
= self
.num_axi_regs32()
44 if isinstance(nregs
, int) or len(nregs
) == 1:
47 idx
= self
.map_to_idx(cfg
, idx
)
50 def get_mmap_cfg_name(self
, idx
):
51 cfg
= self
.get_mmap_configs()
53 nregs
= self
.num_axi_regs32()
54 if isinstance(nregs
, int) or len(nregs
) == 1:
59 def num_axi_regs32cfg(self
):
60 cfg
= self
.get_mmap_configs()
62 return self
.num_axi_regs32()
69 class PBase(MMapConfig
):
70 def __init__(self
, name
):
72 MMapConfig
.__init
__(self
)
74 def extifdecl(self
, name
, count
):
75 sname
= self
.get_iname(count
)
76 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
78 def has_axi_master(self
):
84 def mk_dma_irq(self
, name
, count
):
85 if not self
.irq_name():
87 sname
= self
.get_iname(count
)
88 return "{0}_interrupt".format(sname
)
90 def mk_dma_rule(self
, name
, count
):
91 irqname
= self
.mk_dma_irq(name
, count
)
94 pirqname
= self
.irq_name().format(count
)
95 template
= " {0}.send(\n" + \
96 " slow_peripherals.{1});"
97 return template
.format(irqname
, pirqname
)
99 def get_clock_reset(self
, name
, count
):
100 return "slow_clock,slow_reset"
102 def mk_dma_sync(self
, name
, count
):
103 irqname
= self
.mk_dma_irq(name
, count
)
106 sname
= self
.peripheral
.iname().format(count
)
107 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
108 " <-mkSyncBitToCC({1});"
109 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
111 def mk_dma_connect(self
, name
, count
):
112 irqname
= self
.mk_dma_irq(name
, count
)
115 return "{0}.read".format(irqname
)
117 def fastifdecl(self
, name
, count
):
120 def slowifdeclmux(self
, name
, count
):
123 def slowimport(self
):
126 def num_axi_regs32(self
):
129 def slowifdecl(self
):
132 def get_iname(self
, inum
):
133 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
135 def axibase(self
, name
, ifacenum
, idx
):
137 return "%(name)s%(ifacenum)d%(idx)sBase" % locals()
139 def axiend(self
, name
, ifacenum
, idx
):
141 return "%(name)s%(ifacenum)d%(idx)sEnd" % locals()
143 def _axi_reg_def(self
, idx
, numregs
, start
, name
, ifacenum
):
145 offs
= numregs
* 4 * 16
148 cfgstart
= self
.get_mmap_cfg_start(idx
)
151 end
= start
+ offs
- 1
152 offs
= 0 # don't do contiguous addressing
154 end
= start
+ offs
- 1
155 bname
= self
.axibase(name
, ifacenum
, idx
)
156 bend
= self
.axiend(name
, ifacenum
, idx
)
157 comment
= "%d 32-bit regs" % numregs
158 return ("`define %(bname)s 'h%(start)08X\n"
159 "`define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
162 def axi_reg_def(self
, start
, name
, ifacenum
):
163 offs
= self
.num_axi_regs32cfg()
166 if not isinstance(offs
, list):
171 for (idx
, nregs
) in enumerate(offs
):
172 cfg
= self
.get_mmap_cfg_name(idx
)
173 (txt
, off
) = self
._axi
_reg
_def
(cfg
, nregs
, start
, name
, ifacenum
)
177 return ('\n'.join(res
), offstotal
)
179 def axi_master_name(self
, name
, ifacenum
, typ
=''):
181 return "{0}{1}_master_num".format(name
, ifacenum
)
183 def axi_slave_name(self
, idx
, name
, ifacenum
, typ
=''):
185 return "{0}{1}{3}_{2}slave_num".format(name
, ifacenum
, typ
, idx
)
187 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
188 name
= self
.axi_master_name(name
, ifacenum
, typ
)
189 return ("typedef {0} {1};".format(idx
, name
), 1)
191 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
192 offs
= self
.num_axi_regs32()
195 if not isinstance(offs
, list):
198 for (i
, nregs
) in enumerate(offs
):
199 cfg
= self
.get_mmap_cfg_name(i
)
200 name_
= self
.axi_slave_name(cfg
, name
, ifacenum
, typ
)
201 res
.append("typedef {0} {1};".format(idx
+ i
, name_
))
202 return ('\n'.join(res
), len(offs
))
204 def axi_fastaddr_map(self
, name
, ifacenum
):
205 return self
.axi_addr_map(name
, ifacenum
, 'fast')
207 def _axi_addr_map(self
, idx
, name
, ifacenum
, typ
=""):
208 bname
= self
.axibase(name
, ifacenum
, idx
)
209 bend
= self
.axiend(name
, ifacenum
, idx
)
210 name
= self
.axi_slave_name(idx
, name
, ifacenum
, typ
)
212 if(addr>=`{0} && addr<=`{1})
213 return tuple2(True,fromInteger(valueOf({2})));
215 return template
.format(bname
, bend
, name
)
217 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
218 offs
= self
.num_axi_regs32()
221 if not isinstance(offs
, list):
224 for (idx
, nregs
) in enumerate(offs
):
225 cfg
= self
.get_mmap_cfg_name(idx
)
226 res
.append(self
._axi
_addr
_map
(cfg
, name
, ifacenum
, typ
))
227 return '\n'.join(res
)
229 def _mk_pincon(self
, name
, count
, ptyp
):
230 # TODO: really should be using bsv.interface_decl.Interfaces
231 # pin-naming rules.... logic here is hard-coded to duplicate
232 # it (see Interface.__init__ outen)
234 for p
in self
.peripheral
.pinspecs
:
237 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
238 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
239 ret
.append("//%s %s" % (n
, str(p
)))
241 sname
= self
.get_iname(count
)
242 sname
= "{0}.{1}".format(sname
, pname
)
243 ps
= "slow_peripherals.%s" % sname
245 sname
= self
.peripheral
.iname().format(count
)
246 sname
= "{0}.{1}".format(sname
, pname
)
247 ps
= "pinmux.peripheral_side.%s" % sname
248 if typ
== 'out' or typ
== 'inout':
249 fname
= self
.pinname_out(pname
)
250 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
251 n_
= "{0}{1}".format(n
, count
)
259 cn
= self
._mk
_actual
_connection
('out', name
,
261 pname
, ps_
, n_
, fname
)
265 fname
= self
.pinname_outen(pname
)
267 if isinstance(fname
, str):
268 fname
= "{0}.{1}".format(n_
, fname
)
269 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
270 cn
= self
._mk
_actual
_connection
('outen', name
,
274 if typ
== 'in' or typ
== 'inout':
275 fname
= self
.pinname_in(pname
)
281 n_
= "{0}{1}".format(n
, count
)
282 n_
= '{0}.{1}'.format(n_
, fname
)
283 n_
= self
.ifname_tweak(pname
, 'in', n_
)
284 cn
= self
._mk
_actual
_connection
('in', name
,
286 pname
, ps_
, n_
, fname
)
288 return '\n'.join(ret
)
290 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
294 ret
.append("//%s %s %s %s %s" % (name
, ptyp
, typ
, pname
, stype
))
296 sname
= self
.get_iname(count
)
297 ps
= "slow_peripherals.%s" % sname
299 sname
= self
.peripheral
.iname().format(count
)
300 ps
= "pinmux.peripheral_side.%s" % sname
301 n
= self
.get_iname(count
)
303 n
= "{0}.{1}".format(n
, stype
)
304 ps_
= "{0}.{1}".format(ps
, pname
)
305 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
306 pname
, ps_
, n
, stype
)
307 return '\n'.join(ret
)
309 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
310 pname
, ps
, n
, fname
):
312 ck
= self
.get_clock_reset(name
, count
)
314 if ck
== PBase
.get_clock_reset(self
, name
, count
):
315 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
316 .format(ps
, n
, fname
))
318 n2
= "{0}{1}".format(name
, count
)
319 sync
= '{0}_{1}_sync'.format(n2
, pname
)
320 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
322 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
323 .format(sync
, n
, fname
))
324 elif ctype
== 'outen':
325 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
328 if ck
== PBase
.get_clock_reset(self
, name
, count
):
329 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
332 n2
= "{0}{1}".format(name
, count
)
333 sync
= '{0}_{1}_sync'.format(n2
, pname
)
334 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
336 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
340 def _mk_clk_con(self
, name
, count
, ctype
):
342 ck
= self
.get_clock_reset(name
, count
)
343 if ck
== PBase
.get_clock_reset(self
, name
, count
):
346 spc
= self
.get_clk_spc(ctype
)
349 ck
= self
.get_clk_spc(ctype
)
350 template
= "Ifc_sync#({0}) {1}_sync <-mksyncconnection(\n" + \
352 for p
in self
.peripheral
.pinspecs
:
356 if typ
== 'out' or typ
== 'inout':
357 fname
= self
.pinname_out(pname
)
360 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
361 n_
= "{0}{1}".format(n
, count
)
364 n_
= '{0}_{1}'.format(n_
, pname
)
365 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
366 if typ
== 'in' or typ
== 'inout':
367 fname
= self
.pinname_in(pname
)
370 #fname = self.pinname_in(pname)
371 n_
= "{0}{1}".format(n
, count
)
372 n_
= '{0}_{1}'.format(n_
, pname
)
373 #n_ = self.ifname_tweak(pname, 'in', n_)
374 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
375 return '\n'.join(ret
)
377 def get_clk_spc(self
, ctype
):
379 return "sp_clock, sp_reset"
381 return "core_clock, core_reset"
383 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
384 ck
= self
.get_clock_reset(name
, count
)
385 if ck
== PBase
.get_clock_reset(self
, name
, count
):
388 spc
= self
.get_clk_spc(ctype
)
391 ck
= self
.get_clk_spc(ctype
)
392 template
= "Ifc_sync#({0}) {1}_sync <-mksyncconnection(\n" + \
395 n_ = "{0}{1}
".format(name, count)
396 n_ = '{0}_{1}'.format(n_, pname)
397 if typ == 'in' or typ == 'inout':
399 return template.format(bitspec, n_, ck, spc)
401 def mk_cellconn(self, *args):
404 def mkfast_peripheral(self, size=0):
407 def mkslow_peripheral(self, size=0):
410 def mksuffix(self, name, i):
413 def __mk_connection(self, con, aname, count, fabricname):
414 txt = "mkConnection ({2}
.v_to_slaves
\n" + \
415 " [fromInteger(valueOf({1}
))],\n" + \
418 print "PBase __mk_connection
", self.name, aname
421 con = con.format(count, aname)
422 return txt.format(con, aname, fabricname)
424 def __mk_master_connection(self, con, aname, count, fabricname):
425 txt = "mkConnection ({0}
, {2}
.v_from_masters
\n" + \
426 " [fromInteger(valueOf({1}
))]);\n"
428 print "PBase __mk_master_connection
", self.name, aname
431 con = con.format(count, aname)
432 return txt.format(con, aname, fabricname)
434 def mk_master_connection(self, count, fabricname, typ, name=None):
435 if not self.has_axi_master():
439 print "PBase mk_master_conn
", self.name, count
440 aname = self.axi_master_name(name, count, typ)
442 connections = self._mk_connection(name, count, True)
443 if not isinstance(connections, list):
444 connections = [connections]
445 for con in connections:
446 ret.append(self.__mk_master_connection(con, aname, count,
448 return '\n'.join(ret)
450 def mk_connection(self, count, fabricname, typ, name=None):
453 print "PBase mk_conn
", self.name, count
455 connections = self._mk_connection(name, count)
456 if not isinstance(connections, list):
457 connections = [connections]
458 for (idx, con) in enumerate(connections):
459 cfg = self.get_mmap_cfg_name(idx)
460 aname = self.axi_slave_name(cfg, name, count, typ)
461 ret.append(self.__mk_connection(con, aname, count, fabricname))
462 return '\n'.join(ret)
464 def _mk_connection(self, name=None, count=0):
467 def pinname_out(self, pname):
470 def pinname_in(self, pname):
473 def pinname_outen(self, pname):
476 def ifname_tweak(self, pname, typ, txt):
479 def pinname_tweak(self, pname, typ, txt):
485 def mk_plic(self, inum, irq_offs):
487 print "mk_plic
", self.name, inum, irq_offs
488 niq = self.num_irqs()
490 return ('', irq_offs)
491 name = self.get_iname(inum)
492 res.append("// PLIC rules
for {0}
".format(name))
493 for idx in range(niq):
494 plic_obj = self.plic_object(name, idx)
495 print "plic_obj
", name, idx, plic_obj
496 plic = mkplic_rule.format(name, plic_obj, irq_offs)
498 irq_offs += 1 # increment to next irq
499 return ('\n'.join(res), irq_offs)
501 def mk_ext_ifacedef(self, iname, inum):
504 def extfastifinstance(self, name, count):
507 def _extifinstance(self, name, count, suffix, prefix, samename=False,
511 pname = self.get_iname(count)
515 sname = self.peripheral.iname().format(count)
516 template = "interface {0}{3}
= {2}{1}{4}
;"
517 return template.format(pname, sname, prefix, suffix, ifsuffix)
519 def extifinstance2(self, name, count):
522 def extifinstance(self, name, count):
523 return self._extifinstance(name, count, "",
524 "pinmux
.peripheral_side
.")
528 rule rl_connect_{0}_to_plic_{2};
529 if({1} == 1'b1) begin
530 ff_gateway_queue[{2}].enq(1);
531 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
536 axi_master_declarations = """\
537 typedef 0 Dmem_master_num;
538 typedef 1 Imem_master_num;
540 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
542 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
544 typedef TAdd#(DMA_master_num,1)
548 axi_fastslave_declarations = """\
550 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
551 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
553 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
555 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
557 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
559 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
561 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
562 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
564 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
567 axi_slave_declarations = """\
568 typedef 0 SlowMaster;
570 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
572 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
574 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
576 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
579 pinmux_cellrule = """\
580 rule connect_select_lines_pinmux;
586 class CallFn(object):
587 def __init__(self, peripheral, name):
588 self.peripheral = peripheral
591 def __call__(self, *args):
592 #print "__call__
", self.name, self.peripheral.slow, args
593 if not self.peripheral.slow:
595 return getattr(self.peripheral.slow, self.name)(*args[1:])
598 class PeripheralIface(object):
599 def __init__(self, ifacename):
601 slow = slowfactory.getcls(ifacename)
602 print "Iface
", ifacename, slow
604 self.slow = slow(ifacename)
605 self.slow.peripheral = self
606 for fname in ['slowimport',
608 'extifinstance2', 'extifinstance', 'extifdecl',
609 'slowifdecl', 'slowifdeclmux',
612 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
614 'mk_plic', 'mk_ext_ifacedef',
615 '_mk_clk_con', 'mk_ext_ifacedef',
616 'mk_connection', 'mk_master_connection',
617 'mk_cellconn', '_mk_pincon']:
618 fn = CallFn(self, fname)
619 setattr(self, fname, types.MethodType(fn, self))
621 #print "PeripheralIface
"
624 def mksuffix(self, name, i):
625 if self.slow is None:
627 return self.slow.mksuffix(name, i)
629 def axi_reg_def(self, start, count):
632 return self.slow.axi_reg_def(start, self.ifacename, count)
634 def axi_master_idx(self, start, count, typ):
635 if not self.slow or not self.slow.has_axi_master():
637 return self.slow.axi_master_idx(start, self.ifacename, count, typ)
639 def axi_slave_idx(self, start, count, typ):
642 return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
644 def axi_fastaddr_map(self, count):
647 return self.slow.axi_fastaddr_map(self.ifacename, count)
649 def axi_addr_map(self, count):
652 return self.slow.axi_addr_map(self.ifacename, count)
655 class PeripheralInterfaces(object):
657 self.fastbusmode = False
659 def slowimport(self, *args):
661 for (name, count) in self.ifacecount:
662 #print "slowimport
", name, self.data[name].slowimport
663 ret.append(self.data[name].slowimport())
664 return '\n'.join(li(list(filter(None, ret)), 4))
666 def extfastifinstance(self, *args):
668 for (name, count) in self.ifacecount:
669 for i in range(count):
670 if self.is_on_fastbus(name, i):
672 ret.append(self.data[name].extfastifinstance(name, i))
673 return '\n'.join(li(list(filter(None, ret)), 8))
675 def extifinstance2(self, *args):
677 for (name, count) in self.ifacecount:
678 for i in range(count):
679 ret.append(self.data[name].extifinstance2(name, i))
680 return '\n'.join(li(list(filter(None, ret)), 8))
682 def extifinstance(self, *args):
684 for (name, count) in self.ifacecount:
685 for i in range(count):
686 if not self.is_on_fastbus(name, i):
688 ret.append(self.data[name].extifinstance(name, i))
689 return '\n'.join(li(list(filter(None, ret)), 8))
691 def extifdecl(self, *args):
693 for (name, count) in self.ifacecount:
694 for i in range(count):
695 if not self.is_on_fastbus(name, i):
697 ret.append(self.data[name].extifdecl(name, i))
698 return '\n'.join(li(list(filter(None, ret)), 8))
700 def slowifdeclmux(self, *args):
702 for (name, count) in self.ifacecount:
703 for i in range(count):
704 ret.append(self.data[name].slowifdeclmux(name, i))
705 return '\n'.join(li(list(filter(None, ret)), 8))
707 def fastifdecl(self, *args):
709 for (name, count) in self.ifacecount:
710 for i in range(count):
711 print "fastifdecl
", name, i, self.is_on_fastbus(name, i)
712 if self.is_on_fastbus(name, i):
714 ret.append(self.data[name].fastifdecl(name, i))
715 return '\n'.join(li(list(filter(None, ret)), 4))
717 def slowifdecl(self, *args):
719 for (name, count) in self.ifacecount:
720 for i in range(count):
721 if self.is_on_fastbus(name, i):
723 ret.append(self.data[name].slowifdecl().format(i, name))
724 return '\n'.join(list(filter(None, ret)))
726 def axi_fastmem_def(self, *args):
727 return self._axi_reg_def(0x50000000, *args)
729 def axi_reg_def(self, *args):
730 return self._axi_reg_def(0x00011100, *args)
732 def _axi_reg_def(self, start, *args):
734 for (name, count) in self.ifacecount:
735 for i in range(count):
736 if self.is_on_fastbus(name, i):
738 x = self.data[name].axi_reg_def(start, i)
739 #print ("ifc
", name, x)
743 return '\n'.join(list(filter(None, ret)))
745 def _axi_num_idx(self, start, template, typ, idxtype, *args):
747 for (name, count) in self.ifacecount:
748 for i in range(count):
749 if self.is_on_fastbus(name, i):
752 fn = self.data[name].axi_master_idx
754 fn = self.data[name].axi_slave_idx
755 (rdef, offs) = fn(start, i, idxtype)
756 #print ("ifc
", name, rdef, offs)
759 ret.append("typedef
%d LastGen_
%s_num
;" % (start - 1, typ))
760 decls = '\n'.join(list(filter(None, ret)))
761 return template.format(decls)
763 def axi_slave_idx(self, *args):
764 return self._axi_num_idx(0, axi_slave_declarations, 'slave',
767 def axi_fastslave_idx(self, *args):
768 return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
771 def axi_master_idx(self, *args):
772 return self._axi_num_idx(2, axi_master_declarations, 'master',
775 def axi_fastslave_idx(self, *args):
776 return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
779 def axi_fastaddr_map(self, *args):
781 for (name, count) in self.ifacecount:
782 for i in range(count):
783 if self.is_on_fastbus(name, i):
785 ret.append(self.data[name].axi_fastaddr_map(i))
786 return '\n'.join(li(list(filter(None, ret)), 8))
788 def axi_addr_map(self, *args):
790 for (name, count) in self.ifacecount:
791 for i in range(count):
792 if self.is_on_fastbus(name, i):
794 ret.append(self.data[name].axi_addr_map(i))
795 return '\n'.join(li(list(filter(None, ret)), 8))
797 def mkfast_peripheral(self, *args):
799 for (name, count) in self.ifacecount:
800 for i in range(count):
801 if self.is_on_fastbus(name, i):
803 #print "mkfast
", name, count
804 x = self.data[name].mkfast_peripheral()
806 suffix = self.data[name].mksuffix(name, i)
807 ret.append(x.format(suffix))
808 return '\n'.join(li(list(filter(None, ret)), 8))
810 def mkslow_peripheral(self, *args):
812 for (name, count) in self.ifacecount:
813 for i in range(count):
814 if self.is_on_fastbus(name, i):
816 #print "mkslow
", name, count
817 x = self.data[name].mkslow_peripheral()
819 suffix = self.data[name].mksuffix(name, i)
820 ret.append(x.format(suffix))
821 return '\n'.join(li(list(filter(None, ret)), 8))
823 def _mk_connection(self, fabric, typ, indent, master, *args):
825 for (name, count) in self.ifacecount:
826 for i in range(count):
827 if self.is_on_fastbus(name, i):
830 txt = self.data[name].mk_master_connection(i, fabric, typ)
832 txt = self.data[name].mk_connection(i, fabric, typ)
836 return '\n'.join(li(list(filter(None, ret)), indent))
838 def mk_master_connection(self, *args):
839 return self._mk_connection("fabric
", "fast
", 8, True, *args)
841 def mk_fast_connection(self, *args):
842 return self._mk_connection("fabric
", "fast
", 12, False, *args)
844 def mk_connection(self, *args):
845 return self._mk_connection("slow_fabric
", "", 8, False, *args)
847 def mk_cellconn(self):
850 for (name, count) in self.ifacecount:
851 for i in range(count):
852 if self.is_on_fastbus(name, i):
854 res = self.data[name].mk_cellconn(cellcount, name, i)
857 (txt, cellcount) = res
859 ret = li('\n'.join(list(filter(None, ret))), 4)
860 return li(pinmux_cellrule.format(ret), 4)
863 return self._mk_pincon("slow
")
865 def mk_fast_pincon(self):
866 return self._mk_pincon("fast
")
868 def _mk_pincon(self, typ):
870 for (name, count) in self.ifacecount:
871 for i in range(count):
872 if self.is_on_fastbus(name, i):
874 txt = self.data[name]._mk_pincon(name, i, typ)
876 return '\n'.join(li(list(filter(None, ret)), 4))
878 def mk_dma_irq(self):
886 for (name, count) in self.ifacecount:
888 for i in range(count):
889 if not self.is_on_fastbus(name, i):
891 txt = self.data[name].mk_dma_sync(name, i)
895 txt = self.data[name].mk_dma_rule(name, i)
896 ifacerules.append(txt)
897 txt = self.data[name].mk_dma_connect(name, i)
899 ifacerules = list(filter(None, ifacerules))
901 txt = "rule synchronize_
%s_interrupts
;" % name
904 rules.append("endrule
")
906 cnct = list(filter(None, cnct))
908 _cnct = ["rule rl_connect_interrupt_to_DMA
;",
909 " Bit
#(%d) lv_interrupt_to_DMA={" % ct]
912 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
914 cnct
.append(" dma.interrupt_from_peripherals(\n" +
915 " lv_interrupt_to_DMA);")
916 cnct
.append("endrule;")
918 ret
= list(filter(None, sync
+ rules
+ cnct
))
920 return '\n'.join(ret
)
922 def num_dmachannels(self
):
923 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
925 def mk_ext_ifacedef(self
):
927 for (name
, count
) in self
.ifacecount
:
928 for i
in range(count
):
929 if self
.is_on_fastbus(name
, i
):
931 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
933 return '\n'.join(li(list(filter(None, ret
)), 8))
937 irq_offs
= 8 # XXX: DMA scovers 0-7?
938 for (name
, count
) in self
.ifacecount
:
939 for i
in range(count
):
940 if self
.is_on_fastbus(name
, i
):
942 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
945 (txt
, irq_offs
) = res
947 self
.num_slow_irqs
= irq_offs
948 return '\n'.join(li(list(filter(None, ret
)), 4))
950 def mk_sloirqsdef(self
):
951 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
953 def mk_fastclk_con(self
):
954 return self
._mk
_clk
_con
("fast")
956 def mk_slowclk_con(self
):
957 return self
._mk
_clk
_con
("slow")
959 def _mk_clk_con(self
, ctype
):
961 for (name
, count
) in self
.ifacecount
:
962 for i
in range(count
):
963 if self
.is_on_fastbus(name
, i
):
965 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
967 return '\n'.join(li(list(filter(None, ret
)), 8))
969 def is_on_fastbus(self
, name
, i
):
970 #print "fastbus mode", self.fastbusmode, name, i
971 iname
= self
.data
[name
].iname().format(i
)
973 return iname
not in self
.fastbus
974 return iname
in self
.fastbus
977 class PFactory(object):
978 def getcls(self
, name
):
979 from uart
import uart
980 from quart
import quart
981 from sdmmc
import sdmmc
982 from emmc
import emmc
984 from eint
import eint
985 from rs232
import rs232
987 from eint
import eint
988 from jtag
import jtag
989 from spi
import spi
, mspi
990 from qspi
import qspi
, mqspi
991 from gpio
import gpio
992 from rgbttl
import rgbttl
993 from flexbus
import flexbus
994 from sdram
import sdram
996 for k
, v
in {'uart': uart
,
1014 if name
.startswith(k
):
1019 slowfactory
= PFactory()
1021 if __name__
== '__main__':
1023 print p
.slowimport()
1024 print p
.slowifdecl()
1025 i
= PeripheralIface('uart')
1027 i
= PeripheralIface('gpioa')