1 from bsv
.peripheral_gen
.base
import PBase
7 return "import quart :: *;"
10 return "quart{0}_intr"
13 return "interface QUART_AXI4_Lite_Ifc quart{0};\n" + \
14 "method Bit#(1) %s;" % self
.irq_name()
16 def get_clock_reset(self
, name
, count
):
17 return "uart_clock,uart_reset"
19 def num_axi_regs32(self
):
22 def mkslow_peripheral(self
, size
=0):
23 return "QUART_AXI4_Lite_Ifc quart{0} <- \n" + \
24 " mkQUART(clocked_by uart_clock,\n" + \
25 " reset_by uart_reset, sp_clock, sp_reset);"
27 def _mk_connection(self
, name
=None, count
=0):
28 return "quart{0}.slave"
30 def pinname_out(self
, pname
):
31 return {'tx': 'out.stx_out',
35 def pinname_in(self
, pname
):
36 return {'rx': 'out.srx_in',
40 def __disabled_mk_pincon(self
, name
, count
):
41 ret
= [PBase
.mk_pincon(self
, name
, count
)]
42 ret
.append("rule con_%s%d_io_in;" % (name
, count
))
43 ret
.append(" {0}{1}.out.modem_input(".format(name
, count
))
44 for idx
, pname
in enumerate(['rx', 'cts']):
45 sname
= self
.peripheral
.pname(pname
).format(count
)
46 ps
= "pinmux.peripheral_side.%s" % sname
47 ret
.append(" {0},".format(ps
))
48 ret
.append(" 1'b1,1'b0,1'b1")
57 def plic_object(self
, pname
, idx
):
58 return "{0}_interrupt.read".format(pname
)
60 def mk_plic(self
, inum
, irq_offs
):
61 name
= self
.get_iname(inum
)
62 ret
= [uart_plic_template
.format(name
, irq_offs
)]
63 (ret2
, irq_offs
) = PBase
.mk_plic(self
, inum
, irq_offs
)
65 return ('\n'.join(ret
), irq_offs
)
67 def mk_ext_ifacedef(self
, iname
, inum
):
68 name
= self
.get_iname(inum
)
69 return "method {0}_intr = {0}.irq;".format(name
)
71 def slowifdeclmux(self
, name
, count
):
72 sname
= self
.peripheral
.iname().format(count
)
73 return "method Bit#(1) %s_intr;" % sname
76 uart_plic_template
= """\
77 // PLIC {0} synchronisation with irq {1}
78 SyncBitIfc#(Bit#(1)) {0}_interrupt <-
79 mkSyncBitToCC(uart_clock, uart_reset);
80 rule plic_synchronize_{0}_interrupt_{1};
81 {0}_interrupt.send({0}.irq);