1 from bsv
.peripheral_gen
.base
import PBase
7 return "import sdr_top::*;"
9 def num_axi_regs32(self
):
10 return [0x400000, # defines an entire memory range (hack...)
11 12] # defines the number of configuration regs
13 def extfastifinstance(self
, name
, count
):
14 return "// TODO" + self
._extifinstance
(name
, count
, "_out", "", True,
17 def fastifdecl(self
, name
, count
):
18 return "// (*always_ready*) interface " + \
19 "Ifc_sdram_out sdr{0}_out;".format(count
)
21 def get_clock_reset(self
, name
, count
):
22 return "slow_clock, slow_reset"
24 def mkfast_peripheral(self
):
25 return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
27 def _mk_connection(self
, name
=None, count
=0):
28 return ["sdr{0}.axi4_slave_sdram",
29 "sdr{0}.axi4_slave_cntrl_reg"]
32 def pinname_in(self
, pname
):
33 return {'ta': 'sdram_side.m_tAn',
36 def pinname_out(self
, pname
):
37 return {'ale': 'sdram_side.m_ALE',
38 'oe': 'sdram_side.m_OEn',
39 'tbst': 'sdram_side.m_TBSTn',
40 'rw': 'sdram_side.m_R_Wn',
43 def _mk_clk_con(self
, name
, count
, ctype
):
44 ret
= [PBase
._mk
_clk
_con
(self
, name
, count
, ctype
)]
45 for pname
, sz
, ptype
in [
49 ('ad_out', 32, 'out'),
51 ('ad_out_en', 32, 'out'),
53 bitspec
= "Bit#(%d)" % sz
54 txt
= self
._mk
_clk
_vcon
(name
, count
, ctype
, ptype
, pname
, bitspec
)
58 def _mk_pincon(self
, name
, count
, typ
):
59 ret
= [PBase
._mk
_pincon
(self
, name
, count
, typ
)]
60 assert typ
== 'fast' # TODO slow?
61 for pname
, stype
, ptype
in [
62 ('cs', 'm_FBCSn', 'out'),
63 ('bwe', 'm_BWEn', 'out'),
64 ('tsiz', 'm_TSIZ', 'out'),
65 ('ad_out', 'm_AD', 'out'),
66 ('ad_in', 'm_din', 'in'),
67 ('ad_out_en', 'm_OE32n', 'out'),
69 ret
.append(self
._mk
_vpincon
(name
, count
, typ
, ptype
, pname
,
70 "sdram_side.{0}".format(stype
)))