1 from bsv
.peripheral_gen
.base
import PBase
7 return "import sdr_top::*;"
9 def num_axi_regs32(self
):
10 return [0x400000, # defines an entire memory range (hack...)
11 12] # defines the number of configuration regs
13 def extfastifinstance(self
, name
, count
):
14 return "// TODO" + self
._extifinstance
(name
, count
, "_out", "", True,
17 def fastifdecl(self
, name
, count
):
18 return "// (*always_ready*) interface " + \
19 "Ifc_sdram_out sdr{0}_out;".format(count
)
21 def get_clk_spc(self
, typ
):
24 def get_clock_reset(self
, name
, count
):
25 return "slow_clock, slow_reset"
27 def mkfast_peripheral(self
):
28 return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0, rst0);"
30 def _mk_connection(self
, name
=None, count
=0):
31 return ["sdr{0}.axi4_slave_sdram",
32 "sdr{0}.axi4_slave_cntrl_reg"]
34 def pinname_out(self
, pname
):
35 return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
36 'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
37 'sdrcke': 'ifc_sdram_out.osdr_cke',
38 'sdrclk': 'ifc_sdram_out.osdr_clock',
39 'sdrrasn': 'ifc_sdram_out.osdr_ras_n',
40 'sdrcasn': 'ifc_sdram_out.osdr_cas_n',
43 def _mk_clk_con(self
, name
, count
, ctype
):
44 ret
= [PBase
._mk
_clk
_con
(self
, name
, count
, ctype
)]
45 for pname
, sz
, ptype
in [
51 ('d_out_en', 64, 'out'),
53 bitspec
= "Bit#(%d)" % sz
54 txt
= self
._mk
_clk
_vcon
(name
, count
, ctype
, ptype
, pname
, bitspec
)
58 def _mk_pincon(self
, name
, count
, typ
):
59 ret
= [PBase
._mk
_pincon
(self
, name
, count
, typ
)]
60 assert typ
== 'fast' # TODO slow?
61 for pname
, stype
, ptype
in [
62 ('dqm', 'osdr_dqm', 'out'),
63 ('ba', 'osdr_ba', 'out'),
64 ('ad', 'osdr_addr', 'out'),
65 ('d_out', 'osdr_dout', 'out'),
66 ('d_in', 'ipad_sdr_din', 'in'),
67 ('d_out_en', 'osdr_den_n', 'out'),
69 ret
.append(self
._mk
_vpincon
(name
, count
, typ
, ptype
, pname
,
70 "ifc_sdram_out.{0}".format(stype
)))