src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def axibase(self, name, ifacenum):
  10         name = name.upper()
  11         return "%(name)s%(ifacenum)dBase" % locals()
  12
  13     def axiend(self, name, ifacenum):
  14         name = name.upper()
  15         return "%(name)s%(ifacenum)dEnd" % locals()
  16
  17     def axi_reg_def(self, start, name, ifacenum):
  18         name = name.upper()
  19         offs = self.num_axi_regs32() * 4 * 16
  20         end = start + offs - 1
  21         bname = self.axibase(name, ifacenum)
  22         bend = self.axiend(name, ifacenum)
  23         comment = "%d 32-bit regs" % self.num_axi_regs32()
  24         return ("    `define%(bname)s 'h%(start)08X\n"
  25                 "    `define%(bend)s  'h%(end)08X // %(comment)s" % locals(),
  26                 offs)
  27
  28     def axi_slave_name(self, name, ifacenum):
  29         name = name.upper()
  30         return "{0}{1}_slave_num".format(name, ifacenum)
  31
  32     def axi_slave_idx(self, idx, name, ifacenum):
  33         name = self.axi_slave_name(name, ifacenum)
  34         return ("typedef {0} {1};".format(idx, name), 1)
  35
  36     def axi_addr_map(self, name, ifacenum):
  37         bname = self.axibase(name, ifacenum)
  38         bend = self.axiend(name, ifacenum)
  39         name = self.axi_slave_name(name, ifacenum)
  40         return """\
  41         if(addr>=`{0} && addr<=`{1})
  42             return tuple2(True,fromInteger(valueOf({2})));
  43         else""".format(bname, bend, name)
  44
  45     def mk_pincon(self, name, count):
  46         # TODO: really should be using bsv.interface_decl.Interfaces
  47         # pin-naming rules.... logic here is hard-coded to duplicate
  48         # it (see Interface.__init__ outen)
  49         ret = []
  50         for p in self.peripheral.pinspecs:
  51             typ = p['type']
  52             pname = p['name']
  53             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  54             n = name#"{0}{1}".format(self.name, self.mksuffix(name, count))
  55             ret.append("    //%s %s" % (n, str(p)))
  56             sname = self.peripheral.pname(pname).format(count)
  57             ps = "pinmux.peripheral_side.%s" % sname
  58             if typ == 'out' or typ == 'inout':
  59                 ret.append("    rule con_%s%d_%s_out" % (name, count, pname))
  60                 fname = self.pinname_out(pname)
  61                 if fname:
  62                     if p.get('outen'):
  63                         ps_ = ps + '_out'
  64                     else:
  65                         ps_ = ps
  66                     n_ = "{0}{1}".format(n, count)
  67                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  68                 fname = None
  69                 if p.get('outen'):
  70                     fname = self.pinname_outen(pname)
  71                 if fname:
  72                     fname = "{0}{1}.{2}".format(n, count, fname)
  73                     fname = self.pinname_tweak(pname, 'outen', fname)
  74                     ret.append("      {0}_outen({1});".format(ps, fname))
  75                 ret.append("    endrule")
  76             if typ == 'in' or typ == 'inout':
  77                 fname = self.pinname_in(pname)
  78                 if fname:
  79                     if p.get('outen'):
  80                         ps_ = ps + '_in'
  81                     else:
  82                         ps_ = ps
  83                     ret.append("    rule con_%s%d_%s_in" % (name, count, pname))
  84                     ret.append("      {1}.{2}({0});".format(ps_, n, fname))
  85                     ret.append("    endrule")
  86         return '\n'.join(ret)
  87
  88     def mk_cellconn(self, *args):
  89         return ''
  90
  91     def mkslow_peripheral(self):
  92         return ''
  93
  94     def mksuffix(self, name, i):
  95         return i
  96
  97     def __mk_connection(self, con, aname):
  98         txt =  "        mkConnection (slow_fabric.v_to_slaves\n" + \
  99                "                    [fromInteger(valueOf({1}))],\n" + \
 100                "                    {0});"
 101
 102         print "PBase __mk_connection", self.name, aname
 103         if not con:
 104             return ''
 105         return txt.format(con, aname)
 106
 107     def mk_connection(self, count, name=None):
 108         if name is None:
 109             name = self.name
 110         print "PBase mk_conn", self.name, count
 111         aname = self.axi_slave_name(name, count)
 112         #dname = self.mksuffix(name, count)
 113         #dname = "{0}{1}".format(name, dname)
 114         con = self._mk_connection(name, count).format(count, aname)
 115         return self.__mk_connection(con, aname)
 116
 117     def _mk_connection(self, name=None, count=0):
 118         return ''
 119
 120     def pinname_out(self, pname):
 121         return ''
 122
 123     def pinname_in(self, pname):
 124         return ''
 125
 126     def pinname_outen(self, pname):
 127         return ''
 128
 129     def pinname_tweak(self, pname, typ, txt):
 130         return txt
 131
 132 class uart(PBase):
 133
 134     def slowimport(self):
 135         return "          import Uart16550         :: *;"
 136
 137     def slowifdecl(self):
 138         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 139                "            method Bit#(1) uart{0}_intr;"
 140
 141     def num_axi_regs32(self):
 142         return 8
 143
 144     def mkslow_peripheral(self):
 145         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 146                "                mkUart16550(clocked_by uart_clock,\n" + \
 147                "                    reset_by uart_reset, sp_clock, sp_reset);"
 148
 149     def _mk_connection(self, name=None, count=0):
 150         return "uart{0}.slave_axi_uart"
 151
 152     def pinname_out(self, pname):
 153         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 154
 155     def pinname_in(self, pname):
 156         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 157
 158
 159 class rs232(PBase):
 160
 161     def slowimport(self):
 162         return "        import Uart_bs::*;\n" + \
 163                "        import RS232_modified::*;"
 164
 165     def slowifdecl(self):
 166         return "            interface RS232 uart{0}_coe;"
 167
 168     def num_axi_regs32(self):
 169         return 2
 170
 171     def mkslow_peripheral(self):
 172         return "        //Ifc_Uart_bs uart{0} <-" + \
 173                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 174                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 175                "        Ifc_Uart_bs uart{0} <-" + \
 176                "                mkUart_bs(clocked_by sp_clock,\n" + \
 177                "                    reset_by sp_reset, sp_clock, sp_reset);"
 178
 179     def _mk_connection(self, name=None, count=0):
 180         return "uart{0}.slave_axi_uart"
 181
 182     def pinname_out(self, pname):
 183         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 184
 185     def pinname_in(self, pname):
 186         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 187
 188
 189 class twi(PBase):
 190
 191     def slowimport(self):
 192         return "        import I2C_top           :: *;"
 193
 194     def slowifdecl(self):
 195         return "            interface I2C_out twi{0}_out;\n" + \
 196                "            method Bit#(1) twi{0}_isint;"
 197
 198     def num_axi_regs32(self):
 199         return 8
 200
 201     def mkslow_peripheral(self):
 202         return "        I2C_IFC twi{0} <- mkI2CController();"
 203
 204     def _mk_connection(self, name=None, count=0):
 205         return "twi{0}.slave_i2c_axi"
 206
 207     def pinname_out(self, pname):
 208         return {'sda': 'out.sda_out',
 209                 'scl': 'out.scl_out'}.get(pname, '')
 210
 211     def pinname_in(self, pname):
 212         return {'sda': 'out.sda_in',
 213                 'scl': 'out.scl_in'}.get(pname, '')
 214
 215     def pinname_outen(self, pname):
 216         return {'sda': 'out.sda_outen',
 217                 'scl': 'out.scl_outen'}.get(pname, '')
 218
 219     def pinname_tweak(self, pname, typ, txt):
 220         if typ == 'outen':
 221             return "pack({0})".format(txt)
 222         return txt
 223
 224
 225 class qspi(PBase):
 226
 227     def slowimport(self):
 228         return "        import qspi              :: *;"
 229
 230     def slowifdecl(self):
 231         return "            interface QSPI_out qspi{0}_out;\n" + \
 232                "            method Bit#(1) qspi{0}_isint;"
 233
 234     def num_axi_regs32(self):
 235         return 13
 236
 237     def mkslow_peripheral(self):
 238         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 239
 240     def _mk_connection(self, name=None, count=0):
 241         return "qspi{0}.slave"
 242
 243
 244 class pwm(PBase):
 245
 246     def slowimport(self):
 247         return "        import pwm::*;"
 248
 249     def slowifdecl(self):
 250         return "        interface PWMIO pwm{0}_o;"
 251
 252     def num_axi_regs32(self):
 253         return 4
 254
 255     def mkslow_peripheral(self):
 256         return "        Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
 257
 258     def _mk_connection(self, name=None, count=0):
 259         return "pwm{0}_bus.axi4_slave"
 260
 261     def pinname_out(self, pname):
 262         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 263
 264
 265 class gpio(PBase):
 266
 267     def slowimport(self):
 268         return "     import pinmux::*;\n" + \
 269                "     import mux::*;\n" + \
 270                "     import gpio::*;\n"
 271
 272     def slowifdecl(self):
 273         return "        interface GPIO_config#({1}) pad_config{0};"
 274
 275     def num_axi_regs32(self):
 276         return 2
 277
 278     def axi_slave_idx(self, idx, name, ifacenum):
 279         """ generates AXI slave number definition, except
 280             GPIO also has a muxer per bank
 281         """
 282         name = name.upper()
 283         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 284         (ret2, x) = PBase.axi_slave_idx(self, idx, "mux", ifacenum)
 285         return ("%s\n%s" % (ret, ret2), 2)
 286
 287     def mkslow_peripheral(self):
 288         return "        MUX#(%(name)s) mux{0} <- mkmux();\n" + \
 289                "        GPIO#(%(name)s) gpio{0} <- mkgpio();" % \
 290                     {'name': self.name}
 291
 292     def mk_connection(self, count):
 293         print "GPIO mk_conn", self.name, count
 294         res = []
 295         dname = self.mksuffix(self.name, count)
 296         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 297             res.append(PBase.mk_connection(self, count, n))
 298         return '\n'.join(res)
 299
 300     def _mk_connection(self, name=None, count=0):
 301         n = self.mksuffix(name, count)
 302         if name.startswith('gpio'):
 303             return "gpio{0}.axi_slave".format(n)
 304         if name.startswith('mux'):
 305             return "mux{0}.axi_slave".format(n)
 306
 307     def mksuffix(self, name, i):
 308         if name.startswith('mux'):
 309             return name[3:]
 310         return name[4:]
 311
 312     def mk_cellconn(self, cellnum, name, count):
 313         ret = []
 314         bank = self.mksuffix(name, count)
 315         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 316         for p in self.peripheral.pinspecs:
 317             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 318             cellnum += 1
 319         return ("\n".join(ret), cellnum)
 320
 321     def pinname_out(self, pname):
 322         return "func.gpio_out[{0}]".format(pname[1:])
 323
 324     def pinname_outen(self, pname):
 325         return {'sda': 'out.sda_outen',
 326                 'scl': 'out.scl_outen'}.get(pname, '')
 327
 328     def mk_pincon(self, name, count):
 329         ret = [PBase.mk_pincon(self, name, count)]
 330         # special-case for gpio in, store in a temporary vector
 331         plen = len(self.peripheral.pinspecs)
 332         ret.append("    rule con_%s%d_in" % (name, count))
 333         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 334         for p in self.peripheral.pinspecs:
 335             typ = p['type']
 336             pname = p['name']
 337             idx = pname[1:]
 338             n = name
 339             sname = self.peripheral.pname(pname).format(count)
 340             ps = "pinmux.peripheral_side.%s_in" % sname
 341             ret.append("        temp[{0}]={1};".format(idx, ps))
 342         ret.append("        {0}.func.gpio_in(temp);".format(name))
 343         ret.append("    endrule")
 344         return '\n'.join(ret)
 345
 346
 347 axi_slave_declarations = """\
 348 typedef  0  SlowMaster;
 349 {0}
 350 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 351               CLINT_slave_num;
 352 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 353               Plic_slave_num;
 354 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 355               AxiExp1_slave_num;
 356 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 357 """
 358
 359 pinmux_cellrule = """\
 360     rule connect_select_lines_pinmux;
 361 {0}
 362     endrule
 363 """
 364
 365
 366 class CallFn(object):
 367     def __init__(self, peripheral, name):
 368         self.peripheral = peripheral
 369         self.name = name
 370
 371     def __call__(self, *args):
 372         #print "__call__", self.name, self.peripheral.slow, args
 373         if not self.peripheral.slow:
 374             return ''
 375         return getattr(self.peripheral.slow, self.name)(*args[1:])
 376
 377
 378 class PeripheralIface(object):
 379     def __init__(self, ifacename):
 380         self.slow = None
 381         slow = slowfactory.getcls(ifacename)
 382         print "Iface", ifacename, slow
 383         if slow:
 384             self.slow = slow(ifacename)
 385             self.slow.peripheral = self
 386         for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
 387                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 388             fn = CallFn(self, fname)
 389             setattr(self, fname, types.MethodType(fn, self))
 390
 391         #print "PeripheralIface"
 392         #print dir(self)
 393
 394     def mksuffix(self, name, i):
 395         if self.slow is None:
 396             return i
 397         return self.slow.mksuffix(name, i)
 398
 399     def axi_reg_def(self, start, count):
 400         if not self.slow:
 401             return ('', 0)
 402         return self.slow.axi_reg_def(start, self.ifacename, count)
 403
 404     def axi_slave_idx(self, start, count):
 405         if not self.slow:
 406             return ('', 0)
 407         return self.slow.axi_slave_idx(start, self.ifacename, count)
 408
 409     def axi_addr_map(self, count):
 410         if not self.slow:
 411             return ''
 412         return self.slow.axi_addr_map(self.ifacename, count)
 413
 414
 415 class PeripheralInterfaces(object):
 416     def __init__(self):
 417         pass
 418
 419     def slowimport(self, *args):
 420         ret = []
 421         for (name, count) in self.ifacecount:
 422             #print "slowimport", name, self.data[name].slowimport
 423             ret.append(self.data[name].slowimport())
 424         return '\n'.join(list(filter(None, ret)))
 425
 426     def slowifdecl(self, *args):
 427         ret = []
 428         for (name, count) in self.ifacecount:
 429             for i in range(count):
 430                 ret.append(self.data[name].slowifdecl().format(i, name))
 431         return '\n'.join(list(filter(None, ret)))
 432
 433     def axi_reg_def(self, *args):
 434         ret = []
 435         start = 0x00011100  # start of AXI peripherals address
 436         for (name, count) in self.ifacecount:
 437             for i in range(count):
 438                 x = self.data[name].axi_reg_def(start, i)
 439                 #print ("ifc", name, x)
 440                 (rdef, offs) = x
 441                 ret.append(rdef)
 442                 start += offs
 443         return '\n'.join(list(filter(None, ret)))
 444
 445     def axi_slave_idx(self, *args):
 446         ret = []
 447         start = 0
 448         for (name, count) in self.ifacecount:
 449             for i in range(count):
 450                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 451                 #print ("ifc", name, rdef, offs)
 452                 ret.append(rdef)
 453                 start += offs
 454         ret.append("typedef %d LastGen_slave_num" % (start - 1))
 455         decls = '\n'.join(list(filter(None, ret)))
 456         return axi_slave_declarations.format(decls)
 457
 458     def axi_addr_map(self, *args):
 459         ret = []
 460         for (name, count) in self.ifacecount:
 461             for i in range(count):
 462                 ret.append(self.data[name].axi_addr_map(i))
 463         return '\n'.join(list(filter(None, ret)))
 464
 465     def mkslow_peripheral(self, *args):
 466         ret = []
 467         for (name, count) in self.ifacecount:
 468             for i in range(count):
 469                 print "mkslow", name, count
 470                 x = self.data[name].mkslow_peripheral()
 471                 print name, count, x
 472                 suffix = self.data[name].mksuffix(name, i)
 473                 ret.append(x.format(suffix))
 474         return '\n'.join(list(filter(None, ret)))
 475
 476     def mk_connection(self, *args):
 477         ret = []
 478         for (name, count) in self.ifacecount:
 479             for i in range(count):
 480                 print "mk_conn", name, i
 481                 txt = self.data[name].mk_connection(i)
 482                 if name == 'gpioa':
 483                     print "txt", txt
 484                     print self.data[name].mk_connection
 485                 ret.append(txt)
 486         return '\n'.join(list(filter(None, ret)))
 487
 488     def mk_cellconn(self):
 489         ret = []
 490         cellcount = 0
 491         for (name, count) in self.ifacecount:
 492             for i in range(count):
 493                 res = self.data[name].mk_cellconn(cellcount, name, i)
 494                 if not res:
 495                     continue
 496                 (txt, cellcount) = res
 497                 ret.append(txt)
 498         ret = '\n'.join(list(filter(None, ret)))
 499         return pinmux_cellrule.format(ret)
 500
 501     def mk_pincon(self):
 502         ret = []
 503         for (name, count) in self.ifacecount:
 504             for i in range(count):
 505                 txt = self.data[name].mk_pincon(name, i)
 506                 ret.append(txt)
 507         return '\n'.join(list(filter(None, ret)))
 508
 509 class PFactory(object):
 510     def getcls(self, name):
 511         for k, v in {'uart': uart,
 512                 'rs232': rs232,
 513                 'twi': twi,
 514                 'qspi': qspi,
 515                 'pwm': pwm,
 516                 'gpio': gpio
 517                 }.items():
 518             if name.startswith(k):
 519                 return v
 520         return None
 521
 522
 523 slowfactory = PFactory()
 524
 525 if __name__ == '__main__':
 526     p = uart('uart')
 527     print p.slowimport()
 528     print p.slowifdecl()
 529     i = PeripheralIface('uart')
 530     print i, i.slow
 531     i = PeripheralIface('gpioa')
 532     print i, i.slow