2 from copy
import deepcopy
6 def __init__(self
, name
):
9 def axibase(self
, name
, ifacenum
):
11 return "%(name)s%(ifacenum)dBase" % locals()
13 def axiend(self
, name
, ifacenum
):
15 return "%(name)s%(ifacenum)dEnd" % locals()
17 def axi_reg_def(self
, start
, name
, ifacenum
):
19 offs
= self
.num_axi_regs32() * 4 * 16
20 end
= start
+ offs
- 1
21 bname
= self
.axibase(name
, ifacenum
)
22 bend
= self
.axiend(name
, ifacenum
)
23 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
24 return (" `define %(bname)s 'h%(start)08X\n"
25 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
28 def axi_slave_name(self
, name
, ifacenum
):
30 return "{0}{1}_slave_num".format(name
, ifacenum
)
32 def axi_slave_idx(self
, idx
, name
, ifacenum
):
33 name
= self
.axi_slave_name(name
, ifacenum
)
34 return ("typedef {0} {1};".format(idx
, name
), 1)
36 def axi_addr_map(self
, name
, ifacenum
):
37 bname
= self
.axibase(name
, ifacenum
)
38 bend
= self
.axiend(name
, ifacenum
)
39 name
= self
.axi_slave_name(name
, ifacenum
)
41 if(addr>=`{0} && addr<=`{1})
42 return tuple2(True,fromInteger(valueOf({2})));
43 else""".format(bname
, bend
, name
)
45 def mk_pincon(self
, name
, count
):
46 # TODO: really should be using bsv.interface_decl.Interfaces
47 # pin-naming rules.... logic here is hard-coded to duplicate
48 # it (see Interface.__init__ outen)
50 for p
in self
.peripheral
.pinspecs
:
53 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
54 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
55 ret
.append(" //%s %s" % (n
, str(p
)))
56 sname
= self
.peripheral
.pname(pname
).format(count
)
57 ps
= "pinmux.peripheral_side.%s" % sname
58 if typ
== 'out' or typ
== 'inout':
59 ret
.append(" rule con_%s%d_%s_out;" % (name
, count
, pname
))
60 fname
= self
.pinname_out(pname
)
66 n_
= "{0}{1}".format(n
, count
)
67 ret
.append(" {0}({1}.{2});".format(ps_
, n_
, fname
))
70 fname
= self
.pinname_outen(pname
)
72 if isinstance(fname
, str):
73 fname
= "{0}{1}.{2}".format(n
, count
, fname
)
74 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
75 ret
.append(" {0}_outen({1});".format(ps
, fname
))
76 ret
.append(" endrule")
77 if typ
== 'in' or typ
== 'inout':
78 fname
= self
.pinname_in(pname
)
85 " rule con_%s%d_%s_in;" %
87 ret
.append(" {1}.{2}({0});".format(ps_
, n
, fname
))
88 ret
.append(" endrule")
91 def mk_cellconn(self
, *args
):
94 def mkslow_peripheral(self
, size
=0):
97 def mksuffix(self
, name
, i
):
100 def __mk_connection(self
, con
, aname
):
101 txt
= " mkConnection (slow_fabric.v_to_slaves\n" + \
102 " [fromInteger(valueOf({1}))],\n" + \
105 print "PBase __mk_connection", self
.name
, aname
108 return txt
.format(con
, aname
)
110 def mk_connection(self
, count
, name
=None):
113 print "PBase mk_conn", self
.name
, count
114 aname
= self
.axi_slave_name(name
, count
)
115 #dname = self.mksuffix(name, count)
116 #dname = "{0}{1}".format(name, dname)
117 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
118 return self
.__mk
_connection
(con
, aname
)
120 def _mk_connection(self
, name
=None, count
=0):
123 def pinname_out(self
, pname
):
126 def pinname_in(self
, pname
):
129 def pinname_outen(self
, pname
):
132 def pinname_tweak(self
, pname
, typ
, txt
):
138 def slowimport(self
):
139 return " import Uart16550 :: *;"
141 def slowifdecl(self
):
142 return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
143 " method Bit#(1) uart{0}_intr;"
145 def num_axi_regs32(self
):
148 def mkslow_peripheral(self
, size
=0):
149 return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
150 " mkUart16550(clocked_by uart_clock,\n" + \
151 " reset_by uart_reset, sp_clock, sp_reset);"
153 def _mk_connection(self
, name
=None, count
=0):
154 return "uart{0}.slave_axi_uart"
156 def pinname_out(self
, pname
):
157 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
159 def pinname_in(self
, pname
):
160 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
165 def slowimport(self
):
166 return " import Uart_bs::*;\n" + \
167 " import RS232_modified::*;"
169 def slowifdecl(self
):
170 return " interface RS232 uart{0}_coe;"
172 def num_axi_regs32(self
):
175 def mkslow_peripheral(self
, size
=0):
176 return " //Ifc_Uart_bs uart{0} <-" + \
177 " // mkUart_bs(clocked_by uart_clock,\n" + \
178 " // reset_by uart_reset,sp_clock, sp_reset);" +\
179 " Ifc_Uart_bs uart{0} <-" + \
180 " mkUart_bs(clocked_by sp_clock,\n" + \
181 " reset_by sp_reset, sp_clock, sp_reset);"
183 def _mk_connection(self
, name
=None, count
=0):
184 return "uart{0}.slave_axi_uart"
186 def pinname_out(self
, pname
):
187 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
189 def pinname_in(self
, pname
):
190 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
195 def slowimport(self
):
196 return " import I2C_top :: *;"
198 def slowifdecl(self
):
199 return " interface I2C_out twi{0}_out;\n" + \
200 " method Bit#(1) twi{0}_isint;"
202 def num_axi_regs32(self
):
205 def mkslow_peripheral(self
, size
=0):
206 return " I2C_IFC twi{0} <- mkI2CController();"
208 def _mk_connection(self
, name
=None, count
=0):
209 return "twi{0}.slave_i2c_axi"
211 def pinname_out(self
, pname
):
212 return {'sda': 'out.sda_out',
213 'scl': 'out.scl_out'}.get(pname
, '')
215 def pinname_in(self
, pname
):
216 return {'sda': 'out.sda_in',
217 'scl': 'out.scl_in'}.get(pname
, '')
219 def pinname_outen(self
, pname
):
220 return {'sda': 'out.sda_outen',
221 'scl': 'out.scl_outen'}.get(pname
, '')
223 def pinname_tweak(self
, pname
, typ
, txt
):
225 return "pack({0})".format(txt
)
231 def slowimport(self
):
232 return " import qspi :: *;"
234 def slowifdecl(self
):
235 return " interface QSPI_out qspi{0}_out;\n" + \
236 " method Bit#(1) qspi{0}_isint;"
238 def num_axi_regs32(self
):
241 def mkslow_peripheral(self
, size
=0):
242 return " Ifc_qspi qspi{0} <- mkqspi();"
244 def _mk_connection(self
, name
=None, count
=0):
245 return "qspi{0}.slave"
247 def pinname_out(self
, pname
):
248 return {'ck': 'out.clk_o',
250 'io0': 'out.io_o[0]',
251 'io1': 'out.io_o[1]',
252 'io2': 'out.io_o[2]',
253 'io3': 'out.io_o[3]',
256 def pinname_outen(self
, pname
):
259 'io0': 'out.io_enable[0]',
260 'io1': 'out.io_enable[1]',
261 'io2': 'out.io_enable[2]',
262 'io3': 'out.io_enable[3]',
265 def mk_pincon(self
, name
, count
):
266 ret
= [PBase
.mk_pincon(self
, name
, count
)]
267 # special-case for gpio in, store in a temporary vector
268 plen
= len(self
.peripheral
.pinspecs
)
269 ret
.append(" // XXX NSS and CLK are hard-coded master")
270 ret
.append(" // TODO: must add qspi slave-mode")
271 ret
.append(" // all ins done in one rule from 4-bitfield")
272 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
273 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
274 for i
, p
in enumerate(self
.peripheral
.pinspecs
):
277 if not pname
.startswith('io'):
281 sname
= self
.peripheral
.pname(pname
).format(count
)
282 ps
= "pinmux.peripheral_side.%s_in" % sname
283 comma
= '' if i
== 5 else ','
284 ret
.append(" {0}{1}".format(ps
, comma
))
286 ret
.append(" endrule")
287 return '\n'.join(ret
)
292 def slowimport(self
):
293 return " import pwm::*;"
295 def slowifdecl(self
):
296 return " interface PWMIO pwm{0}_o;"
298 def num_axi_regs32(self
):
301 def mkslow_peripheral(self
, size
=0):
302 return " Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
304 def _mk_connection(self
, name
=None, count
=0):
305 return "pwm{0}_bus.axi4_slave"
307 def pinname_out(self
, pname
):
308 return {'out': 'pwm_io.pwm_o'}.get(pname
, '')
313 def slowimport(self
):
314 return " import pinmux::*;\n" + \
315 " import mux::*;\n" + \
318 def slowifdecl(self
):
319 return " interface GPIO_config#({1}) pad_config{0};"
321 def num_axi_regs32(self
):
324 def axi_slave_idx(self
, idx
, name
, ifacenum
):
325 """ generates AXI slave number definition, except
326 GPIO also has a muxer per bank
329 mname
= 'mux' + name
[4:]
330 mname
= mname
.upper()
331 print "AXIslavenum", name
, mname
332 (ret
, x
) = PBase
.axi_slave_idx(self
, idx
, name
, ifacenum
)
333 (ret2
, x
) = PBase
.axi_slave_idx(self
, idx
, mname
, ifacenum
)
334 return ("%s\n%s" % (ret
, ret2
), 2)
336 def mkslow_peripheral(self
, size
=0):
337 print "gpioslow", self
.peripheral
, dir(self
.peripheral
)
338 size
= len(self
.peripheral
.pinspecs
)
339 return " MUX#(%d) mux{0} <- mkmux();\n" % size
+ \
340 " GPIO#(%d) gpio{0} <- mkgpio();" % size
342 def mk_connection(self
, count
):
343 print "GPIO mk_conn", self
.name
, count
345 dname
= self
.mksuffix(self
.name
, count
)
346 for i
, n
in enumerate(['gpio' + dname
, 'mux' + dname
]):
347 res
.append(PBase
.mk_connection(self
, count
, n
))
348 return '\n'.join(res
)
350 def _mk_connection(self
, name
=None, count
=0):
351 n
= self
.mksuffix(name
, count
)
352 if name
.startswith('gpio'):
353 return "gpio{0}.axi_slave".format(n
)
354 if name
.startswith('mux'):
355 return "mux{0}.axi_slave".format(n
)
357 def mksuffix(self
, name
, i
):
358 if name
.startswith('mux'):
362 def mk_cellconn(self
, cellnum
, name
, count
):
364 bank
= self
.mksuffix(name
, count
)
365 txt
= " pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
366 for p
in self
.peripheral
.pinspecs
:
367 ret
.append(txt
.format(cellnum
, bank
, p
['name'][1:]))
369 return ("\n".join(ret
), cellnum
)
371 def pinname_out(self
, pname
):
372 return "func.gpio_out[{0}]".format(pname
[1:])
374 def pinname_outen(self
, pname
):
375 return {'sda': 'out.sda_outen',
376 'scl': 'out.scl_outen'}.get(pname
, '')
378 def mk_pincon(self
, name
, count
):
379 ret
= [PBase
.mk_pincon(self
, name
, count
)]
380 # special-case for gpio in, store in a temporary vector
381 plen
= len(self
.peripheral
.pinspecs
)
382 ret
.append(" rule con_%s%d_in;" % (name
, count
))
383 ret
.append(" Vector#({0},Bit#(1)) temp;".format(plen
))
384 for p
in self
.peripheral
.pinspecs
:
389 sname
= self
.peripheral
.pname(pname
).format(count
)
390 ps
= "pinmux.peripheral_side.%s_in" % sname
391 ret
.append(" temp[{0}]={1};".format(idx
, ps
))
392 ret
.append(" {0}.func.gpio_in(temp);".format(name
))
393 ret
.append(" endrule")
394 return '\n'.join(ret
)
397 axi_slave_declarations
= """\
398 typedef 0 SlowMaster;
400 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
402 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
404 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
406 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
409 pinmux_cellrule
= """\
410 rule connect_select_lines_pinmux;
416 class CallFn(object):
417 def __init__(self
, peripheral
, name
):
418 self
.peripheral
= peripheral
421 def __call__(self
, *args
):
422 #print "__call__", self.name, self.peripheral.slow, args
423 if not self
.peripheral
.slow
:
425 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
428 class PeripheralIface(object):
429 def __init__(self
, ifacename
):
431 slow
= slowfactory
.getcls(ifacename
)
432 print "Iface", ifacename
, slow
434 self
.slow
= slow(ifacename
)
435 self
.slow
.peripheral
= self
436 for fname
in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
437 'mk_connection', 'mk_cellconn', 'mk_pincon']:
438 fn
= CallFn(self
, fname
)
439 setattr(self
, fname
, types
.MethodType(fn
, self
))
441 #print "PeripheralIface"
444 def mksuffix(self
, name
, i
):
445 if self
.slow
is None:
447 return self
.slow
.mksuffix(name
, i
)
449 def axi_reg_def(self
, start
, count
):
452 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
454 def axi_slave_idx(self
, start
, count
):
457 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
459 def axi_addr_map(self
, count
):
462 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
465 class PeripheralInterfaces(object):
469 def slowimport(self
, *args
):
471 for (name
, count
) in self
.ifacecount
:
472 #print "slowimport", name, self.data[name].slowimport
473 ret
.append(self
.data
[name
].slowimport())
474 return '\n'.join(list(filter(None, ret
)))
476 def slowifdecl(self
, *args
):
478 for (name
, count
) in self
.ifacecount
:
479 for i
in range(count
):
480 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
481 return '\n'.join(list(filter(None, ret
)))
483 def axi_reg_def(self
, *args
):
485 start
= 0x00011100 # start of AXI peripherals address
486 for (name
, count
) in self
.ifacecount
:
487 for i
in range(count
):
488 x
= self
.data
[name
].axi_reg_def(start
, i
)
489 #print ("ifc", name, x)
493 return '\n'.join(list(filter(None, ret
)))
495 def axi_slave_idx(self
, *args
):
498 for (name
, count
) in self
.ifacecount
:
499 for i
in range(count
):
500 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
501 #print ("ifc", name, rdef, offs)
504 ret
.append("typedef %d LastGen_slave_num;" % (start
- 1))
505 decls
= '\n'.join(list(filter(None, ret
)))
506 return axi_slave_declarations
.format(decls
)
508 def axi_addr_map(self
, *args
):
510 for (name
, count
) in self
.ifacecount
:
511 for i
in range(count
):
512 ret
.append(self
.data
[name
].axi_addr_map(i
))
513 return '\n'.join(list(filter(None, ret
)))
515 def mkslow_peripheral(self
, *args
):
517 for (name
, count
) in self
.ifacecount
:
518 for i
in range(count
):
519 print "mkslow", name
, count
520 x
= self
.data
[name
].mkslow_peripheral()
522 suffix
= self
.data
[name
].mksuffix(name
, i
)
523 ret
.append(x
.format(suffix
))
524 return '\n'.join(list(filter(None, ret
)))
526 def mk_connection(self
, *args
):
528 for (name
, count
) in self
.ifacecount
:
529 for i
in range(count
):
530 print "mk_conn", name
, i
531 txt
= self
.data
[name
].mk_connection(i
)
534 print self
.data
[name
].mk_connection
536 return '\n'.join(list(filter(None, ret
)))
538 def mk_cellconn(self
):
541 for (name
, count
) in self
.ifacecount
:
542 for i
in range(count
):
543 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
546 (txt
, cellcount
) = res
548 ret
= '\n'.join(list(filter(None, ret
)))
549 return pinmux_cellrule
.format(ret
)
553 for (name
, count
) in self
.ifacecount
:
554 for i
in range(count
):
555 txt
= self
.data
[name
].mk_pincon(name
, i
)
557 return '\n'.join(list(filter(None, ret
)))
560 class PFactory(object):
561 def getcls(self
, name
):
562 for k
, v
in {'uart': uart
,
569 if name
.startswith(k
):
574 slowfactory
= PFactory()
576 if __name__
== '__main__':
580 i
= PeripheralIface('uart')
582 i
= PeripheralIface('gpioa')