4 def axibase(self
, name
, ifacenum
):
6 return "%(name)s%(ifacenum)dBase" % locals()
8 def axiend(self
, name
, ifacenum
):
10 return "%(name)s%(ifacenum)dEnd" % locals()
12 def axi_reg_def(self
, start
, name
, ifacenum
):
14 offs
= self
.num_axi_regs32() * 4 * 16
15 end
= start
+ offs
- 1
16 bname
= self
.axibase(name
, ifacenum
)
17 bend
= self
.axiend(name
, ifacenum
)
18 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
19 return (" `define%(bname)s 'h%(start)08X\n"
20 " `define%(bend)s 'h%(end)08X // %(comment)s" % locals(),
23 def axi_slave_name(self
, name
, ifacenum
):
25 return "{0}{1}_slave_num".format(name
, ifacenum
)
27 def axi_slave_idx(self
, idx
, name
, ifacenum
):
28 name
= self
.axi_slave_name(name
, ifacenum
)
29 return ("typedef {0} {1};".format(idx
, name
), 1)
31 def axi_addr_map(self
, name
, ifacenum
):
32 bname
= self
.axibase(name
, ifacenum
)
33 bend
= self
.axiend(name
, ifacenum
)
34 name
= self
.axi_slave_name(name
, ifacenum
)
36 if(addr>=`{0} && addr<=`{1})
37 return tuple2(True,fromInteger(valueOf({2})));
38 else""".format(bname
, bend
, name
)
43 return " import Uart16550 :: *;"
46 return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
47 " method Bit#(1) uart{0}_intr;"
49 def num_axi_regs32(self
):
55 return " import Uart_bs::*;\n" + \
56 " import RS232_modified::*;"
59 return " interface RS232 uart{0}_coe;"
61 def num_axi_regs32(self
):
67 return " import I2C_top :: *;"
70 return " interface I2C_out i2c{0}_out;\n" + \
71 " method Bit#(1) i2c{0}_isint;"
73 def num_axi_regs32(self
):
79 return " import qspi :: *;"
82 return " interface QSPI_out qspi{0}_out;\n" + \
83 " method Bit#(1) qspi{0}_isint;"
85 def num_axi_regs32(self
):
91 return " import pwm::*;"
94 return " interface PWMIO pwm_o;"
96 def num_axi_regs32(self
):
102 return " import pinmux::*;\n" + \
103 " import mux::*;\n" + \
107 return " interface GPIO_config#({1}) pad_config{0};"
109 def num_axi_regs32(self
):
112 def axi_slave_idx(self
, idx
, name
, ifacenum
):
113 """ generates AXI slave number definition, except
114 GPIO also has a muxer per bank
117 (ret
, x
) = PBase
.axi_slave_idx(self
, idx
, name
, ifacenum
)
118 (ret2
, x
) = PBase
.axi_slave_idx(self
, idx
, "mux", ifacenum
)
119 return ("%s\n%s" % (ret
, ret2
), 2)
122 axi_slave_declarations
= """\
123 typedef 0 SlowMaster;
125 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
127 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
129 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
131 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
135 class PeripheralIface(object):
136 def __init__(self
, ifacename
):
138 slow
= slowfactory
.getcls(ifacename
)
142 def slowimport(self
):
145 return self
.slow
.importfn().format()
147 def slowifdecl(self
, count
):
150 return self
.slow
.ifacedecl().format(count
, self
.ifacename
)
152 def axi_reg_def(self
, start
, count
):
155 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
157 def axi_slave_idx(self
, start
, count
):
160 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
162 def axi_addr_map(self
, count
):
165 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
167 class PeripheralInterfaces(object):
171 def slowimport(self
, *args
):
173 for (name
, count
) in self
.ifacecount
:
174 ret
.append(self
.data
[name
].slowimport())
175 return '\n'.join(list(filter(None, ret
)))
177 def slowifdecl(self
, *args
):
179 for (name
, count
) in self
.ifacecount
:
180 for i
in range(count
):
181 ret
.append(self
.data
[name
].slowifdecl(i
))
182 return '\n'.join(list(filter(None, ret
)))
184 def axi_reg_def(self
, *args
):
186 start
= 0x00011100 # start of AXI peripherals address
187 for (name
, count
) in self
.ifacecount
:
188 for i
in range(count
):
189 x
= self
.data
[name
].axi_reg_def(start
, i
)
190 print ("ifc", name
, x
)
194 return '\n'.join(list(filter(None, ret
)))
196 def axi_slave_idx(self
, *args
):
199 for (name
, count
) in self
.ifacecount
:
200 for i
in range(count
):
201 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
202 print ("ifc", name
, rdef
, offs
)
205 ret
.append("typedef %d LastGen_slave_num" % (start
- 1))
206 decls
= '\n'.join(list(filter(None, ret
)))
207 return axi_slave_declarations
.format(decls
)
209 def axi_addr_map(self
, *args
):
211 for (name
, count
) in self
.ifacecount
:
212 for i
in range(count
):
213 ret
.append(self
.data
[name
].axi_addr_map(i
))
214 return '\n'.join(list(filter(None, ret
)))
217 class PFactory(object):
218 def getcls(self
, name
):
219 return {'uart': uart
,
227 slowfactory
= PFactory()