2 from copy
import deepcopy
6 def __init__(self
, name
):
9 def axibase(self
, name
, ifacenum
):
11 return "%(name)s%(ifacenum)dBase" % locals()
13 def axiend(self
, name
, ifacenum
):
15 return "%(name)s%(ifacenum)dEnd" % locals()
17 def axi_reg_def(self
, start
, name
, ifacenum
):
19 offs
= self
.num_axi_regs32() * 4 * 16
20 end
= start
+ offs
- 1
21 bname
= self
.axibase(name
, ifacenum
)
22 bend
= self
.axiend(name
, ifacenum
)
23 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
24 return (" `define%(bname)s 'h%(start)08X\n"
25 " `define%(bend)s 'h%(end)08X // %(comment)s" % locals(),
28 def axi_slave_name(self
, name
, ifacenum
):
30 return "{0}{1}_slave_num".format(name
, ifacenum
)
32 def axi_slave_idx(self
, idx
, name
, ifacenum
):
33 name
= self
.axi_slave_name(name
, ifacenum
)
34 return ("typedef {0} {1};".format(idx
, name
), 1)
36 def axi_addr_map(self
, name
, ifacenum
):
37 bname
= self
.axibase(name
, ifacenum
)
38 bend
= self
.axiend(name
, ifacenum
)
39 name
= self
.axi_slave_name(name
, ifacenum
)
41 if(addr>=`{0} && addr<=`{1})
42 return tuple2(True,fromInteger(valueOf({2})));
43 else""".format(bname
, bend
, name
)
45 def mk_pincon(self
, name
, count
):
46 # TODO: really should be using bsv.interface_decl.Interfaces
47 # pin-naming rules.... logic here is hard-coded to duplicate
48 # it (see Interface.__init__ outen)
50 for p
in self
.peripheral
.pinspecs
:
53 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
54 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
55 ret
.append(" //%s %s" % (n
, str(p
)))
56 sname
= self
.peripheral
.pname(pname
).format(count
)
57 ps
= "pinmux.peripheral_side.%s" % sname
58 if typ
== 'out' or typ
== 'inout':
59 ret
.append(" rule con_%s%d_%s_out" % (name
, count
, pname
))
60 fname
= self
.pinname_out(pname
)
66 n_
= "{0}{1}".format(n
, count
)
67 ret
.append(" {0}({1}.{2});".format(ps_
, n_
, fname
))
70 fname
= self
.pinname_outen(pname
)
72 fname
= "{0}{1}.{2}".format(n
, count
, fname
)
73 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
74 ret
.append(" {0}_outen({1});".format(ps
, fname
))
75 ret
.append(" endrule")
76 if typ
== 'in' or typ
== 'inout':
77 fname
= self
.pinname_in(pname
)
84 " rule con_%s%d_%s_in" %
86 ret
.append(" {1}.{2}({0});".format(ps_
, n
, fname
))
87 ret
.append(" endrule")
90 def mk_cellconn(self
, *args
):
93 def mkslow_peripheral(self
):
96 def mksuffix(self
, name
, i
):
99 def __mk_connection(self
, con
, aname
):
100 txt
= " mkConnection (slow_fabric.v_to_slaves\n" + \
101 " [fromInteger(valueOf({1}))],\n" + \
104 print "PBase __mk_connection", self
.name
, aname
107 return txt
.format(con
, aname
)
109 def mk_connection(self
, count
, name
=None):
112 print "PBase mk_conn", self
.name
, count
113 aname
= self
.axi_slave_name(name
, count
)
114 #dname = self.mksuffix(name, count)
115 #dname = "{0}{1}".format(name, dname)
116 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
117 return self
.__mk
_connection
(con
, aname
)
119 def _mk_connection(self
, name
=None, count
=0):
122 def pinname_out(self
, pname
):
125 def pinname_in(self
, pname
):
128 def pinname_outen(self
, pname
):
131 def pinname_tweak(self
, pname
, typ
, txt
):
137 def slowimport(self
):
138 return " import Uart16550 :: *;"
140 def slowifdecl(self
):
141 return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
142 " method Bit#(1) uart{0}_intr;"
144 def num_axi_regs32(self
):
147 def mkslow_peripheral(self
):
148 return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
149 " mkUart16550(clocked_by uart_clock,\n" + \
150 " reset_by uart_reset, sp_clock, sp_reset);"
152 def _mk_connection(self
, name
=None, count
=0):
153 return "uart{0}.slave_axi_uart"
155 def pinname_out(self
, pname
):
156 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
158 def pinname_in(self
, pname
):
159 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
164 def slowimport(self
):
165 return " import Uart_bs::*;\n" + \
166 " import RS232_modified::*;"
168 def slowifdecl(self
):
169 return " interface RS232 uart{0}_coe;"
171 def num_axi_regs32(self
):
174 def mkslow_peripheral(self
):
175 return " //Ifc_Uart_bs uart{0} <-" + \
176 " // mkUart_bs(clocked_by uart_clock,\n" + \
177 " // reset_by uart_reset,sp_clock, sp_reset);" +\
178 " Ifc_Uart_bs uart{0} <-" + \
179 " mkUart_bs(clocked_by sp_clock,\n" + \
180 " reset_by sp_reset, sp_clock, sp_reset);"
182 def _mk_connection(self
, name
=None, count
=0):
183 return "uart{0}.slave_axi_uart"
185 def pinname_out(self
, pname
):
186 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
188 def pinname_in(self
, pname
):
189 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
194 def slowimport(self
):
195 return " import I2C_top :: *;"
197 def slowifdecl(self
):
198 return " interface I2C_out twi{0}_out;\n" + \
199 " method Bit#(1) twi{0}_isint;"
201 def num_axi_regs32(self
):
204 def mkslow_peripheral(self
):
205 return " I2C_IFC twi{0} <- mkI2CController();"
207 def _mk_connection(self
, name
=None, count
=0):
208 return "twi{0}.slave_i2c_axi"
210 def pinname_out(self
, pname
):
211 return {'sda': 'out.sda_out',
212 'scl': 'out.scl_out'}.get(pname
, '')
214 def pinname_in(self
, pname
):
215 return {'sda': 'out.sda_in',
216 'scl': 'out.scl_in'}.get(pname
, '')
218 def pinname_outen(self
, pname
):
219 return {'sda': 'out.sda_outen',
220 'scl': 'out.scl_outen'}.get(pname
, '')
222 def pinname_tweak(self
, pname
, typ
, txt
):
224 return "pack({0})".format(txt
)
230 def slowimport(self
):
231 return " import qspi :: *;"
233 def slowifdecl(self
):
234 return " interface QSPI_out qspi{0}_out;\n" + \
235 " method Bit#(1) qspi{0}_isint;"
237 def num_axi_regs32(self
):
240 def mkslow_peripheral(self
):
241 return " Ifc_qspi qspi{0} <- mkqspi();"
243 def _mk_connection(self
, name
=None, count
=0):
244 return "qspi{0}.slave"
249 def slowimport(self
):
250 return " import pwm::*;"
252 def slowifdecl(self
):
253 return " interface PWMIO pwm{0}_o;"
255 def num_axi_regs32(self
):
258 def mkslow_peripheral(self
):
259 return " Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
261 def _mk_connection(self
, name
=None, count
=0):
262 return "pwm{0}_bus.axi4_slave"
264 def pinname_out(self
, pname
):
265 return {'out': 'pwm_io.pwm_o'}.get(pname
, '')
270 def slowimport(self
):
271 return " import pinmux::*;\n" + \
272 " import mux::*;\n" + \
275 def slowifdecl(self
):
276 return " interface GPIO_config#({1}) pad_config{0};"
278 def num_axi_regs32(self
):
281 def axi_slave_idx(self
, idx
, name
, ifacenum
):
282 """ generates AXI slave number definition, except
283 GPIO also has a muxer per bank
286 (ret
, x
) = PBase
.axi_slave_idx(self
, idx
, name
, ifacenum
)
287 (ret2
, x
) = PBase
.axi_slave_idx(self
, idx
, "mux", ifacenum
)
288 return ("%s\n%s" % (ret
, ret2
), 2)
290 def mkslow_peripheral(self
):
291 return " MUX#(%(name)s) mux{0} <- mkmux();\n" + \
292 " GPIO#(%(name)s) gpio{0} <- mkgpio();" % \
295 def mk_connection(self
, count
):
296 print "GPIO mk_conn", self
.name
, count
298 dname
= self
.mksuffix(self
.name
, count
)
299 for i
, n
in enumerate(['gpio' + dname
, 'mux' + dname
]):
300 res
.append(PBase
.mk_connection(self
, count
, n
))
301 return '\n'.join(res
)
303 def _mk_connection(self
, name
=None, count
=0):
304 n
= self
.mksuffix(name
, count
)
305 if name
.startswith('gpio'):
306 return "gpio{0}.axi_slave".format(n
)
307 if name
.startswith('mux'):
308 return "mux{0}.axi_slave".format(n
)
310 def mksuffix(self
, name
, i
):
311 if name
.startswith('mux'):
315 def mk_cellconn(self
, cellnum
, name
, count
):
317 bank
= self
.mksuffix(name
, count
)
318 txt
= " pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
319 for p
in self
.peripheral
.pinspecs
:
320 ret
.append(txt
.format(cellnum
, bank
, p
['name'][1:]))
322 return ("\n".join(ret
), cellnum
)
324 def pinname_out(self
, pname
):
325 return "func.gpio_out[{0}]".format(pname
[1:])
327 def pinname_outen(self
, pname
):
328 return {'sda': 'out.sda_outen',
329 'scl': 'out.scl_outen'}.get(pname
, '')
331 def mk_pincon(self
, name
, count
):
332 ret
= [PBase
.mk_pincon(self
, name
, count
)]
333 # special-case for gpio in, store in a temporary vector
334 plen
= len(self
.peripheral
.pinspecs
)
335 ret
.append(" rule con_%s%d_in" % (name
, count
))
336 ret
.append(" Vector#({0},Bit#(1)) temp;".format(plen
))
337 for p
in self
.peripheral
.pinspecs
:
342 sname
= self
.peripheral
.pname(pname
).format(count
)
343 ps
= "pinmux.peripheral_side.%s_in" % sname
344 ret
.append(" temp[{0}]={1};".format(idx
, ps
))
345 ret
.append(" {0}.func.gpio_in(temp);".format(name
))
346 ret
.append(" endrule")
347 return '\n'.join(ret
)
350 axi_slave_declarations
= """\
351 typedef 0 SlowMaster;
353 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
355 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
357 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
359 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
362 pinmux_cellrule
= """\
363 rule connect_select_lines_pinmux;
369 class CallFn(object):
370 def __init__(self
, peripheral
, name
):
371 self
.peripheral
= peripheral
374 def __call__(self
, *args
):
375 #print "__call__", self.name, self.peripheral.slow, args
376 if not self
.peripheral
.slow
:
378 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
381 class PeripheralIface(object):
382 def __init__(self
, ifacename
):
384 slow
= slowfactory
.getcls(ifacename
)
385 print "Iface", ifacename
, slow
387 self
.slow
= slow(ifacename
)
388 self
.slow
.peripheral
= self
389 for fname
in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
390 'mk_connection', 'mk_cellconn', 'mk_pincon']:
391 fn
= CallFn(self
, fname
)
392 setattr(self
, fname
, types
.MethodType(fn
, self
))
394 #print "PeripheralIface"
397 def mksuffix(self
, name
, i
):
398 if self
.slow
is None:
400 return self
.slow
.mksuffix(name
, i
)
402 def axi_reg_def(self
, start
, count
):
405 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
407 def axi_slave_idx(self
, start
, count
):
410 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
412 def axi_addr_map(self
, count
):
415 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
418 class PeripheralInterfaces(object):
422 def slowimport(self
, *args
):
424 for (name
, count
) in self
.ifacecount
:
425 #print "slowimport", name, self.data[name].slowimport
426 ret
.append(self
.data
[name
].slowimport())
427 return '\n'.join(list(filter(None, ret
)))
429 def slowifdecl(self
, *args
):
431 for (name
, count
) in self
.ifacecount
:
432 for i
in range(count
):
433 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
434 return '\n'.join(list(filter(None, ret
)))
436 def axi_reg_def(self
, *args
):
438 start
= 0x00011100 # start of AXI peripherals address
439 for (name
, count
) in self
.ifacecount
:
440 for i
in range(count
):
441 x
= self
.data
[name
].axi_reg_def(start
, i
)
442 #print ("ifc", name, x)
446 return '\n'.join(list(filter(None, ret
)))
448 def axi_slave_idx(self
, *args
):
451 for (name
, count
) in self
.ifacecount
:
452 for i
in range(count
):
453 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
454 #print ("ifc", name, rdef, offs)
457 ret
.append("typedef %d LastGen_slave_num" % (start
- 1))
458 decls
= '\n'.join(list(filter(None, ret
)))
459 return axi_slave_declarations
.format(decls
)
461 def axi_addr_map(self
, *args
):
463 for (name
, count
) in self
.ifacecount
:
464 for i
in range(count
):
465 ret
.append(self
.data
[name
].axi_addr_map(i
))
466 return '\n'.join(list(filter(None, ret
)))
468 def mkslow_peripheral(self
, *args
):
470 for (name
, count
) in self
.ifacecount
:
471 for i
in range(count
):
472 print "mkslow", name
, count
473 x
= self
.data
[name
].mkslow_peripheral()
475 suffix
= self
.data
[name
].mksuffix(name
, i
)
476 ret
.append(x
.format(suffix
))
477 return '\n'.join(list(filter(None, ret
)))
479 def mk_connection(self
, *args
):
481 for (name
, count
) in self
.ifacecount
:
482 for i
in range(count
):
483 print "mk_conn", name
, i
484 txt
= self
.data
[name
].mk_connection(i
)
487 print self
.data
[name
].mk_connection
489 return '\n'.join(list(filter(None, ret
)))
491 def mk_cellconn(self
):
494 for (name
, count
) in self
.ifacecount
:
495 for i
in range(count
):
496 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
499 (txt
, cellcount
) = res
501 ret
= '\n'.join(list(filter(None, ret
)))
502 return pinmux_cellrule
.format(ret
)
506 for (name
, count
) in self
.ifacecount
:
507 for i
in range(count
):
508 txt
= self
.data
[name
].mk_pincon(name
, i
)
510 return '\n'.join(list(filter(None, ret
)))
513 class PFactory(object):
514 def getcls(self
, name
):
515 for k
, v
in {'uart': uart
,
522 if name
.startswith(k
):
527 slowfactory
= PFactory()
529 if __name__
== '__main__':
533 i
= PeripheralIface('uart')
535 i
= PeripheralIface('gpioa')