2 from copy
import deepcopy
6 def __init__(self
, name
):
9 def axibase(self
, name
, ifacenum
):
11 return "%(name)s%(ifacenum)dBase" % locals()
13 def axiend(self
, name
, ifacenum
):
15 return "%(name)s%(ifacenum)dEnd" % locals()
17 def axi_reg_def(self
, start
, name
, ifacenum
):
19 offs
= self
.num_axi_regs32() * 4 * 16
20 end
= start
+ offs
- 1
21 bname
= self
.axibase(name
, ifacenum
)
22 bend
= self
.axiend(name
, ifacenum
)
23 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
24 return (" `define%(bname)s 'h%(start)08X\n"
25 " `define%(bend)s 'h%(end)08X // %(comment)s" % locals(),
28 def axi_slave_name(self
, name
, ifacenum
):
30 return "{0}{1}_slave_num".format(name
, ifacenum
)
32 def axi_slave_idx(self
, idx
, name
, ifacenum
):
33 name
= self
.axi_slave_name(name
, ifacenum
)
34 return ("typedef {0} {1};".format(idx
, name
), 1)
36 def axi_addr_map(self
, name
, ifacenum
):
37 bname
= self
.axibase(name
, ifacenum
)
38 bend
= self
.axiend(name
, ifacenum
)
39 name
= self
.axi_slave_name(name
, ifacenum
)
41 if(addr>=`{0} && addr<=`{1})
42 return tuple2(True,fromInteger(valueOf({2})));
43 else""".format(bname
, bend
, name
)
45 def mk_pincon(self
, name
, count
):
47 for p
in self
.peripheral
.pinspecs
:
50 n
= "{0}{1}".format(name
, self
.mksuffix(name
, count
))
51 ret
.append(" //%s %s" % (n
, str(p
)))
52 sname
= self
.peripheral
.pname(pname
).format(count
)
53 ps
= "pinmux.peripheral_side.%s" % sname
54 if typ
== 'out' or typ
== 'inout':
55 ret
.append(" rule con_%s%d_%s_out" % (name
, count
, pname
))
56 fname
= self
.pinname_out(pname
)
58 ret
.append(" {0}_out({1}.{2});".format(ps
, n
, fname
))
61 fname
= self
.pinname_outen(pname
)
63 ret
.append(" {0}_outen({1}.{2});".format(ps
, n
, fname
))
64 ret
.append(" endrule")
65 if typ
== 'in' or typ
== 'inout':
66 fname
= self
.pinname_in(pname
)
68 ret
.append(" rule con_%s%d_%s_in" % (name
, count
, pname
))
69 ret
.append(" {1}.{2}({0}_in);".format(ps
, n
, fname
))
70 ret
.append(" endrule")
73 def mk_cellconn(self
, *args
):
76 def mkslow_peripheral(self
):
79 def mksuffix(self
, name
, i
):
82 def __mk_connection(self
, con
, aname
):
83 txt
= " mkConnection (slow_fabric.v_to_slaves\n" + \
84 " [fromInteger(valueOf({1}))],\n" + \
87 print "PBase __mk_connection", self
.name
, aname
90 return txt
.format(con
, aname
)
92 def mk_connection(self
, count
, name
=None):
95 print "PBase mk_conn", self
.name
, count
96 aname
= self
.axi_slave_name(name
, count
)
97 #dname = self.mksuffix(name, count)
98 #dname = "{0}{1}".format(name, dname)
99 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
100 return self
.__mk
_connection
(con
, aname
)
102 def _mk_connection(self
, name
=None, count
=0):
105 def pinname_out(self
, pname
):
108 def pinname_in(self
, pname
):
111 def pinname_outen(self
, pname
):
117 def slowimport(self
):
118 return " import Uart16550 :: *;"
120 def slowifdecl(self
):
121 return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
122 " method Bit#(1) uart{0}_intr;"
124 def num_axi_regs32(self
):
127 def mkslow_peripheral(self
):
128 return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
129 " mkUart16550(clocked_by uart_clock,\n" + \
130 " reset_by uart_reset, sp_clock, sp_reset);"
132 def _mk_connection(self
, name
=None, count
=0):
133 return "uart{0}.slave_axi_uart"
135 def pinname_out(self
, pname
):
136 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
138 def pinname_in(self
, pname
):
139 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
144 def slowimport(self
):
145 return " import Uart_bs::*;\n" + \
146 " import RS232_modified::*;"
148 def slowifdecl(self
):
149 return " interface RS232 uart{0}_coe;"
151 def num_axi_regs32(self
):
154 def mkslow_peripheral(self
):
155 return " //Ifc_Uart_bs uart{0} <-" + \
156 " // mkUart_bs(clocked_by uart_clock,\n" + \
157 " // reset_by uart_reset,sp_clock, sp_reset);" +\
158 " Ifc_Uart_bs uart{0} <-" + \
159 " mkUart_bs(clocked_by sp_clock,\n" + \
160 " reset_by sp_reset, sp_clock, sp_reset);"
162 def _mk_connection(self
, name
=None, count
=0):
163 return "uart{0}.slave_axi_uart"
165 def pinname_out(self
, pname
):
166 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
168 def pinname_in(self
, pname
):
169 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
174 def slowimport(self
):
175 return " import I2C_top :: *;"
177 def slowifdecl(self
):
178 return " interface I2C_out twi{0}_out;\n" + \
179 " method Bit#(1) twi{0}_isint;"
181 def num_axi_regs32(self
):
184 def mkslow_peripheral(self
):
185 return " I2C_IFC twi{0} <- mkI2CController();"
187 def _mk_connection(self
, name
=None, count
=0):
188 return "twi{0}.slave_i2c_axi"
190 def pinname_out(self
, pname
):
191 return {'sda': 'out.sda_out',
192 'scl': 'out.scl_out'}.get(pname
, '')
194 def pinname_in(self
, pname
):
195 return {'sda': 'out.sda_in',
196 'scl': 'out.scl_in'}.get(pname
, '')
198 def pinname_outen(self
, pname
):
199 return {'sda': 'out.sda_outen',
200 'scl': 'out.scl_outen'}.get(pname
, '')
206 def slowimport(self
):
207 return " import qspi :: *;"
209 def slowifdecl(self
):
210 return " interface QSPI_out qspi{0}_out;\n" + \
211 " method Bit#(1) qspi{0}_isint;"
213 def num_axi_regs32(self
):
216 def mkslow_peripheral(self
):
217 return " Ifc_qspi qspi{0} <- mkqspi();"
219 def _mk_connection(self
, name
=None, count
=0):
220 return "qspi{0}.slave"
225 def slowimport(self
):
226 return " import pwm::*;"
228 def slowifdecl(self
):
229 return " interface PWMIO pwm{0}_o;"
231 def num_axi_regs32(self
):
234 def mkslow_peripheral(self
):
235 return " Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
237 def _mk_connection(self
, name
=None, count
=0):
238 return "pwm{0}_bus.axi4_slave"
243 def slowimport(self
):
244 return " import pinmux::*;\n" + \
245 " import mux::*;\n" + \
248 def slowifdecl(self
):
249 return " interface GPIO_config#({1}) pad_config{0};"
251 def num_axi_regs32(self
):
254 def axi_slave_idx(self
, idx
, name
, ifacenum
):
255 """ generates AXI slave number definition, except
256 GPIO also has a muxer per bank
259 (ret
, x
) = PBase
.axi_slave_idx(self
, idx
, name
, ifacenum
)
260 (ret2
, x
) = PBase
.axi_slave_idx(self
, idx
, "mux", ifacenum
)
261 return ("%s\n%s" % (ret
, ret2
), 2)
263 def mkslow_peripheral(self
):
264 return " MUX#(%(name)s) mux{0} <- mkmux();\n" + \
265 " GPIO#(%(name)s) gpio{0} <- mkgpio();" % \
268 def mk_connection(self
, count
):
269 print "GPIO mk_conn", self
.name
, count
271 dname
= self
.mksuffix(self
.name
, count
)
272 for i
, n
in enumerate(['gpio' + dname
, 'mux' + dname
]):
273 res
.append(PBase
.mk_connection(self
, count
, n
))
274 return '\n'.join(res
)
276 def _mk_connection(self
, name
=None, count
=0):
277 n
= self
.mksuffix(name
, count
)
278 if name
.startswith('gpio'):
279 return "gpio{0}.axi_slave".format(n
)
280 if name
.startswith('mux'):
281 return "mux{0}.axi_slave".format(n
)
283 def mksuffix(self
, name
, i
):
284 if name
.startswith('mux'):
288 def mk_cellconn(self
, cellnum
, name
, count
):
290 bank
= self
.mksuffix(name
, count
)
291 txt
= " pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
292 for p
in self
.peripheral
.pinspecs
:
293 ret
.append(txt
.format(cellnum
, bank
, p
['name'][1:]))
295 return ("\n".join(ret
), cellnum
)
298 axi_slave_declarations
= """\
299 typedef 0 SlowMaster;
301 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
303 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
305 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
307 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
310 pinmux_cellrule
= """\
311 rule connect_select_lines_pinmux;
317 class CallFn(object):
318 def __init__(self
, peripheral
, name
):
319 self
.peripheral
= peripheral
322 def __call__(self
, *args
):
323 #print "__call__", self.name, self.peripheral.slow, args
324 if not self
.peripheral
.slow
:
326 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
329 class PeripheralIface(object):
330 def __init__(self
, ifacename
):
332 slow
= slowfactory
.getcls(ifacename
)
333 print "Iface", ifacename
, slow
335 self
.slow
= slow(ifacename
)
336 self
.slow
.peripheral
= self
337 for fname
in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
338 'mk_connection', 'mk_cellconn', 'mk_pincon']:
339 fn
= CallFn(self
, fname
)
340 setattr(self
, fname
, types
.MethodType(fn
, self
))
342 #print "PeripheralIface"
345 def mksuffix(self
, name
, i
):
346 if self
.slow
is None:
348 return self
.slow
.mksuffix(name
, i
)
350 def axi_reg_def(self
, start
, count
):
353 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
355 def axi_slave_idx(self
, start
, count
):
358 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
360 def axi_addr_map(self
, count
):
363 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
366 class PeripheralInterfaces(object):
370 def slowimport(self
, *args
):
372 for (name
, count
) in self
.ifacecount
:
373 #print "slowimport", name, self.data[name].slowimport
374 ret
.append(self
.data
[name
].slowimport())
375 return '\n'.join(list(filter(None, ret
)))
377 def slowifdecl(self
, *args
):
379 for (name
, count
) in self
.ifacecount
:
380 for i
in range(count
):
381 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
382 return '\n'.join(list(filter(None, ret
)))
384 def axi_reg_def(self
, *args
):
386 start
= 0x00011100 # start of AXI peripherals address
387 for (name
, count
) in self
.ifacecount
:
388 for i
in range(count
):
389 x
= self
.data
[name
].axi_reg_def(start
, i
)
390 #print ("ifc", name, x)
394 return '\n'.join(list(filter(None, ret
)))
396 def axi_slave_idx(self
, *args
):
399 for (name
, count
) in self
.ifacecount
:
400 for i
in range(count
):
401 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
402 #print ("ifc", name, rdef, offs)
405 ret
.append("typedef %d LastGen_slave_num" % (start
- 1))
406 decls
= '\n'.join(list(filter(None, ret
)))
407 return axi_slave_declarations
.format(decls
)
409 def axi_addr_map(self
, *args
):
411 for (name
, count
) in self
.ifacecount
:
412 for i
in range(count
):
413 ret
.append(self
.data
[name
].axi_addr_map(i
))
414 return '\n'.join(list(filter(None, ret
)))
416 def mkslow_peripheral(self
, *args
):
418 for (name
, count
) in self
.ifacecount
:
419 for i
in range(count
):
420 print "mkslow", name
, count
421 x
= self
.data
[name
].mkslow_peripheral()
423 suffix
= self
.data
[name
].mksuffix(name
, i
)
424 ret
.append(x
.format(suffix
))
425 return '\n'.join(list(filter(None, ret
)))
427 def mk_connection(self
, *args
):
429 for (name
, count
) in self
.ifacecount
:
430 for i
in range(count
):
431 print "mk_conn", name
, i
432 txt
= self
.data
[name
].mk_connection(i
)
435 print self
.data
[name
].mk_connection
437 return '\n'.join(list(filter(None, ret
)))
439 def mk_cellconn(self
):
442 for (name
, count
) in self
.ifacecount
:
443 for i
in range(count
):
444 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
447 (txt
, cellcount
) = res
449 ret
= '\n'.join(list(filter(None, ret
)))
450 return pinmux_cellrule
.format(ret
)
454 for (name
, count
) in self
.ifacecount
:
455 for i
in range(count
):
456 txt
= self
.data
[name
].mk_pincon(name
, i
)
458 return '\n'.join(list(filter(None, ret
)))
460 class PFactory(object):
461 def getcls(self
, name
):
462 for k
, v
in {'uart': uart
,
469 if name
.startswith(k
):
474 slowfactory
= PFactory()
476 if __name__
== '__main__':
480 i
= PeripheralIface('uart')
482 i
= PeripheralIface('gpioa')