4 def axibase(self
, name
, ifacenum
):
6 return "%(name)s%(ifacenum)dBase" % locals()
8 def axiend(self
, name
, ifacenum
):
10 return "%(name)s%(ifacenum)dEnd" % locals()
12 def axi_reg_def(self
, start
, name
, ifacenum
):
14 offs
= self
.num_axi_regs32() * 4 * 16
15 end
= start
+ offs
- 1
16 bname
= self
.axibase(name
, ifacenum
)
17 bend
= self
.axiend(name
, ifacenum
)
18 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
19 return (" `define%(bname)s 'h%(start)08X\n"
20 " `define%(bend)s 'h%(end)08X // %(comment)s" % locals(),
23 def axi_slave_name(self
, name
, ifacenum
):
25 return "{0}{1}_slave_num".format(name
, ifacenum
)
27 def axi_slave_idx(self
, idx
, name
, ifacenum
):
28 name
= self
.axi_slave_name(name
, ifacenum
)
29 return ("typedef {0} {1};".format(idx
, name
), 1)
31 def axi_addr_map(self
, name
, ifacenum
):
32 bname
= self
.axibase(name
, ifacenum
)
33 bend
= self
.axiend(name
, ifacenum
)
34 name
= self
.axi_slave_name(name
, ifacenum
)
36 if(addr>=`{0} && addr<=`{1})
37 return tuple2(True,fromInteger(valueOf({2})));
38 else""".format(bname
, bend
, name
)
40 def mkslow_peripheral(self
, name
, ifacenum
):
46 return " import Uart16550 :: *;"
49 return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
50 " method Bit#(1) uart{0}_intr;"
52 def num_axi_regs32(self
):
55 def mkslow_peripheral(self
):
56 return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
57 " mkUart16550(clocked_by uart_clock,\n" + \
58 " reset_by uart_reset, sp_clock, sp_reset);"
63 return " import Uart_bs::*;\n" + \
64 " import RS232_modified::*;"
67 return " interface RS232 uart{0}_coe;"
69 def num_axi_regs32(self
):
72 def mkslow_peripheral(self
):
73 return " //Ifc_Uart_bs uart{0} <-" + \
74 " // mkUart_bs(clocked_by uart_clock,\n" + \
75 " // reset_by uart_reset,sp_clock, sp_reset);" +\
76 " Ifc_Uart_bs uart{0} <-" + \
77 " mkUart_bs(clocked_by sp_clock,\n" + \
78 " reset_by sp_reset, sp_clock, sp_reset);"
83 return " import I2C_top :: *;"
86 return " interface I2C_out i2c{0}_out;\n" + \
87 " method Bit#(1) i2c{0}_isint;"
89 def num_axi_regs32(self
):
92 def mkslow_peripheral(self
):
93 return " I2C_IFC i2c{0} <- mkI2CController();"
98 return " import qspi :: *;"
101 return " interface QSPI_out qspi{0}_out;\n" + \
102 " method Bit#(1) qspi{0}_isint;"
104 def num_axi_regs32(self
):
107 def mkslow_peripheral(self
):
108 return " Ifc_qspi qspi{0} <- mkqspi();"
113 return " import pwm::*;"
116 return " interface PWMIO pwm_o;"
118 def num_axi_regs32(self
):
121 def mkslow_peripheral(self
):
122 return " Ifc_PWM_bus pwm_bus <- mkPWM_bus(sp_clock);"
128 return " import pinmux::*;\n" + \
129 " import mux::*;\n" + \
133 return " interface GPIO_config#({1}) pad_config{0};"
135 def num_axi_regs32(self
):
138 def axi_slave_idx(self
, idx
, name
, ifacenum
):
139 """ generates AXI slave number definition, except
140 GPIO also has a muxer per bank
143 (ret
, x
) = PBase
.axi_slave_idx(self
, idx
, name
, ifacenum
)
144 (ret2
, x
) = PBase
.axi_slave_idx(self
, idx
, "mux", ifacenum
)
145 return ("%s\n%s" % (ret
, ret2
), 2)
147 def mkslow_peripheral(self
):
148 return " MUX#({1}) mux{0} <- mkmux();\n" + \
149 " GPIO#({1}) gpio{0} <- mkgpio();"
152 axi_slave_declarations
= """\
153 typedef 0 SlowMaster;
155 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
157 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
159 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
161 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
165 class PeripheralIface(object):
166 def __init__(self
, ifacename
):
168 slow
= slowfactory
.getcls(ifacename
)
172 def slowimport(self
):
175 return self
.slow
.importfn().format()
177 def slowifdecl(self
, count
):
180 return self
.slow
.ifacedecl().format(count
, self
.ifacename
)
182 def axi_reg_def(self
, start
, count
):
185 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
187 def axi_slave_idx(self
, start
, count
):
190 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
192 def axi_addr_map(self
, count
):
195 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
197 def mkslow_periph(self
, count
):
200 return self
.slow
.mkslow_peripheral().format(count
, self
.ifacename
)
202 class PeripheralInterfaces(object):
206 def slowimport(self
, *args
):
208 for (name
, count
) in self
.ifacecount
:
209 ret
.append(self
.data
[name
].slowimport())
210 return '\n'.join(list(filter(None, ret
)))
212 def slowifdecl(self
, *args
):
214 for (name
, count
) in self
.ifacecount
:
215 for i
in range(count
):
216 ret
.append(self
.data
[name
].slowifdecl(i
))
217 return '\n'.join(list(filter(None, ret
)))
219 def axi_reg_def(self
, *args
):
221 start
= 0x00011100 # start of AXI peripherals address
222 for (name
, count
) in self
.ifacecount
:
223 for i
in range(count
):
224 x
= self
.data
[name
].axi_reg_def(start
, i
)
225 print ("ifc", name
, x
)
229 return '\n'.join(list(filter(None, ret
)))
231 def axi_slave_idx(self
, *args
):
234 for (name
, count
) in self
.ifacecount
:
235 for i
in range(count
):
236 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
237 print ("ifc", name
, rdef
, offs
)
240 ret
.append("typedef %d LastGen_slave_num" % (start
- 1))
241 decls
= '\n'.join(list(filter(None, ret
)))
242 return axi_slave_declarations
.format(decls
)
244 def axi_addr_map(self
, *args
):
246 for (name
, count
) in self
.ifacecount
:
247 for i
in range(count
):
248 ret
.append(self
.data
[name
].axi_addr_map(i
))
249 return '\n'.join(list(filter(None, ret
)))
251 def mkslow_periph(self
, *args
):
253 for (name
, count
) in self
.ifacecount
:
254 for i
in range(count
):
255 ret
.append(self
.data
[name
].mkslow_periph(i
))
256 return '\n'.join(list(filter(None, ret
)))
259 class PFactory(object):
260 def getcls(self
, name
):
261 return {'uart': uart
,
270 slowfactory
= PFactory()