1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
52 def pinmuxgen(pth
=None, verify
=True):
53 """ populating the file with the code
56 p
= Parse(pth
, verify
)
57 iocells
= Interfaces()
58 iocells
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
59 ifaces
= Interfaces(pth
)
60 #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
65 bp
= os
.path
.join(pth
, bp
)
66 if not os
.path
.exists(bp
):
68 bl
= os
.path
.join(bp
, 'bsv_lib')
69 if not os
.path
.exists(bl
):
72 cwd
= os
.path
.split(__file__
)[0]
74 # copy over template and library files
75 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
76 os
.path
.join(bp
, 'Makefile'))
77 cwd
= os
.path
.join(cwd
, 'bsv_lib')
79 shutil
.copyfile(os
.path
.join(cwd
, fname
),
80 os
.path
.join(bl
, fname
))
82 bus
= os
.path
.join(bp
, 'busenable.bsv')
83 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
84 bvp
= os
.path
.join(bp
, 'bus.bsv')
85 idef
= os
.path
.join(bp
, 'instance_defines.bsv')
86 slow
= os
.path
.join(bp
, 'slow_peripherals.bsv')
87 slowt
= os
.path
.join(cwd
, 'slow_peripherals_template.bsv')
88 slowmf
= os
.path
.join(bp
, 'slow_memory_map.bsv')
89 slowmt
= os
.path
.join(cwd
, 'slow_tuple2_template.bsv')
90 fastmf
= os
.path
.join(bp
, 'fast_memory_map.bsv')
91 fastmt
= os
.path
.join(cwd
, 'fast_tuple2_template.bsv')
92 soc
= os
.path
.join(bp
, 'socgen.bsv')
93 soct
= os
.path
.join(cwd
, 'soc_template.bsv')
95 write_pmp(pmp
, p
, ifaces
, iocells
)
96 write_bvp(bvp
, p
, ifaces
)
97 write_bus(bus
, p
, ifaces
)
98 write_instances(idef
, p
, ifaces
)
99 write_slow(slow
, slowt
, slowmf
, slowmt
, p
, ifaces
, iocells
)
100 write_soc(soc
, soct
, fastmf
, fastmt
, p
, ifaces
, iocells
)
103 def write_slow(slow
, slowt
, slowmf
, slowmt
, p
, ifaces
, iocells
):
104 """ write out the slow_peripherals.bsv file.
105 joins all the peripherals together into one AXI Lite interface
107 imports
= ifaces
.slowimport()
108 ifdecl
= ifaces
.slowifdeclmux() + '\n' + ifaces
.extifdecl()
109 regdef
= ifaces
.axi_reg_def()
110 slavedecl
= ifaces
.axi_slave_idx()
111 fnaddrmap
= ifaces
.axi_addr_map()
112 mkslow
= ifaces
.mkslow_peripheral()
113 mkcon
= ifaces
.mk_connection()
114 mkcellcon
= ifaces
.mk_cellconn()
115 pincon
= ifaces
.mk_pincon()
116 inst
= ifaces
.extifinstance()
117 inst2
= ifaces
.extifinstance2()
118 mkplic
= ifaces
.mk_plic()
119 numsloirqs
= ifaces
.mk_sloirqsdef()
120 ifacedef
= ifaces
.mk_ext_ifacedef()
121 ifacedef
= ifaces
.mk_ext_ifacedef()
122 clockcon
= ifaces
.mk_slowclk_con()
124 with
open(slow
, "w") as bsv_file
:
125 with
open(slowt
) as f
:
127 bsv_file
.write(slowt
.format(imports
, ifdecl
, regdef
, slavedecl
,
128 fnaddrmap
, mkslow
, mkcon
, mkcellcon
,
129 pincon
, inst
, mkplic
,
130 numsloirqs
, ifacedef
,
133 with
open(slowmf
, "w") as bsv_file
:
134 with
open(slowmt
) as f
:
136 bsv_file
.write(slowmt
.format(regdef
, slavedecl
, fnaddrmap
))
139 def write_soc(soc
, soct
, fastmf
, fastmt
, p
, ifaces
, iocells
):
140 """ write out the soc.bsv file.
141 joins all the peripherals together as AXI Masters
143 ifaces
.fastbusmode
= True # side-effects... shouldn't really do this
145 imports
= ifaces
.slowimport()
146 ifdecl
= ifaces
.fastifdecl()
147 regdef
= ifaces
.axi_fastmem_def()
148 slavedecl
= ifaces
.axi_fastslave_idx()
149 mastdecl
= ifaces
.axi_master_idx()
150 fnaddrmap
= ifaces
.axi_fastaddr_map()
151 mkfast
= ifaces
.mkfast_peripheral()
152 mkcon
= ifaces
.mk_fast_connection()
153 mkmstcon
= ifaces
.mk_master_connection()
154 mkcellcon
= ifaces
.mk_cellconn()
155 pincon
= ifaces
.mk_fast_pincon()
156 inst
= ifaces
.extfastifinstance()
157 mkplic
= ifaces
.mk_plic()
158 numsloirqs
= ifaces
.mk_sloirqsdef()
159 ifacedef
= ifaces
.mk_ext_ifacedef()
160 dma
= ifaces
.mk_dma_irq()
161 num_dmachannels
= ifaces
.num_dmachannels()
162 clockcon
= ifaces
.mk_fastclk_con()
164 with
open(soc
, "w") as bsv_file
:
165 with
open(soct
) as f
:
167 bsv_file
.write(soct
.format(imports
, ifdecl
, mkfast
,
168 slavedecl
, mastdecl
, mkcon
,
169 inst
, dma
, num_dmachannels
,
170 pincon
, regdef
, fnaddrmap
,
174 with
open(fastmf
, "w") as bsv_file
:
175 with
open(fastmt
) as f
:
177 bsv_file
.write(fastmt
.format(regdef
, slavedecl
, mastdecl
, fnaddrmap
))
180 def write_bus(bus
, p
, ifaces
):
181 # package and interface declaration followed by
182 # the generic io_cell definition
183 with
open(bus
, "w") as bsv_file
:
184 ifaces
.busfmt(bsv_file
)
187 def write_pmp(pmp
, p
, ifaces
, iocells
):
188 # package and interface declaration followed by
189 # the generic io_cell definition
190 with
open(pmp
, "w") as bsv_file
:
191 bsv_file
.write(header
)
193 bwid_template
= 'Bit#(%d)'
195 (*always_ready,always_enabled*)
196 interface MuxSelectionLines;
198 // declare the method which will capture the user pin-mux
199 // selection values.The width of the input is dependent on the number
200 // of muxes happening per IO. For now we have a generalized width
201 // where each IO will have the same number of muxes.''')
203 for cell
in p
.muxed_cells
:
205 bitwidth
= p
.get_muxbitwidth(cellnum
)
208 cell_bit_width
= bwid_template
% bitwidth
209 bsv_file
.write(mux_interface
.ifacefmt(cellnum
, cell_bit_width
))
211 bsv_file
.write("\n endinterface\n")
215 interface IOCellSide;
216 // declare the interface to the IO cells.
217 // Each IO cell will have 1 input field (output from pin mux)
218 // and an output and out-enable field (input to pinmux)''')
220 # == create method definitions for all iocell interfaces ==#
221 iocells
.ifacefmt(bsv_file
)
223 # ===== finish interface definition and start module definition=======
224 bsv_file
.write("\n endinterface\n")
226 ifaces
.ifacepfmt(bsv_file
)
227 # ===== io cell definition =======
229 (*always_ready,always_enabled*)
230 interface PeripheralSide;
231 // declare the interface to the peripherals
232 // Each peripheral's function will be either an input, output
233 // or be bi-directional. an input field will be an output from the
234 // peripheral and an output field will be an input to the peripheral.
235 // Bi-directional functions also have an output-enable (which
236 // again comes *in* from the peripheral)''')
237 # ==============================================================
239 # == create method definitions for all peripheral interfaces ==#
240 ifaces
.ifacefmt2(bsv_file
)
241 bsv_file
.write("\n endinterface\n")
243 # ===== finish interface definition and start module definition=======
246 interface Ifc_pinmux;
247 // this interface controls how each IO cell is routed. setting
248 // any given IO cell's mux control value will result in redirection
249 // of not just the input or output to different peripheral functions
250 // but also the *direction* control - if appropriate - as well.
251 interface MuxSelectionLines mux_lines;
253 // this interface contains the inputs, outputs and direction-control
254 // lines for all peripherals. GPIO is considered to also be just
255 // a peripheral because it also has in, out and direction-control.
256 interface PeripheralSide peripheral_side;
258 // this interface is to be linked to the individual IO cells.
259 // if looking at a "non-muxed" GPIO design, basically the
260 // IO cell input, output and direction-control wires are cut
261 // (giving six pairs of dangling wires, named left and right)
262 // these iocells are routed in their place on one side ("left")
263 // and the matching *GPIO* peripheral interfaces in/out/dir
264 // connect to the OTHER side ("right"). the result is that
265 // the muxer settings end up controlling the routing of where
266 // the I/O from the IOcell actually goes.
267 interface IOCellSide iocell_side;
271 module mkpinmux(Ifc_pinmux);
273 # ====================================================================
275 # ======================= create wire and registers =================#
277 // the followins wires capture the pin-mux selection
278 // values for each mux assigned to a CELL
280 for cell
in p
.muxed_cells
:
282 bitwidth
= p
.get_muxbitwidth(cellnum
)
285 cell_bit_width
= bwid_template
% bitwidth
286 bsv_file
.write(mux_interface
.wirefmt(cellnum
, cell_bit_width
))
288 iocells
.wirefmt(bsv_file
)
289 ifaces
.wirefmt(bsv_file
)
292 # ====================================================================
293 # ========================= Actual pinmuxing ========================#
295 /*====== This where the muxing starts for each io-cell======*/
296 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
297 Wire#(Bit#(1)) val1<-mkDWire(1); // need a one
299 bsv_file
.write(p
.pinmux
)
301 /*============================================================*/
303 # ====================================================================
304 # ================= interface definitions for each method =============#
306 interface mux_lines = interface MuxSelectionLines
308 for cell
in p
.muxed_cells
:
310 bitwidth
= p
.get_muxbitwidth(cellnum
)
313 cell_bit_width
= bwid_template
% bitwidth
315 mux_interface
.ifacedef(
316 cellnum
, cell_bit_width
))
317 bsv_file
.write("\n endinterface;")
321 interface iocell_side = interface IOCellSide
323 iocells
.ifacedef(bsv_file
)
324 bsv_file
.write("\n endinterface;")
328 interface peripheral_side = interface PeripheralSide
330 ifaces
.ifacedef2(bsv_file
)
331 bsv_file
.write("\n endinterface;")
333 bsv_file
.write(footer
)
334 print("BSV file successfully generated: bsv_src/pinmux.bsv")
335 # ======================================================================
338 def write_bvp(bvp
, p
, ifaces
):
339 # ######## Generate bus transactors ################
340 gpiocfg
= '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
341 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
342 muxcfg
= '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
343 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
345 gpiodec
= '\tGPIO#({0}) mygpio{1} <- mkgpio();'
346 muxdec
= '\tMUX#({0}) mymux{1} <- mkmux();'
347 gpioifc
= '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
348 '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
349 muxifc
= '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
350 '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
351 with
open(bvp
, 'w') as bsv_file
:
352 # assume here that all muxes have a 1:1 gpio
356 iks
= sorted(ifaces
.keys())
358 if not iname
.startswith('gpio'): # TODO: declare other interfaces
362 npins
= len(ifc
.pinspecs
)
363 cfg
.append(gpiocfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
366 cfg
.append(muxcfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
369 decl
.append(gpiodec
.format(npins
, bank
))
370 decl
.append(muxdec
.format(npins
, bank
))
371 idec
.append(gpioifc
.format(bank
))
372 idec
.append(muxifc
.format(bank
))
375 print dir(ifaces
['gpioa'])
376 print ifaces
['gpioa'].pinspecs
377 gpiodecl
= '\n'.join(decl
) + '\n' + '\n'.join(idec
)
378 gpiocfg
= '\n'.join(cfg
)
379 bsv_file
.write(axi4_lite
.format(gpiodecl
, gpiocfg
))
380 # ##################################################
383 def write_instances(idef
, p
, ifaces
):
384 with
open(idef
, 'w') as bsv_file
:
389 `define Reg_width {1}
393 // TODO: work out if these are needed
397 `define DCACHE_BLOCK_SIZE 4
398 `define DCACHE_WORD_SIZE 8
399 `define PERFMONITORS 64
400 `define DCACHE_WAYS 4
401 `define DCACHE_TAG_BITS 20 // tag_bits = 52
404 `define ClintBase 'h02000000
405 `define ClintEnd 'h020BFFFF
408 `define PLICBase 'h0c000000
409 `define PLICEnd 'h10000000
410 `define INTERRUPT_PINS 64
412 `define BAUD_RATE 130
414 `define BAUD_RATE 5 //130 //
417 bsv_file
.write(txt
.format(p
.ADDR_WIDTH
,