1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
52 def pinmuxgen(pth
=None, verify
=True):
53 """ populating the file with the code
56 p
= Parse(pth
, verify
)
57 iocells
= Interfaces()
58 iocells
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
59 ifaces
= Interfaces(pth
)
60 #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
65 bp
= os
.path
.join(pth
, bp
)
66 if not os
.path
.exists(bp
):
68 bl
= os
.path
.join(bp
, 'bsv_lib')
69 if not os
.path
.exists(bl
):
72 cwd
= os
.path
.split(__file__
)[0]
74 # copy over template and library files
75 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
76 os
.path
.join(bp
, 'Makefile'))
77 cwd
= os
.path
.join(cwd
, 'bsv_lib')
79 shutil
.copyfile(os
.path
.join(cwd
, fname
),
80 os
.path
.join(bl
, fname
))
82 bus
= os
.path
.join(bp
, 'busenable.bsv')
83 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
84 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
85 bvp
= os
.path
.join(bp
, 'bus.bsv')
86 idef
= os
.path
.join(bp
, 'instance_defines.bsv')
87 slow
= os
.path
.join(bp
, 'slow_peripherals.bsv')
88 slowt
= os
.path
.join(cwd
, 'slow_peripherals_template.bsv')
89 slowmf
= os
.path
.join(bp
, 'slow_memory_map.bsv')
90 slowmt
= os
.path
.join(cwd
, 'slow_tuple2_template.bsv')
91 fastmf
= os
.path
.join(bp
, 'fast_memory_map.bsv')
92 fastmt
= os
.path
.join(cwd
, 'fast_tuple2_template.bsv')
93 soc
= os
.path
.join(bp
, 'socgen.bsv')
94 soct
= os
.path
.join(cwd
, 'soc_template.bsv')
96 write_pmp(pmp
, p
, ifaces
, iocells
)
97 write_ptp(ptp
, p
, ifaces
)
98 write_bvp(bvp
, p
, ifaces
)
99 write_bus(bus
, p
, ifaces
)
100 write_instances(idef
, p
, ifaces
)
101 write_slow(slow
, slowt
, slowmf
, slowmt
, p
, ifaces
, iocells
)
102 write_soc(soc
, soct
, fastmf
, fastmt
, p
, ifaces
, iocells
)
105 def write_slow(slow
, slowt
, slowmf
, slowmt
, p
, ifaces
, iocells
):
106 """ write out the slow_peripherals.bsv file.
107 joins all the peripherals together into one AXI Lite interface
109 imports
= ifaces
.slowimport()
110 ifdecl
= ifaces
.slowifdeclmux() + '\n' + ifaces
.extifdecl()
111 regdef
= ifaces
.axi_reg_def()
112 slavedecl
= ifaces
.axi_slave_idx()
113 fnaddrmap
= ifaces
.axi_addr_map()
114 mkslow
= ifaces
.mkslow_peripheral()
115 mkcon
= ifaces
.mk_connection()
116 mkcellcon
= ifaces
.mk_cellconn()
117 pincon
= ifaces
.mk_pincon()
118 inst
= ifaces
.extifinstance()
119 inst2
= ifaces
.extifinstance2()
120 mkplic
= ifaces
.mk_plic()
121 numsloirqs
= ifaces
.mk_sloirqsdef()
122 ifacedef
= ifaces
.mk_ext_ifacedef()
123 ifacedef
= ifaces
.mk_ext_ifacedef()
124 clockcon
= ifaces
.mk_slowclk_con()
126 with
open(slow
, "w") as bsv_file
:
127 with
open(slowt
) as f
:
129 bsv_file
.write(slowt
.format(imports
, ifdecl
, regdef
, slavedecl
,
130 fnaddrmap
, mkslow
, mkcon
, mkcellcon
,
131 pincon
, inst
, mkplic
,
132 numsloirqs
, ifacedef
,
135 with
open(slowmf
, "w") as bsv_file
:
136 with
open(slowmt
) as f
:
138 bsv_file
.write(slowmt
.format(regdef
, slavedecl
, fnaddrmap
))
141 def write_soc(soc
, soct
, fastmf
, fastmt
, p
, ifaces
, iocells
):
142 """ write out the soc.bsv file.
143 joins all the peripherals together as AXI Masters
145 ifaces
.fastbusmode
= True # side-effects... shouldn't really do this
147 imports
= ifaces
.slowimport()
148 ifdecl
= ifaces
.fastifdecl()
149 regdef
= ifaces
.axi_fastmem_def()
150 slavedecl
= ifaces
.axi_fastslave_idx()
151 mastdecl
= ifaces
.axi_master_idx()
152 fnaddrmap
= ifaces
.axi_fastaddr_map()
153 mkfast
= ifaces
.mkfast_peripheral()
154 mkcon
= ifaces
.mk_fast_connection()
155 mkmstcon
= ifaces
.mk_master_connection()
156 mkcellcon
= ifaces
.mk_cellconn()
157 pincon
= ifaces
.mk_fast_pincon()
158 inst
= ifaces
.extfastifinstance()
159 mkplic
= ifaces
.mk_plic()
160 numsloirqs
= ifaces
.mk_sloirqsdef()
161 ifacedef
= ifaces
.mk_ext_ifacedef()
162 dma
= ifaces
.mk_dma_irq()
163 num_dmachannels
= ifaces
.num_dmachannels()
164 clockcon
= ifaces
.mk_fastclk_con()
166 with
open(soc
, "w") as bsv_file
:
167 with
open(soct
) as f
:
169 bsv_file
.write(soct
.format(imports
, ifdecl
, mkfast
,
170 slavedecl
, mastdecl
, mkcon
,
171 inst
, dma
, num_dmachannels
,
172 pincon
, regdef
, fnaddrmap
,
176 with
open(fastmf
, "w") as bsv_file
:
177 with
open(fastmt
) as f
:
179 bsv_file
.write(fastmt
.format(regdef
, slavedecl
, mastdecl
, fnaddrmap
))
182 def write_bus(bus
, p
, ifaces
):
183 # package and interface declaration followed by
184 # the generic io_cell definition
185 with
open(bus
, "w") as bsv_file
:
186 ifaces
.busfmt(bsv_file
)
189 def write_pmp(pmp
, p
, ifaces
, iocells
):
190 # package and interface declaration followed by
191 # the generic io_cell definition
192 with
open(pmp
, "w") as bsv_file
:
193 bsv_file
.write(header
)
195 cell_bit_width
= 'Bit#(%d)' % p
.cell_bitwidth
197 (*always_ready,always_enabled*)
198 interface MuxSelectionLines;
200 // declare the method which will capture the user pin-mux
201 // selection values.The width of the input is dependent on the number
202 // of muxes happening per IO. For now we have a generalized width
203 // where each IO will have the same number of muxes.''')
205 for cell
in p
.muxed_cells
:
206 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cell_bit_width
))
208 bsv_file
.write("\n endinterface\n")
212 interface IOCellSide;
213 // declare the interface to the IO cells.
214 // Each IO cell will have 1 input field (output from pin mux)
215 // and an output and out-enable field (input to pinmux)''')
217 # == create method definitions for all iocell interfaces ==#
218 iocells
.ifacefmt(bsv_file
)
220 # ===== finish interface definition and start module definition=======
221 bsv_file
.write("\n endinterface\n")
223 ifaces
.ifacepfmt(bsv_file
)
224 # ===== io cell definition =======
226 (*always_ready,always_enabled*)
227 interface PeripheralSide;
228 // declare the interface to the peripherals
229 // Each peripheral's function will be either an input, output
230 // or be bi-directional. an input field will be an output from the
231 // peripheral and an output field will be an input to the peripheral.
232 // Bi-directional functions also have an output-enable (which
233 // again comes *in* from the peripheral)''')
234 # ==============================================================
236 # == create method definitions for all peripheral interfaces ==#
237 ifaces
.ifacefmt2(bsv_file
)
238 bsv_file
.write("\n endinterface\n")
240 # ===== finish interface definition and start module definition=======
243 interface Ifc_pinmux;
244 // this interface controls how each IO cell is routed. setting
245 // any given IO cell's mux control value will result in redirection
246 // of not just the input or output to different peripheral functions
247 // but also the *direction* control - if appropriate - as well.
248 interface MuxSelectionLines mux_lines;
250 // this interface contains the inputs, outputs and direction-control
251 // lines for all peripherals. GPIO is considered to also be just
252 // a peripheral because it also has in, out and direction-control.
253 interface PeripheralSide peripheral_side;
255 // this interface is to be linked to the individual IO cells.
256 // if looking at a "non-muxed" GPIO design, basically the
257 // IO cell input, output and direction-control wires are cut
258 // (giving six pairs of dangling wires, named left and right)
259 // these iocells are routed in their place on one side ("left")
260 // and the matching *GPIO* peripheral interfaces in/out/dir
261 // connect to the OTHER side ("right"). the result is that
262 // the muxer settings end up controlling the routing of where
263 // the I/O from the IOcell actually goes.
264 interface IOCellSide iocell_side;
268 module mkpinmux(Ifc_pinmux);
270 # ====================================================================
272 # ======================= create wire and registers =================#
274 // the followins wires capture the pin-mux selection
275 // values for each mux assigned to a CELL
277 for cell
in p
.muxed_cells
:
278 bsv_file
.write(mux_interface
.wirefmt(
279 cell
[0], cell_bit_width
))
281 iocells
.wirefmt(bsv_file
)
282 ifaces
.wirefmt(bsv_file
)
285 # ====================================================================
286 # ========================= Actual pinmuxing ========================#
288 /*====== This where the muxing starts for each io-cell======*/
289 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
291 bsv_file
.write(p
.pinmux
)
293 /*============================================================*/
295 # ====================================================================
296 # ================= interface definitions for each method =============#
298 interface mux_lines = interface MuxSelectionLines
300 for cell
in p
.muxed_cells
:
302 mux_interface
.ifacedef(
303 cell
[0], cell_bit_width
))
304 bsv_file
.write("\n endinterface;")
308 interface iocell_side = interface IOCellSide
310 iocells
.ifacedef(bsv_file
)
311 bsv_file
.write("\n endinterface;")
315 interface peripheral_side = interface PeripheralSide
317 ifaces
.ifacedef2(bsv_file
)
318 bsv_file
.write("\n endinterface;")
320 bsv_file
.write(footer
)
321 print("BSV file successfully generated: bsv_src/pinmux.bsv")
322 # ======================================================================
325 def write_ptp(ptp
, p
, ifaces
):
326 with
open(ptp
, 'w') as bsv_file
:
327 bsv_file
.write(copyright
+ '''
330 interface Ifc_PintTop;
331 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
332 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
333 interface PeripheralSide peripheral_side;
336 module mkPinTop(Ifc_PintTop);
337 // instantiate the pin-mux module here
338 Ifc_pinmux pinmux <-mkpinmux;
340 // declare the registers which will be used to mux the IOs
341 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
343 cell_bit_width
= str(p
.cell_bitwidth
)
344 for cell
in p
.muxed_cells
:
346 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
347 cell_bit_width
, cell
[0]))
350 // rule to connect the registers to the selection lines of the
352 rule connect_selection_registers;''')
354 for cell
in p
.muxed_cells
:
356 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
360 // method definitions for the write user interface
361 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
363 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
364 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
366 for cell
in p
.muxed_cells
:
368 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
378 // method definitions for the read user interface
379 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
382 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
383 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
385 for cell
in p
.muxed_cells
:
387 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
393 return tuple2(err,data);
395 interface peripheral_side=pinmux.peripheral_side;
401 def write_bvp(bvp
, p
, ifaces
):
402 # ######## Generate bus transactors ################
403 gpiocfg
= '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
404 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
405 muxcfg
= '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
406 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
408 gpiodec
= '\tGPIO#({0}) mygpio{1} <- mkgpio();'
409 muxdec
= '\tMUX#({0}) mymux{1} <- mkmux();'
410 gpioifc
= '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
411 '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
412 muxifc
= '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
413 '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
414 with
open(bvp
, 'w') as bsv_file
:
415 # assume here that all muxes have a 1:1 gpio
419 iks
= sorted(ifaces
.keys())
421 if not iname
.startswith('gpio'): # TODO: declare other interfaces
425 npins
= len(ifc
.pinspecs
)
426 cfg
.append(gpiocfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
429 cfg
.append(muxcfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
432 decl
.append(gpiodec
.format(npins
, bank
))
433 decl
.append(muxdec
.format(npins
, bank
))
434 idec
.append(gpioifc
.format(bank
))
435 idec
.append(muxifc
.format(bank
))
438 print dir(ifaces
['gpioa'])
439 print ifaces
['gpioa'].pinspecs
440 gpiodecl
= '\n'.join(decl
) + '\n' + '\n'.join(idec
)
441 gpiocfg
= '\n'.join(cfg
)
442 bsv_file
.write(axi4_lite
.format(gpiodecl
, gpiocfg
))
443 # ##################################################
446 def write_instances(idef
, p
, ifaces
):
447 with
open(idef
, 'w') as bsv_file
:
452 `define Reg_width {1}
456 // TODO: work out if these are needed
460 `define DCACHE_BLOCK_SIZE 4
461 `define DCACHE_WORD_SIZE 8
462 `define PERFMONITORS 64
463 `define DCACHE_WAYS 4
464 `define DCACHE_TAG_BITS 20 // tag_bits = 52
467 `define ClintBase 'h02000000
468 `define ClintEnd 'h020BFFFF
471 `define PLICBase 'h0c000000
472 `define PLICEnd 'h10000000
473 `define INTERRUPT_PINS 64
475 `define BAUD_RATE 130
477 `define BAUD_RATE 5 //130 //
480 bsv_file
.write(txt
.format(p
.ADDR_WIDTH
,