1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
49 def pinmuxgen(pth
=None, verify
=True):
50 """ populating the file with the code
53 p
= Parse(pth
, verify
)
54 iocells
= Interfaces()
55 iocells
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
56 ifaces
= Interfaces(pth
)
57 #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
62 bp
= os
.path
.join(pth
, bp
)
63 if not os
.path
.exists(bp
):
65 bl
= os
.path
.join(bp
, 'bsv_lib')
66 if not os
.path
.exists(bl
):
69 cwd
= os
.path
.split(__file__
)[0]
71 # copy over template and library files
72 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
73 os
.path
.join(bp
, 'Makefile'))
74 cwd
= os
.path
.join(cwd
, 'bsv_lib')
75 for fname
in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
76 'gpio.bsv', 'mux.bsv']:
77 shutil
.copyfile(os
.path
.join(cwd
, fname
),
78 os
.path
.join(bl
, fname
))
80 bus
= os
.path
.join(bp
, 'busenable.bsv')
81 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
82 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
83 bvp
= os
.path
.join(bp
, 'bus.bsv')
84 idef
= os
.path
.join(bp
, 'instance_defines.bsv')
85 slow
= os
.path
.join(bp
, 'slow_peripherals.bsv')
86 slowt
= os
.path
.join(cwd
, 'slow_peripherals_template.bsv')
88 write_pmp(pmp
, p
, ifaces
, iocells
)
89 write_ptp(ptp
, p
, ifaces
)
90 write_bvp(bvp
, p
, ifaces
)
91 write_bus(bus
, p
, ifaces
)
92 write_instances(idef
, p
, ifaces
)
93 write_slow(slow
, slowt
, p
, ifaces
, iocells
)
96 def write_slow(slow
, template
, p
, ifaces
, iocells
):
97 """ write out the slow_peripherals.bsv file.
98 joins all the peripherals together into one AXI Lite interface
100 with
open(template
) as bsv_file
:
101 template
= bsv_file
.read()
102 imports
= ifaces
.slowimport()
103 ifdecl
= ifaces
.slowifdecl()
104 regdef
= ifaces
.axi_reg_def()
105 slavedecl
= ifaces
.axi_slave_idx()
106 fnaddrmap
= ifaces
.axi_addr_map()
107 mkslow
= ifaces
.mkslow_peripheral()
108 mkcon
= ifaces
.mk_connection()
109 mkcellcon
= ifaces
.mk_cellconn()
110 pincon
= ifaces
.mk_pincon()
111 with
open(slow
, "w") as bsv_file
:
112 bsv_file
.write(template
.format(imports
, ifdecl
, regdef
, slavedecl
,
113 fnaddrmap
, mkslow
, mkcon
, mkcellcon
,
117 def write_bus(bus
, p
, ifaces
):
118 # package and interface declaration followed by
119 # the generic io_cell definition
120 with
open(bus
, "w") as bsv_file
:
121 ifaces
.busfmt(bsv_file
)
124 def write_pmp(pmp
, p
, ifaces
, iocells
):
125 # package and interface declaration followed by
126 # the generic io_cell definition
127 with
open(pmp
, "w") as bsv_file
:
128 bsv_file
.write(header
)
130 cell_bit_width
= 'Bit#(%d)' % p
.cell_bitwidth
132 interface MuxSelectionLines;
134 // declare the method which will capture the user pin-mux
135 // selection values.The width of the input is dependent on the number
136 // of muxes happening per IO. For now we have a generalized width
137 // where each IO will have the same number of muxes.''')
139 for cell
in p
.muxed_cells
:
140 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cell_bit_width
))
142 bsv_file
.write("\n endinterface\n")
146 interface IOCellSide;
147 // declare the interface to the IO cells.
148 // Each IO cell will have 1 input field (output from pin mux)
149 // and an output and out-enable field (input to pinmux)''')
151 # == create method definitions for all iocell interfaces ==#
152 iocells
.ifacefmt(bsv_file
)
154 # ===== finish interface definition and start module definition=======
155 bsv_file
.write("\n endinterface\n")
157 # ===== io cell definition =======
160 interface PeripheralSide;
161 // declare the interface to the peripherals
162 // Each peripheral's function will be either an input, output
163 // or be bi-directional. an input field will be an output from the
164 // peripheral and an output field will be an input to the peripheral.
165 // Bi-directional functions also have an output-enable (which
166 // again comes *in* from the peripheral)''')
167 # ==============================================================
169 # == create method definitions for all peripheral interfaces ==#
170 ifaces
.ifacefmt(bsv_file
)
171 bsv_file
.write("\n endinterface\n")
173 # ===== finish interface definition and start module definition=======
176 interface Ifc_pinmux;
177 // this interface controls how each IO cell is routed. setting
178 // any given IO cell's mux control value will result in redirection
179 // of not just the input or output to different peripheral functions
180 // but also the *direction* control - if appropriate - as well.
181 interface MuxSelectionLines mux_lines;
183 // this interface contains the inputs, outputs and direction-control
184 // lines for all peripherals. GPIO is considered to also be just
185 // a peripheral because it also has in, out and direction-control.
186 interface PeripheralSide peripheral_side;
188 // this interface is to be linked to the individual IO cells.
189 // if looking at a "non-muxed" GPIO design, basically the
190 // IO cell input, output and direction-control wires are cut
191 // (giving six pairs of dangling wires, named left and right)
192 // these iocells are routed in their place on one side ("left")
193 // and the matching *GPIO* peripheral interfaces in/out/dir
194 // connect to the OTHER side ("right"). the result is that
195 // the muxer settings end up controlling the routing of where
196 // the I/O from the IOcell actually goes.
197 interface IOCellSide iocell_side;
200 module mkpinmux(Ifc_pinmux);
202 # ====================================================================
204 # ======================= create wire and registers =================#
206 // the followins wires capture the pin-mux selection
207 // values for each mux assigned to a CELL
209 for cell
in p
.muxed_cells
:
210 bsv_file
.write(mux_interface
.wirefmt(
211 cell
[0], cell_bit_width
))
213 iocells
.wirefmt(bsv_file
)
214 ifaces
.wirefmt(bsv_file
)
217 # ====================================================================
218 # ========================= Actual pinmuxing ========================#
220 /*====== This where the muxing starts for each io-cell======*/
221 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
223 bsv_file
.write(p
.pinmux
)
225 /*============================================================*/
227 # ====================================================================
228 # ================= interface definitions for each method =============#
230 interface mux_lines = interface MuxSelectionLines
232 for cell
in p
.muxed_cells
:
234 mux_interface
.ifacedef(
235 cell
[0], cell_bit_width
))
236 bsv_file
.write("\n endinterface;")
239 interface iocell_side = interface IOCellSide
241 iocells
.ifacedef(bsv_file
)
242 bsv_file
.write("\n endinterface;")
245 interface peripheral_side = interface PeripheralSide
247 ifaces
.ifacedef(bsv_file
)
248 bsv_file
.write("\n endinterface;")
250 bsv_file
.write(footer
)
251 print("BSV file successfully generated: bsv_src/pinmux.bsv")
252 # ======================================================================
255 def write_ptp(ptp
, p
, ifaces
):
256 with
open(ptp
, 'w') as bsv_file
:
257 bsv_file
.write(copyright
+ '''
260 interface Ifc_PintTop;
261 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
262 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
263 interface PeripheralSide peripheral_side;
266 module mkPinTop(Ifc_PintTop);
267 // instantiate the pin-mux module here
268 Ifc_pinmux pinmux <-mkpinmux;
270 // declare the registers which will be used to mux the IOs
271 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
273 cell_bit_width
= str(p
.cell_bitwidth
)
274 for cell
in p
.muxed_cells
:
276 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
277 cell_bit_width
, cell
[0]))
280 // rule to connect the registers to the selection lines of the
282 rule connect_selection_registers;''')
284 for cell
in p
.muxed_cells
:
286 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
290 // method definitions for the write user interface
291 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
293 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
294 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
296 for cell
in p
.muxed_cells
:
298 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
308 // method definitions for the read user interface
309 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
312 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
313 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
315 for cell
in p
.muxed_cells
:
317 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
323 return tuple2(err,data);
325 interface peripheral_side=pinmux.peripheral_side;
331 def write_bvp(bvp
, p
, ifaces
):
332 # ######## Generate bus transactors ################
333 gpiocfg
= '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
334 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
335 muxcfg
= '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
336 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
338 gpiodec
= '\tGPIO#({0}) mygpio{1} <- mkgpio();'
339 muxdec
= '\tMUX#({0}) mymux{1} <- mkmux();'
340 gpioifc
= '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
341 '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
342 muxifc
= '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
343 '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
344 with
open(bvp
, 'w') as bsv_file
:
345 # assume here that all muxes have a 1:1 gpio
349 iks
= sorted(ifaces
.keys())
351 if not iname
.startswith('gpio'): # TODO: declare other interfaces
355 npins
= len(ifc
.pinspecs
)
356 cfg
.append(gpiocfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
359 cfg
.append(muxcfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
362 decl
.append(gpiodec
.format(npins
, bank
))
363 decl
.append(muxdec
.format(npins
, bank
))
364 idec
.append(gpioifc
.format(bank
))
365 idec
.append(muxifc
.format(bank
))
368 print dir(ifaces
['gpioa'])
369 print ifaces
['gpioa'].pinspecs
370 gpiodecl
= '\n'.join(decl
) + '\n' + '\n'.join(idec
)
371 gpiocfg
= '\n'.join(cfg
)
372 bsv_file
.write(axi4_lite
.format(gpiodecl
, gpiocfg
))
373 # ##################################################
376 def write_instances(idef
, p
, ifaces
):
377 with
open(idef
, 'w') as bsv_file
:
383 bsv_file
.write(txt
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))