1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
49 def pinmuxgen(pth
=None, verify
=True):
50 """ populating the file with the code
53 p
= Parse(pth
, verify
)
54 iocells
= Interfaces()
55 iocells
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
56 ifaces
= Interfaces(pth
)
57 #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
62 bp
= os
.path
.join(pth
, bp
)
63 if not os
.path
.exists(bp
):
65 bl
= os
.path
.join(bp
, 'bsv_lib')
66 if not os
.path
.exists(bl
):
69 cwd
= os
.path
.split(__file__
)[0]
71 # copy over template and library files
72 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
73 os
.path
.join(bp
, 'Makefile'))
74 cwd
= os
.path
.join(cwd
, 'bsv_lib')
75 for fname
in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
76 shutil
.copyfile(os
.path
.join(cwd
, fname
),
77 os
.path
.join(bl
, fname
))
79 bus
= os
.path
.join(bp
, 'busenable.bsv')
80 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
81 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
82 bvp
= os
.path
.join(bp
, 'bus.bsv')
84 write_pmp(pmp
, p
, ifaces
, iocells
)
85 write_ptp(ptp
, p
, ifaces
)
86 write_bvp(bvp
, p
, ifaces
)
87 write_bus(bus
, p
, ifaces
)
90 def write_bus(bus
, p
, ifaces
):
91 # package and interface declaration followed by
92 # the generic io_cell definition
93 with
open(bus
, "w") as bsv_file
:
94 ifaces
.busfmt(bsv_file
)
97 def write_pmp(pmp
, p
, ifaces
, iocells
):
98 # package and interface declaration followed by
99 # the generic io_cell definition
100 with
open(pmp
, "w") as bsv_file
:
101 bsv_file
.write(header
)
103 cell_bit_width
= 'Bit#(%d)' % p
.cell_bitwidth
105 interface MuxSelectionLines;
107 // declare the method which will capture the user pin-mux
108 // selection values.The width of the input is dependent on the number
109 // of muxes happening per IO. For now we have a generalized width
110 // where each IO will have the same number of muxes.''')
112 for cell
in p
.muxed_cells
:
113 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cell_bit_width
))
115 bsv_file
.write("\n endinterface\n")
119 interface PeripheralSide;
120 // declare the interface to the peripherals
121 // Each IO cell will have 3 input field (output from pin mux
122 // and on output field (input to pinmux)''')
123 # ==============================================================
125 # == create method definitions for all peripheral interfaces ==#
126 iocells
.ifacefmt(bsv_file
)
128 # ===== finish interface definition and start module definition=======
129 bsv_file
.write("\n endinterface\n")
131 # ===== io cell definition =======
134 interface IOCellSide;
135 // declare the interface to the IO cells.
136 // Each IO cell will have 3 input field (output from pin mux
137 // and on output field (input to pinmux)''')
139 # == create method definitions for all iocell interfaces ==#
140 ifaces
.ifacefmt(bsv_file
)
141 bsv_file
.write("\n endinterface\n")
143 # ===== finish interface definition and start module definition=======
146 interface Ifc_pinmux;
147 interface MuxSelectionLines mux_lines;
148 interface PeripheralSide peripheral_side;
149 interface IOCellSide iocell_side;
152 module mkpinmux(Ifc_pinmux);
154 # ====================================================================
156 # ======================= create wire and registers =================#
158 // the followins wires capture the pin-mux selection
159 // values for each mux assigned to a CELL
161 for cell
in p
.muxed_cells
:
162 bsv_file
.write(mux_interface
.wirefmt(
163 cell
[0], cell_bit_width
))
165 iocells
.wirefmt(bsv_file
)
166 ifaces
.wirefmt(bsv_file
)
169 # ====================================================================
170 # ========================= Actual pinmuxing ========================#
172 /*====== This where the muxing starts for each io-cell======*/
174 bsv_file
.write(p
.pinmux
)
176 /*============================================================*/
178 # ====================================================================
179 # ================= interface definitions for each method =============#
181 interface mux_lines = interface MuxSelectionLines
183 for cell
in p
.muxed_cells
:
185 mux_interface
.ifacedef(
186 cell
[0], cell_bit_width
))
187 bsv_file
.write("\n endinterface;")
190 interface iocell_side = interface IOCellSide
192 iocells
.ifacedef(bsv_file
)
193 bsv_file
.write("\n endinterface;")
196 interface peripheral_side = interface PeripheralSide
198 ifaces
.ifacedef(bsv_file
)
199 bsv_file
.write("\n endinterface;")
202 bsv_file
.write(footer
)
203 print("BSV file successfully generated: bsv_src/pinmux.bsv")
204 # ======================================================================
207 def write_ptp(ptp
, p
, ifaces
):
208 with
open(ptp
, 'w') as bsv_file
:
209 bsv_file
.write(copyright
+ '''
212 interface Ifc_PintTop;
213 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
214 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
215 interface PeripheralSide peripheral_side;
218 module mkPinTop(Ifc_PintTop);
219 // instantiate the pin-mux module here
220 Ifc_pinmux pinmux <-mkpinmux;
222 // declare the registers which will be used to mux the IOs
223 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
225 cell_bit_width
= str(p
.cell_bitwidth
)
226 for cell
in p
.muxed_cells
:
228 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
229 cell_bit_width
, cell
[0]))
232 // rule to connect the registers to the selection lines of the
234 rule connect_selection_registers;''')
236 for cell
in p
.muxed_cells
:
238 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
242 // method definitions for the write user interface
243 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
245 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
246 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
248 for cell
in p
.muxed_cells
:
250 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
260 // method definitions for the read user interface
261 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
264 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
265 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
267 for cell
in p
.muxed_cells
:
269 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
275 return tuple2(err,data);
277 interface peripheral_side=pinmux.peripheral_side;
283 def write_bvp(bvp
, p
, ifaces
):
284 # ######## Generate bus transactors ################
285 with
open(bvp
, 'w') as bsv_file
:
286 bsv_file
.write(axi4_lite
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
287 # ##################################################