1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
52 def pinmuxgen(pth
=None, verify
=True):
53 """ populating the file with the code
56 p
= Parse(pth
, verify
)
57 iocells
= Interfaces()
58 iocells
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
59 ifaces
= Interfaces(pth
)
60 #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
65 bp
= os
.path
.join(pth
, bp
)
66 if not os
.path
.exists(bp
):
68 bl
= os
.path
.join(bp
, 'bsv_lib')
69 if not os
.path
.exists(bl
):
72 cwd
= os
.path
.split(__file__
)[0]
74 # copy over template and library files
75 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
76 os
.path
.join(bp
, 'Makefile'))
77 cwd
= os
.path
.join(cwd
, 'bsv_lib')
79 shutil
.copyfile(os
.path
.join(cwd
, fname
),
80 os
.path
.join(bl
, fname
))
82 bus
= os
.path
.join(bp
, 'busenable.bsv')
83 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
84 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
85 bvp
= os
.path
.join(bp
, 'bus.bsv')
86 idef
= os
.path
.join(bp
, 'instance_defines.bsv')
87 slow
= os
.path
.join(bp
, 'slow_peripherals.bsv')
88 slowt
= os
.path
.join(cwd
, 'slow_peripherals_template.bsv')
89 soc
= os
.path
.join(bp
, 'soc.bsv')
90 soct
= os
.path
.join(cwd
, 'soc_template.bsv')
92 write_pmp(pmp
, p
, ifaces
, iocells
)
93 write_ptp(ptp
, p
, ifaces
)
94 write_bvp(bvp
, p
, ifaces
)
95 write_bus(bus
, p
, ifaces
)
96 write_instances(idef
, p
, ifaces
)
97 write_slow(slow
, slowt
, p
, ifaces
, iocells
)
98 write_soc(soc
, soct
, p
, ifaces
, iocells
)
101 def write_slow(slow
, slowt
, p
, ifaces
, iocells
):
102 """ write out the slow_peripherals.bsv file.
103 joins all the peripherals together into one AXI Lite interface
105 with
open(slowt
) as bsv_file
:
106 slowt
= bsv_file
.read()
107 imports
= ifaces
.slowimport()
108 ifdecl
= ifaces
.slowifdeclmux() + '\n' + ifaces
.extifdecl()
109 regdef
= ifaces
.axi_reg_def()
110 slavedecl
= ifaces
.axi_slave_idx()
111 fnaddrmap
= ifaces
.axi_addr_map()
112 mkslow
= ifaces
.mkslow_peripheral()
113 mkcon
= ifaces
.mk_connection()
114 mkcellcon
= ifaces
.mk_cellconn()
115 pincon
= ifaces
.mk_pincon()
116 inst
= ifaces
.extifinstance()
117 inst2
= ifaces
.extifinstance2()
118 mkplic
= ifaces
.mk_plic()
119 numsloirqs
= ifaces
.mk_sloirqsdef()
120 ifacedef
= ifaces
.mk_ext_ifacedef()
121 ifacedef
= ifaces
.mk_ext_ifacedef()
122 with
open(slow
, "w") as bsv_file
:
123 bsv_file
.write(slowt
.format(imports
, ifdecl
, regdef
, slavedecl
,
124 fnaddrmap
, mkslow
, mkcon
, mkcellcon
,
125 pincon
, inst
, mkplic
,
126 numsloirqs
, ifacedef
,
130 def write_soc(soc
, soct
, p
, ifaces
, iocells
):
131 """ write out the soc.bsv file.
132 joins all the peripherals together as AXI Masters
134 ifaces
.fastbusmode
= True # side-effects... shouldn't really do this
135 with
open(soct
) as bsv_file
:
136 soct
= bsv_file
.read()
137 imports
= ifaces
.slowimport()
138 ifdecl
= ifaces
.fastifdecl()
139 #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
140 regdef
= ifaces
.axi_reg_def()
141 slavedecl
= ifaces
.axi_fastslave_idx()
142 mastdecl
= ifaces
.axi_master_idx()
143 fnaddrmap
= ifaces
.axi_addr_map()
144 mkfast
= ifaces
.mkfast_peripheral()
145 mkcon
= ifaces
.mk_fast_connection()
146 mkcellcon
= ifaces
.mk_cellconn()
147 pincon
= ifaces
.mk_pincon()
148 inst
= ifaces
.extfastifinstance()
149 mkplic
= ifaces
.mk_plic()
150 numsloirqs
= ifaces
.mk_sloirqsdef()
151 ifacedef
= ifaces
.mk_ext_ifacedef()
152 dma
= ifaces
.mk_dma_irq()
153 num_dmachannels
= ifaces
.num_dmachannels()
154 with
open(soc
, "w") as bsv_file
:
155 bsv_file
.write(soct
.format(imports
, ifdecl
, mkfast
,
156 slavedecl
, mastdecl
, mkcon
,
157 inst
, dma
, num_dmachannels
,
161 def write_bus(bus
, p
, ifaces
):
162 # package and interface declaration followed by
163 # the generic io_cell definition
164 with
open(bus
, "w") as bsv_file
:
165 ifaces
.busfmt(bsv_file
)
168 def write_pmp(pmp
, p
, ifaces
, iocells
):
169 # package and interface declaration followed by
170 # the generic io_cell definition
171 with
open(pmp
, "w") as bsv_file
:
172 bsv_file
.write(header
)
174 cell_bit_width
= 'Bit#(%d)' % p
.cell_bitwidth
176 (*always_ready,always_enabled*)
177 interface MuxSelectionLines;
179 // declare the method which will capture the user pin-mux
180 // selection values.The width of the input is dependent on the number
181 // of muxes happening per IO. For now we have a generalized width
182 // where each IO will have the same number of muxes.''')
184 for cell
in p
.muxed_cells
:
185 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cell_bit_width
))
187 bsv_file
.write("\n endinterface\n")
191 interface IOCellSide;
192 // declare the interface to the IO cells.
193 // Each IO cell will have 1 input field (output from pin mux)
194 // and an output and out-enable field (input to pinmux)''')
196 # == create method definitions for all iocell interfaces ==#
197 iocells
.ifacefmt(bsv_file
)
199 # ===== finish interface definition and start module definition=======
200 bsv_file
.write("\n endinterface\n")
202 ifaces
.ifacepfmt(bsv_file
)
203 # ===== io cell definition =======
205 (*always_ready,always_enabled*)
206 interface PeripheralSide;
207 // declare the interface to the peripherals
208 // Each peripheral's function will be either an input, output
209 // or be bi-directional. an input field will be an output from the
210 // peripheral and an output field will be an input to the peripheral.
211 // Bi-directional functions also have an output-enable (which
212 // again comes *in* from the peripheral)''')
213 # ==============================================================
215 # == create method definitions for all peripheral interfaces ==#
216 ifaces
.ifacefmt2(bsv_file
)
217 bsv_file
.write("\n endinterface\n")
219 # ===== finish interface definition and start module definition=======
222 interface Ifc_pinmux;
223 // this interface controls how each IO cell is routed. setting
224 // any given IO cell's mux control value will result in redirection
225 // of not just the input or output to different peripheral functions
226 // but also the *direction* control - if appropriate - as well.
227 interface MuxSelectionLines mux_lines;
229 // this interface contains the inputs, outputs and direction-control
230 // lines for all peripherals. GPIO is considered to also be just
231 // a peripheral because it also has in, out and direction-control.
232 interface PeripheralSide peripheral_side;
234 // this interface is to be linked to the individual IO cells.
235 // if looking at a "non-muxed" GPIO design, basically the
236 // IO cell input, output and direction-control wires are cut
237 // (giving six pairs of dangling wires, named left and right)
238 // these iocells are routed in their place on one side ("left")
239 // and the matching *GPIO* peripheral interfaces in/out/dir
240 // connect to the OTHER side ("right"). the result is that
241 // the muxer settings end up controlling the routing of where
242 // the I/O from the IOcell actually goes.
243 interface IOCellSide iocell_side;
247 module mkpinmux(Ifc_pinmux);
249 # ====================================================================
251 # ======================= create wire and registers =================#
253 // the followins wires capture the pin-mux selection
254 // values for each mux assigned to a CELL
256 for cell
in p
.muxed_cells
:
257 bsv_file
.write(mux_interface
.wirefmt(
258 cell
[0], cell_bit_width
))
260 iocells
.wirefmt(bsv_file
)
261 ifaces
.wirefmt(bsv_file
)
264 # ====================================================================
265 # ========================= Actual pinmuxing ========================#
267 /*====== This where the muxing starts for each io-cell======*/
268 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
270 bsv_file
.write(p
.pinmux
)
272 /*============================================================*/
274 # ====================================================================
275 # ================= interface definitions for each method =============#
277 interface mux_lines = interface MuxSelectionLines
279 for cell
in p
.muxed_cells
:
281 mux_interface
.ifacedef(
282 cell
[0], cell_bit_width
))
283 bsv_file
.write("\n endinterface;")
287 interface iocell_side = interface IOCellSide
289 iocells
.ifacedef(bsv_file
)
290 bsv_file
.write("\n endinterface;")
294 interface peripheral_side = interface PeripheralSide
296 ifaces
.ifacedef2(bsv_file
)
297 bsv_file
.write("\n endinterface;")
299 bsv_file
.write(footer
)
300 print("BSV file successfully generated: bsv_src/pinmux.bsv")
301 # ======================================================================
304 def write_ptp(ptp
, p
, ifaces
):
305 with
open(ptp
, 'w') as bsv_file
:
306 bsv_file
.write(copyright
+ '''
309 interface Ifc_PintTop;
310 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
311 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
312 interface PeripheralSide peripheral_side;
315 module mkPinTop(Ifc_PintTop);
316 // instantiate the pin-mux module here
317 Ifc_pinmux pinmux <-mkpinmux;
319 // declare the registers which will be used to mux the IOs
320 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
322 cell_bit_width
= str(p
.cell_bitwidth
)
323 for cell
in p
.muxed_cells
:
325 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
326 cell_bit_width
, cell
[0]))
329 // rule to connect the registers to the selection lines of the
331 rule connect_selection_registers;''')
333 for cell
in p
.muxed_cells
:
335 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
339 // method definitions for the write user interface
340 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
342 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
343 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
345 for cell
in p
.muxed_cells
:
347 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
357 // method definitions for the read user interface
358 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
361 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
362 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
364 for cell
in p
.muxed_cells
:
366 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
372 return tuple2(err,data);
374 interface peripheral_side=pinmux.peripheral_side;
380 def write_bvp(bvp
, p
, ifaces
):
381 # ######## Generate bus transactors ################
382 gpiocfg
= '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
383 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
384 muxcfg
= '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
385 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
387 gpiodec
= '\tGPIO#({0}) mygpio{1} <- mkgpio();'
388 muxdec
= '\tMUX#({0}) mymux{1} <- mkmux();'
389 gpioifc
= '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
390 '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
391 muxifc
= '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
392 '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
393 with
open(bvp
, 'w') as bsv_file
:
394 # assume here that all muxes have a 1:1 gpio
398 iks
= sorted(ifaces
.keys())
400 if not iname
.startswith('gpio'): # TODO: declare other interfaces
404 npins
= len(ifc
.pinspecs
)
405 cfg
.append(gpiocfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
408 cfg
.append(muxcfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
411 decl
.append(gpiodec
.format(npins
, bank
))
412 decl
.append(muxdec
.format(npins
, bank
))
413 idec
.append(gpioifc
.format(bank
))
414 idec
.append(muxifc
.format(bank
))
417 print dir(ifaces
['gpioa'])
418 print ifaces
['gpioa'].pinspecs
419 gpiodecl
= '\n'.join(decl
) + '\n' + '\n'.join(idec
)
420 gpiocfg
= '\n'.join(cfg
)
421 bsv_file
.write(axi4_lite
.format(gpiodecl
, gpiocfg
))
422 # ##################################################
425 def write_instances(idef
, p
, ifaces
):
426 with
open(idef
, 'w') as bsv_file
:
431 `define Reg_width {1}
434 // TODO: work out if these are needed
438 `define DCACHE_BLOCK_SIZE 4
439 `define DCACHE_WORD_SIZE 8
440 `define PERFMONITORS 64
441 `define DCACHE_WAYS 4
442 `define DCACHE_TAG_BITS 20 // tag_bits = 52
444 `define PLICBase 'h0c000000
445 `define PLICEnd 'h10000000
446 `define INTERRUPT_PINS 64
448 `define BAUD_RATE 130
450 `define BAUD_RATE 5 //130 //
453 bsv_file
.write(txt
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))