1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
25 # project module imports
26 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
27 from parse
import Parse
28 from bsv
.actual_pinmux
import init
29 from bsv
.bus_transactors
import axi4_lite
33 This BSV file has been generated by the PinMux tool available at:
34 https://bitbucket.org/casl/pinmux.
36 Authors: Neel Gala, Luke
37 Date of generation: ''' + time
.strftime("%c") + '''
40 header
= copyright
+ '''
43 // FunctionType: contains the active wires of a function. That INCLUDES
44 // GPIO (as GPIO is also a "Function"). These are what get muxed.
45 // However, only GPIO "Functions" will end up with Register SRAMs.
47 Bit#(1) outputval; // output from function to pad bit2
48 Bit#(1) inputval; // input from pad to function bit1
49 Bit#(1) output_en; // output enable from core to pad bit0
50 } FunctionType deriving(Eq,Bits,FShow);
53 Bit#(1) outputval; // output from core to pad bit7
54 Bit#(1) output_en; // output enable from core to pad bit6
55 Bit#(1) input_en; // input enable from core to io_cell bit5
56 } GenericIOType deriving(Eq,Bits,FShow);
66 def pinmuxgen(pth
=None, verify
=True):
67 """ populating the file with the code
70 p
= Parse(pth
, verify
)
71 ifaces
= Interfaces(pth
)
72 ifaces
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
77 bp
= os
.path
.join(pth
, bp
)
78 if not os
.path
.exists(bp
):
80 bl
= os
.path
.join(bp
, 'bsv_lib')
81 if not os
.path
.exists(bl
):
84 cwd
= os
.path
.split(__file__
)[0]
86 # copy over template and library files
87 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
88 os
.path
.join(bp
, 'Makefile'))
89 cwd
= os
.path
.join(cwd
, 'bsv_lib')
90 for fname
in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
91 shutil
.copyfile(os
.path
.join(cwd
, fname
),
92 os
.path
.join(bl
, fname
))
94 bus
= os
.path
.join(bp
, 'busenable.bsv')
95 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
96 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
97 bvp
= os
.path
.join(bp
, 'bus.bsv')
99 write_pmp(pmp
, p
, ifaces
)
100 write_ptp(ptp
, p
, ifaces
)
101 write_bvp(bvp
, p
, ifaces
)
102 write_bus(bus
, p
, ifaces
)
105 def write_bus(bus
, p
, ifaces
):
106 # package and interface declaration followed by
107 # the generic io_cell definition
108 with
open(bus
, "w") as bsv_file
:
109 ifaces
.busfmt(bsv_file
)
112 def get_cell_bit_width(p
):
114 for cell
in p
.muxed_cells
:
115 max_num_cells
= max(len(cell
) - 1, max_num_cells
)
116 return int(math
.log(max_num_cells
, 2))
119 def write_pmp(pmp
, p
, ifaces
):
120 # package and interface declaration followed by
121 # the generic io_cell definition
122 with
open(pmp
, "w") as bsv_file
:
123 bsv_file
.write(header
)
126 interface MuxSelectionLines;
128 // declare the method which will capture the user pin-mux
129 // selection values.The width of the input is dependent on the number
130 // of muxes happening per IO. For now we have a generalized width
131 // where each IO will have the same number of muxes.''')
133 for cell
in p
.muxed_cells
:
134 cnum
= 'Bit#(' + str(int(math
.log(len(cell
) - 1, 2))) + ')'
135 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cnum
))
140 interface PeripheralSide;
141 // declare the interface to the IO cells.
142 // Each IO cell will have 8 input field (output from pin mux
143 // and on output field (input to pinmux)''')
144 # ==============================================================
146 # == create method definitions for all peripheral interfaces ==#
147 ifaces
.ifacefmt(bsv_file
)
149 # ==============================================================
151 # ===== finish interface definition and start module definition=======
155 interface Ifc_pinmux;
156 interface MuxSelectionLines mux_lines;
157 interface PeripheralSide peripheral_side;
160 module mkpinmux(Ifc_pinmux);
162 # ====================================================================
164 # ======================= create wire and registers =================#
166 // the followins wires capture the pin-mux selection
167 // values for each mux assigned to a CELL
169 cell_bit_width
= 'Bit#(%d)' % get_cell_bit_width(p
)
170 for cell
in p
.muxed_cells
:
171 bsv_file
.write(mux_interface
.wirefmt(
172 cell
[0], cell_bit_width
))
174 ifaces
.wirefmt(bsv_file
)
177 # ====================================================================
178 # ========================= Actual pinmuxing ========================#
180 /*====== This where the muxing starts for each io-cell======*/
182 bsv_file
.write(p
.pinmux
)
184 /*============================================================*/
186 # ====================================================================
187 # ================= interface definitions for each method =============#
189 interface mux_lines = interface MuxSelectionLines
191 for cell
in p
.muxed_cells
:
193 mux_interface
.ifacedef(
194 cell
[0], cell_bit_width
))
197 interface peripheral_side = interface PeripheralSide
199 ifaces
.ifacedef(bsv_file
)
200 bsv_file
.write(footer
)
201 print("BSV file successfully generated: bsv_src/pinmux.bsv")
202 # ======================================================================
205 def write_ptp(ptp
, p
, ifaces
):
206 with
open(ptp
, 'w') as bsv_file
:
207 bsv_file
.write(copyright
+ '''
210 interface Ifc_PintTop;
211 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
212 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
213 interface PeripheralSide peripheral_side;
216 module mkPinTop(Ifc_PintTop);
217 // instantiate the pin-mux module here
218 Ifc_pinmux pinmux <-mkpinmux;
220 // declare the registers which will be used to mux the IOs
221 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
223 cell_bit_width
= str(get_cell_bit_width(p
))
224 for cell
in p
.muxed_cells
:
226 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
227 cell_bit_width
, cell
[0]))
230 // rule to connect the registers to the selection lines of the
232 rule connect_selection_registers;''')
234 for cell
in p
.muxed_cells
:
236 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
240 // method definitions for the write user interface
241 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
243 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
244 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
246 for cell
in p
.muxed_cells
:
248 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
258 // method definitions for the read user interface
259 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
262 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
263 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
265 for cell
in p
.muxed_cells
:
267 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
273 return tuple2(err,data);
275 interface peripheral_side=pinmux.peripheral_side;
281 def write_bvp(bvp
, p
, ifaces
):
282 # ######## Generate bus transactors ################
283 with
open(bvp
, 'w') as bsv_file
:
284 bsv_file
.write(axi4_lite
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
285 # ##################################################