1 # Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
2 # Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (c) 2018-2020 Florent Kermarrec <florent@enjoy-digital.fr>
4 # Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
6 # Based on code from LambaConcept, from the gram example which is BSD-2-License
7 # https://github.com/jeanthom/gram/tree/master/examples
9 # Modifications for the Libre-SOC Project funded by NLnet and NGI POINTER
10 # under EU Grants 871528 and 957073, under the LGPLv3+ License
13 from nmigen
import (Elaboratable
, Module
, Signal
, ClockDomain
, Instance
,
14 ClockSignal
, ResetSignal
, Const
)
19 class PLL(Elaboratable
):
21 clki_div_range
= (1, 128+1)
22 clkfb_div_range
= (1, 128+1)
23 clko_div_range
= (1, 128+1)
24 clki_freq_range
= ( 8e6
, 400e6
)
25 clko_freq_range
= (3.125e6
, 400e6
)
26 vco_freq_range
= ( 400e6
, 800e6
)
28 def __init__(self
, clkin
,
29 clksel
=Signal(shape
=2, reset
=2),
30 reset
=Signal(reset_less
=True),
33 self
.clkin_freq
= None
47 ] + list(self
.clkouts
.values())
49 def set_clkin_freq(self
, freq
):
50 (clki_freq_min
, clki_freq_max
) = self
.clki_freq_range
51 assert freq
>= clki_freq_min
52 assert freq
<= clki_freq_max
53 self
.clkin_freq
= freq
55 def create_clkout(self
, cd
, freq
, phase
=0, margin
=1e-2):
56 (clko_freq_min
, clko_freq_max
) = self
.clko_freq_range
57 assert freq
>= clko_freq_min
58 assert freq
<= clko_freq_max
59 assert self
.nclkouts
< self
.nclkouts_max
60 self
.clkouts
[self
.nclkouts
] = (cd
, freq
, phase
, margin
)
61 #create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
62 print("clock domain", cd
.domain
, freq
, margin
, self
.nclkouts
)
65 def compute_config(self
):
67 for clki_div
in range(*self
.clki_div_range
):
68 config
["clki_div"] = clki_div
69 for clkfb_div
in range(*self
.clkfb_div_range
):
71 vco_freq
= self
.clkin_freq
/clki_div
*clkfb_div
*1 # clkos3_div=1
72 (vco_freq_min
, vco_freq_max
) = self
.vco_freq_range
73 if vco_freq
>= vco_freq_min
and vco_freq
<= vco_freq_max
:
74 for n
, (clk
, f
, p
, m
) in sorted(self
.clkouts
.items()):
76 for d
in range(*self
.clko_div_range
):
78 if abs(clk_freq
- f
) <= f
*m
:
79 config
["clko{}_freq".format(n
)] = clk_freq
80 config
["clko{}_div".format(n
)] = d
81 config
["clko{}_phase".format(n
)] = p
89 config
["vco"] = vco_freq
90 config
["clkfb_div"] = clkfb_div
91 #compute_config_log(self.logger, config)
92 print ("PLL config", config
)
94 raise ValueError("No PLL config found")
96 def elaborate(self
, platform
):
97 config
= self
.compute_config()
101 a_FREQUENCY_PIN_CLKI
= str(self
.clkin_freq
/1e6
),
103 a_LPF_RESISTOR
= "16",
104 a_MFG_ENABLE_FILTEROPAMP
= "1",
105 a_MFG_GMCREF_SEL
= "2",
107 p_FEEDBK_PATH
= "INT_OS3", # CLKOS3 rsvd for feedback with div=1.
108 p_CLKOS3_ENABLE
= "ENABLED",
110 p_CLKFB_DIV
= config
["clkfb_div"],
111 p_CLKI_DIV
= config
["clki_div"],
112 # reset, input clock, lock-achieved output
115 o_LOCK
= self
.locked
,
117 # for each clock-out, set additional parameters
118 for n
, (clk
, f
, p
, m
) in sorted(self
.clkouts
.items()):
119 n_to_l
= {0: "P", 1: "S", 2: "S2"}
120 div
= config
["clko{}_div".format(n
)]
121 cphase
= int(p
*(div
+ 1)/360 + div
)
122 self
.params
["p_CLKO{}_ENABLE".format(n_to_l
[n
])] = "ENABLED"
123 self
.params
["p_CLKO{}_DIV".format(n_to_l
[n
])] = div
124 self
.params
["p_CLKO{}_FPHASE".format(n_to_l
[n
])] = 0
125 self
.params
["p_CLKO{}_CPHASE".format(n_to_l
[n
])] = cphase
126 self
.params
["o_CLKO{}".format(n_to_l
[n
])] = clk
129 print ("params", self
.params
)
130 pll
= Instance("EHXPLLL", **self
.params
)
131 m
.submodules
.pll
= pll
134 pll
= Instance("EHXPLLL",
135 p_OUTDIVIDER_MUXA
='DIVA',
136 p_OUTDIVIDER_MUXB
='DIVB',
137 p_CLKOP_ENABLE
='ENABLED',
138 p_CLKOS_ENABLE
='ENABLED',
139 p_CLKOS2_ENABLE
='DISABLED',
140 p_CLKOS3_ENABLE
='DISABLED',
141 p_CLKOP_DIV
=self
.CLKOP_DIV
,
142 p_CLKOS_DIV
=self
.CLKOS_DIV
,
143 p_CLKFB_DIV
=self
.CLKFB_DIV
,
144 p_CLKI_DIV
=self
.CLKI_DIV
,
145 p_FEEDBK_PATH
='INT_OP',
146 p_CLKOP_TRIM_POL
="FALLING",
147 p_CLKOP_TRIM_DELAY
=0,
148 p_CLKOS_TRIM_POL
="FALLING",
149 p_CLKOS_TRIM_DELAY
=0,
163 o_CLKOP
=self
.clkout1
,
164 o_CLKOS
=self
.clkout2
,
165 o_CLKOS2
=self
.clkout3
,
166 o_CLKOS3
=self
.clkout4
,
171 class ECP5CRG(Elaboratable
):
172 def __init__(self
, sys_clk_freq
=100e6
):
173 self
.sys_clk_freq
= sys_clk_freq
175 def elaborate(self
, platform
):
178 # Get 100Mhz from oscillator
179 extclk
= platform
.request(platform
.default_clk
)
180 cd_rawclk
= ClockDomain("rawclk", local
=True, reset_less
=True)
181 m
.d
.comb
+= cd_rawclk
.clk
.eq(extclk
)
182 m
.domains
+= cd_rawclk
185 if platform
.default_rst
is not None:
186 reset
= platform
.request(platform
.default_rst
).i
188 reset
= Const(0) # whoops
194 Instance("FD1S3AX", p_GSR
="DISABLED",
195 i_CK
=ClockSignal("rawclk"),
198 Instance("FD1S3AX", p_GSR
="DISABLED",
199 i_CK
=ClockSignal("rawclk"),
202 Instance("SGSR", i_CLK
=ClockSignal("rawclk"),
207 m
.submodules
.pll
= pll
= PLL(ClockSignal("rawclk"), reset
=~reset
)
209 # Power-on delay (655us)
210 podcnt
= Signal(25, reset
=-1)
212 with m
.If((podcnt
!= 0) & pll
.locked
):
213 m
.d
.rawclk
+= podcnt
.eq(podcnt
-1)
214 m
.d
.rawclk
+= pod_done
.eq(podcnt
== 0)
216 # Generating sync2x (200Mhz) and init (25Mhz) from extclk
217 cd_sync2x
= ClockDomain("sync2x", local
=False)
218 cd_sync2x_unbuf
= ClockDomain("sync2x_unbuf",
219 local
=False, reset_less
=True)
220 cd_init
= ClockDomain("init", local
=False)
221 cd_sync
= ClockDomain("sync", local
=False)
222 cd_dramsync
= ClockDomain("dramsync", local
=False)
225 pll
.set_clkin_freq(platform
.default_clk_frequency
)
226 pll
.create_clkout(ClockSignal("sync2x_unbuf"), 2*self
.sys_clk_freq
)
227 pll
.create_clkout(ClockSignal("init"), 25e6
)
228 m
.submodules
+= Instance("ECLKSYNCB",
229 i_ECLKI
= ClockSignal("sync2x_unbuf"),
231 o_ECLKO
= ClockSignal("sync2x"))
232 m
.domains
+= cd_sync2x_unbuf
233 m
.domains
+= cd_sync2x
236 m
.domains
+= cd_dramsync
237 reset_ok
= Signal(reset_less
=True)
238 m
.d
.comb
+= reset_ok
.eq(~pll
.locked|~pod_done
)
239 m
.d
.comb
+= ResetSignal("init").eq(reset_ok
)
240 m
.d
.comb
+= ResetSignal("sync").eq(reset_ok
)
241 m
.d
.comb
+= ResetSignal("dramsync").eq(reset_ok
)
243 # # Generating sync (100Mhz) from sync2x
245 m
.submodules
+= Instance("CLKDIVF",
248 i_CLKI
=ClockSignal("sync2x"),
250 o_CDIVX
=ClockSignal("sync"))
252 # temporarily set dram sync clock exactly equal to main sync
253 m
.d
.comb
+= ClockSignal("dramsync").eq(ClockSignal("sync"))