2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "common/freedreno_guardband.h"
29 #include "tu_private.h"
31 #include "ir3/ir3_nir.h"
32 #include "main/menums.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "util/debug.h"
37 #include "util/mesa-sha1.h"
38 #include "util/u_atomic.h"
39 #include "vk_format.h"
44 /* Emit IB that preloads the descriptors that the shader uses */
47 emit_load_state(struct tu_cs
*cs
, unsigned opcode
, enum a6xx_state_type st
,
48 enum a6xx_state_block sb
, unsigned base
, unsigned offset
,
51 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
52 * clear if emitting more packets will even help anything. Presumably the
53 * descriptor cache is relatively small, and these packets stop doing
54 * anything when there are too many descriptors.
56 tu_cs_emit_pkt7(cs
, opcode
, 3);
58 CP_LOAD_STATE6_0_STATE_TYPE(st
) |
59 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS
) |
60 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
61 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count
, 1024-1)));
62 tu_cs_emit_qw(cs
, offset
| (base
<< 28));
66 tu6_load_state_size(struct tu_pipeline
*pipeline
, bool compute
)
68 const unsigned load_state_size
= 4;
70 for (unsigned i
= 0; i
< pipeline
->layout
->num_sets
; i
++) {
71 if (pipeline
&& !(pipeline
->active_desc_sets
& (1u << i
)))
74 struct tu_descriptor_set_layout
*set_layout
= pipeline
->layout
->set
[i
].layout
;
75 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
76 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
78 /* Note: some users, like amber for example, pass in
79 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
80 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
82 VkShaderStageFlags stages
= compute
?
83 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
84 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
85 unsigned stage_count
= util_bitcount(stages
);
87 if (!binding
->array_size
)
90 switch (binding
->type
) {
91 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
92 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
93 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
94 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
95 /* IBO-backed resources only need one packet for all graphics stages */
96 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
)
98 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)
101 case VK_DESCRIPTOR_TYPE_SAMPLER
:
102 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
103 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
104 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
105 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
106 /* Textures and UBO's needs a packet for each stage */
109 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
110 /* Because of how we pack combined images and samplers, we
111 * currently can't use one packet for the whole array.
113 count
= stage_count
* binding
->array_size
* 2;
115 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
118 unreachable("bad descriptor type");
120 size
+= count
* load_state_size
;
127 tu6_emit_load_state(struct tu_pipeline
*pipeline
, bool compute
)
129 unsigned size
= tu6_load_state_size(pipeline
, compute
);
134 tu_cs_begin_sub_stream(&pipeline
->cs
, size
, &cs
);
136 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
137 for (unsigned i
= 0; i
< layout
->num_sets
; i
++) {
138 /* From 13.2.7. Descriptor Set Binding:
140 * A compatible descriptor set must be bound for all set numbers that
141 * any shaders in a pipeline access, at the time that a draw or
142 * dispatch command is recorded to execute using that pipeline.
143 * However, if none of the shaders in a pipeline statically use any
144 * bindings with a particular set number, then no descriptor set need
145 * be bound for that set number, even if the pipeline layout includes
146 * a non-trivial descriptor set layout for that set number.
148 * This means that descriptor sets unused by the pipeline may have a
149 * garbage or 0 BINDLESS_BASE register, which will cause context faults
150 * when prefetching descriptors from these sets. Skip prefetching for
151 * descriptors from them to avoid this. This is also an optimization,
152 * since these prefetches would be useless.
154 if (!(pipeline
->active_desc_sets
& (1u << i
)))
157 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[i
].layout
;
158 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
159 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
161 unsigned offset
= binding
->offset
/ 4;
162 /* Note: some users, like amber for example, pass in
163 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
164 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
166 VkShaderStageFlags stages
= compute
?
167 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
168 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
169 unsigned count
= binding
->array_size
;
170 if (count
== 0 || stages
== 0)
172 switch (binding
->type
) {
173 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
175 offset
= (layout
->set
[i
].dynamic_offset_start
+
176 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
178 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
179 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
180 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
181 /* IBO-backed resources only need one packet for all graphics stages */
182 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
) {
183 emit_load_state(&cs
, CP_LOAD_STATE6
, ST6_SHADER
, SB6_IBO
,
184 base
, offset
, count
);
186 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
) {
187 emit_load_state(&cs
, CP_LOAD_STATE6_FRAG
, ST6_IBO
, SB6_CS_SHADER
,
188 base
, offset
, count
);
191 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
192 /* nothing - input attachment doesn't use bindless */
194 case VK_DESCRIPTOR_TYPE_SAMPLER
:
195 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
196 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
: {
197 tu_foreach_stage(stage
, stages
) {
198 emit_load_state(&cs
, tu6_stage2opcode(stage
),
199 binding
->type
== VK_DESCRIPTOR_TYPE_SAMPLER
?
200 ST6_SHADER
: ST6_CONSTANTS
,
201 tu6_stage2texsb(stage
), base
, offset
, count
);
205 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
207 offset
= (layout
->set
[i
].dynamic_offset_start
+
208 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
210 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
: {
211 tu_foreach_stage(stage
, stages
) {
212 emit_load_state(&cs
, tu6_stage2opcode(stage
), ST6_UBO
,
213 tu6_stage2shadersb(stage
), base
, offset
, count
);
217 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
: {
218 tu_foreach_stage(stage
, stages
) {
219 /* TODO: We could emit less CP_LOAD_STATE6 if we used
220 * struct-of-arrays instead of array-of-structs.
222 for (unsigned i
= 0; i
< count
; i
++) {
223 unsigned tex_offset
= offset
+ 2 * i
* A6XX_TEX_CONST_DWORDS
;
224 unsigned sam_offset
= offset
+ (2 * i
+ 1) * A6XX_TEX_CONST_DWORDS
;
225 emit_load_state(&cs
, tu6_stage2opcode(stage
),
226 ST6_CONSTANTS
, tu6_stage2texsb(stage
),
227 base
, tex_offset
, 1);
228 emit_load_state(&cs
, tu6_stage2opcode(stage
),
229 ST6_SHADER
, tu6_stage2texsb(stage
),
230 base
, sam_offset
, 1);
236 unreachable("bad descriptor type");
241 pipeline
->load_state
= tu_cs_end_draw_state(&pipeline
->cs
, &cs
);
244 struct tu_pipeline_builder
246 struct tu_device
*device
;
247 struct tu_pipeline_cache
*cache
;
248 struct tu_pipeline_layout
*layout
;
249 const VkAllocationCallbacks
*alloc
;
250 const VkGraphicsPipelineCreateInfo
*create_info
;
252 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
253 struct ir3_shader_variant
*variants
[MESA_SHADER_STAGES
];
254 struct ir3_shader_variant
*binning_variant
;
255 uint64_t shader_iova
[MESA_SHADER_STAGES
];
256 uint64_t binning_vs_iova
;
258 bool rasterizer_discard
;
259 /* these states are affectd by rasterizer_discard */
260 VkSampleCountFlagBits samples
;
261 bool use_color_attachments
;
262 bool use_dual_src_blend
;
263 uint32_t color_attachment_count
;
264 VkFormat color_attachment_formats
[MAX_RTS
];
265 VkFormat depth_attachment_format
;
266 uint32_t render_components
;
270 tu_logic_op_reads_dst(VkLogicOp op
)
273 case VK_LOGIC_OP_CLEAR
:
274 case VK_LOGIC_OP_COPY
:
275 case VK_LOGIC_OP_COPY_INVERTED
:
276 case VK_LOGIC_OP_SET
:
284 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
286 /* treat dst alpha as 1.0 and avoid reading it */
288 case VK_BLEND_FACTOR_DST_ALPHA
:
289 return VK_BLEND_FACTOR_ONE
;
290 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
291 return VK_BLEND_FACTOR_ZERO
;
297 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor
)
300 case VK_BLEND_FACTOR_SRC1_COLOR
:
301 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
302 case VK_BLEND_FACTOR_SRC1_ALPHA
:
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
311 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo
*info
)
316 for (unsigned i
= 0; i
< info
->attachmentCount
; i
++) {
317 const VkPipelineColorBlendAttachmentState
*blend
= &info
->pAttachments
[i
];
318 if (tu_blend_factor_is_dual_src(blend
->srcColorBlendFactor
) ||
319 tu_blend_factor_is_dual_src(blend
->dstColorBlendFactor
) ||
320 tu_blend_factor_is_dual_src(blend
->srcAlphaBlendFactor
) ||
321 tu_blend_factor_is_dual_src(blend
->dstAlphaBlendFactor
))
329 tu6_emit_xs_config(struct tu_cs
*cs
,
330 gl_shader_stage stage
, /* xs->type, but xs may be NULL */
331 const struct ir3_shader_variant
*xs
,
332 uint64_t binary_iova
)
334 static const struct xs_config
{
335 uint16_t reg_sp_xs_ctrl
;
336 uint16_t reg_sp_xs_config
;
337 uint16_t reg_hlsq_xs_ctrl
;
338 uint16_t reg_sp_vs_obj_start
;
340 [MESA_SHADER_VERTEX
] = {
341 REG_A6XX_SP_VS_CTRL_REG0
,
342 REG_A6XX_SP_VS_CONFIG
,
343 REG_A6XX_HLSQ_VS_CNTL
,
344 REG_A6XX_SP_VS_OBJ_START_LO
,
346 [MESA_SHADER_TESS_CTRL
] = {
347 REG_A6XX_SP_HS_CTRL_REG0
,
348 REG_A6XX_SP_HS_CONFIG
,
349 REG_A6XX_HLSQ_HS_CNTL
,
350 REG_A6XX_SP_HS_OBJ_START_LO
,
352 [MESA_SHADER_TESS_EVAL
] = {
353 REG_A6XX_SP_DS_CTRL_REG0
,
354 REG_A6XX_SP_DS_CONFIG
,
355 REG_A6XX_HLSQ_DS_CNTL
,
356 REG_A6XX_SP_DS_OBJ_START_LO
,
358 [MESA_SHADER_GEOMETRY
] = {
359 REG_A6XX_SP_GS_CTRL_REG0
,
360 REG_A6XX_SP_GS_CONFIG
,
361 REG_A6XX_HLSQ_GS_CNTL
,
362 REG_A6XX_SP_GS_OBJ_START_LO
,
364 [MESA_SHADER_FRAGMENT
] = {
365 REG_A6XX_SP_FS_CTRL_REG0
,
366 REG_A6XX_SP_FS_CONFIG
,
367 REG_A6XX_HLSQ_FS_CNTL
,
368 REG_A6XX_SP_FS_OBJ_START_LO
,
370 [MESA_SHADER_COMPUTE
] = {
371 REG_A6XX_SP_CS_CTRL_REG0
,
372 REG_A6XX_SP_CS_CONFIG
,
373 REG_A6XX_HLSQ_CS_CNTL
,
374 REG_A6XX_SP_CS_OBJ_START_LO
,
377 const struct xs_config
*cfg
= &xs_config
[stage
];
380 /* shader stage disabled */
381 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_config
, 1);
384 tu_cs_emit_pkt4(cs
, cfg
->reg_hlsq_xs_ctrl
, 1);
389 bool is_fs
= xs
->type
== MESA_SHADER_FRAGMENT
;
390 enum a3xx_threadsize threadsize
= FOUR_QUADS
;
393 * the "threadsize" field may have nothing to do with threadsize,
394 * use a value that matches the blob until it is figured out
396 if (xs
->type
== MESA_SHADER_GEOMETRY
)
397 threadsize
= TWO_QUADS
;
399 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_ctrl
, 1);
401 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize
) |
402 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs
->info
.max_reg
+ 1) |
403 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs
->info
.max_half_reg
+ 1) |
404 COND(xs
->mergedregs
, A6XX_SP_VS_CTRL_REG0_MERGEDREGS
) |
405 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs
->branchstack
) |
406 COND(xs
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
) |
407 COND(xs
->need_fine_derivatives
, A6XX_SP_VS_CTRL_REG0_DIFF_FINE
) |
408 /* only fragment shader sets VARYING bit */
409 COND(xs
->total_in
&& is_fs
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
410 /* unknown bit, seems unnecessary */
411 COND(is_fs
, 0x1000000));
413 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_config
, 2);
414 tu_cs_emit(cs
, A6XX_SP_VS_CONFIG_ENABLED
|
415 COND(xs
->bindless_tex
, A6XX_SP_VS_CONFIG_BINDLESS_TEX
) |
416 COND(xs
->bindless_samp
, A6XX_SP_VS_CONFIG_BINDLESS_SAMP
) |
417 COND(xs
->bindless_ibo
, A6XX_SP_VS_CONFIG_BINDLESS_IBO
) |
418 COND(xs
->bindless_ubo
, A6XX_SP_VS_CONFIG_BINDLESS_UBO
) |
419 A6XX_SP_VS_CONFIG_NTEX(xs
->num_samp
) |
420 A6XX_SP_VS_CONFIG_NSAMP(xs
->num_samp
));
421 tu_cs_emit(cs
, xs
->instrlen
);
423 tu_cs_emit_pkt4(cs
, cfg
->reg_hlsq_xs_ctrl
, 1);
424 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs
->constlen
) |
425 A6XX_HLSQ_VS_CNTL_ENABLED
);
427 /* emit program binary
428 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
431 assert((binary_iova
& 0x7f) == 0);
433 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_vs_obj_start
, 2);
434 tu_cs_emit_qw(cs
, binary_iova
);
436 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(stage
), 3);
437 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
438 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
439 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
440 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage
)) |
441 CP_LOAD_STATE6_0_NUM_UNIT(xs
->instrlen
));
442 tu_cs_emit_qw(cs
, binary_iova
);
444 /* emit immediates */
446 const struct ir3_const_state
*const_state
= ir3_const_state(xs
);
447 uint32_t base
= const_state
->offsets
.immediate
;
448 int size
= const_state
->immediates_count
;
450 /* truncate size to avoid writing constants that shader
453 size
= MIN2(size
+ base
, xs
->constlen
) - base
;
458 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(stage
), 3 + size
* 4);
459 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
460 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
461 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
462 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage
)) |
463 CP_LOAD_STATE6_0_NUM_UNIT(size
));
464 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
465 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
467 for (unsigned i
= 0; i
< size
; i
++) {
468 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
469 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
470 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
471 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
476 tu6_emit_cs_config(struct tu_cs
*cs
, const struct tu_shader
*shader
,
477 const struct ir3_shader_variant
*v
,
478 uint32_t binary_iova
)
480 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(
484 tu6_emit_xs_config(cs
, MESA_SHADER_COMPUTE
, v
, binary_iova
);
486 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
487 tu_cs_emit(cs
, 0x41);
489 uint32_t local_invocation_id
=
490 ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
491 uint32_t work_group_id
=
492 ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
494 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
496 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
497 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
498 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
499 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
500 tu_cs_emit(cs
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
504 tu6_emit_vs_system_values(struct tu_cs
*cs
,
505 const struct ir3_shader_variant
*vs
,
506 const struct ir3_shader_variant
*hs
,
507 const struct ir3_shader_variant
*ds
,
508 const struct ir3_shader_variant
*gs
,
509 bool primid_passthru
)
511 const uint32_t vertexid_regid
=
512 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
513 const uint32_t instanceid_regid
=
514 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
515 const uint32_t tess_coord_x_regid
= hs
?
516 ir3_find_sysval_regid(ds
, SYSTEM_VALUE_TESS_COORD
) :
518 const uint32_t tess_coord_y_regid
= VALIDREG(tess_coord_x_regid
) ?
519 tess_coord_x_regid
+ 1 :
521 const uint32_t hs_patch_regid
= hs
?
522 ir3_find_sysval_regid(hs
, SYSTEM_VALUE_PRIMITIVE_ID
) :
524 const uint32_t ds_patch_regid
= hs
?
525 ir3_find_sysval_regid(ds
, SYSTEM_VALUE_PRIMITIVE_ID
) :
527 const uint32_t hs_invocation_regid
= hs
?
528 ir3_find_sysval_regid(hs
, SYSTEM_VALUE_TCS_HEADER_IR3
) :
530 const uint32_t primitiveid_regid
= gs
?
531 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
) :
533 const uint32_t gsheader_regid
= gs
?
534 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_GS_HEADER_IR3
) :
537 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
538 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
539 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
540 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid
) |
542 tu_cs_emit(cs
, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid
) |
543 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid
));
544 tu_cs_emit(cs
, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid
) |
545 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid
) |
546 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid
) |
548 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
549 tu_cs_emit(cs
, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid
) |
550 0xfc00); /* VFD_CONTROL_5 */
551 tu_cs_emit(cs
, COND(primid_passthru
, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU
)); /* VFD_CONTROL_6 */
554 /* Add any missing varyings needed for stream-out. Otherwise varyings not
555 * used by fragment shader will be stripped out.
558 tu6_link_streamout(struct ir3_shader_linkage
*l
,
559 const struct ir3_shader_variant
*v
)
561 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
564 * First, any stream-out varyings not already in linkage map (ie. also
565 * consumed by frag shader) need to be added:
567 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
568 const struct ir3_stream_output
*out
= &info
->output
[i
];
570 (1 << (out
->num_components
+ out
->start_component
)) - 1;
571 unsigned k
= out
->register_index
;
572 unsigned idx
, nextloc
= 0;
574 /* psize/pos need to be the last entries in linkage map, and will
575 * get added link_stream_out, so skip over them:
577 if (v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
||
578 v
->outputs
[k
].slot
== VARYING_SLOT_POS
)
581 for (idx
= 0; idx
< l
->cnt
; idx
++) {
582 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
584 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
587 /* add if not already in linkage map: */
589 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
591 /* expand component-mask if needed, ie streaming out all components
592 * but frag shader doesn't consume all components:
594 if (compmask
& ~l
->var
[idx
].compmask
) {
595 l
->var
[idx
].compmask
|= compmask
;
596 l
->max_loc
= MAX2(l
->max_loc
, l
->var
[idx
].loc
+
597 util_last_bit(l
->var
[idx
].compmask
));
603 tu6_setup_streamout(struct tu_cs
*cs
,
604 const struct ir3_shader_variant
*v
,
605 struct ir3_shader_linkage
*l
)
607 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
608 uint32_t prog
[IR3_MAX_SO_OUTPUTS
* 2] = {};
609 uint32_t ncomp
[IR3_MAX_SO_BUFFERS
] = {};
610 uint32_t prog_count
= align(l
->max_loc
, 2) / 2;
612 /* TODO: streamout state should be in a non-GMEM draw state */
615 if (info
->num_outputs
== 0) {
616 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
617 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
619 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
624 /* is there something to do with info->stride[i]? */
626 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
627 const struct ir3_stream_output
*out
= &info
->output
[i
];
628 unsigned k
= out
->register_index
;
631 /* Skip it, if there's an unused reg in the middle of outputs. */
632 if (v
->outputs
[k
].regid
== INVALID_REG
)
635 ncomp
[out
->output_buffer
] += out
->num_components
;
637 /* linkage map sorted by order frag shader wants things, so
638 * a bit less ideal here..
640 for (idx
= 0; idx
< l
->cnt
; idx
++)
641 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
644 debug_assert(idx
< l
->cnt
);
646 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
647 unsigned c
= j
+ out
->start_component
;
648 unsigned loc
= l
->var
[idx
].loc
+ c
;
649 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
652 prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
653 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
654 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
656 prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
657 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
658 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
663 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + 2 * prog_count
);
664 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
665 tu_cs_emit(cs
, A6XX_VPC_SO_BUF_CNTL_ENABLE
|
666 COND(ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
667 COND(ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
668 COND(ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
669 COND(ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
));
670 for (uint32_t i
= 0; i
< 4; i
++) {
671 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(i
));
672 tu_cs_emit(cs
, ncomp
[i
]);
674 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
675 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
676 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
677 for (uint32_t i
= 0; i
< prog_count
; i
++) {
678 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
679 tu_cs_emit(cs
, prog
[i
]);
684 tu6_emit_const(struct tu_cs
*cs
, uint32_t opcode
, uint32_t base
,
685 enum a6xx_state_block block
, uint32_t offset
,
686 uint32_t size
, uint32_t *dwords
) {
687 assert(size
% 4 == 0);
689 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
);
690 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
691 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
692 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
693 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
694 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 4));
696 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
697 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
698 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
700 tu_cs_emit_array(cs
, dwords
, size
);
704 tu6_emit_link_map(struct tu_cs
*cs
,
705 const struct ir3_shader_variant
*producer
,
706 const struct ir3_shader_variant
*consumer
,
707 enum a6xx_state_block sb
)
709 const struct ir3_const_state
*const_state
= ir3_const_state(consumer
);
710 uint32_t base
= const_state
->offsets
.primitive_map
;
711 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
712 num_loc
= ir3_link_geometry_stages(producer
, consumer
, patch_locs
);
713 int size
= DIV_ROUND_UP(num_loc
, 4);
715 size
= (MIN2(size
+ base
, consumer
->constlen
) - base
) * 4;
719 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, base
, sb
, 0, size
,
724 gl_primitive_to_tess(uint16_t primitive
) {
730 case GL_TRIANGLE_STRIP
:
738 tu6_emit_vpc(struct tu_cs
*cs
,
739 const struct ir3_shader_variant
*vs
,
740 const struct ir3_shader_variant
*hs
,
741 const struct ir3_shader_variant
*ds
,
742 const struct ir3_shader_variant
*gs
,
743 const struct ir3_shader_variant
*fs
,
744 uint32_t patch_control_points
,
747 /* note: doesn't compile as static because of the array regs.. */
748 const struct reg_config
{
749 uint16_t reg_sp_xs_out_reg
;
750 uint16_t reg_sp_xs_vpc_dst_reg
;
751 uint16_t reg_vpc_xs_pack
;
752 uint16_t reg_vpc_xs_clip_cntl
;
753 uint16_t reg_gras_xs_cl_cntl
;
754 uint16_t reg_pc_xs_out_cntl
;
755 uint16_t reg_sp_xs_primitive_cntl
;
756 uint16_t reg_vpc_xs_layer_cntl
;
757 uint16_t reg_gras_xs_layer_cntl
;
759 [MESA_SHADER_VERTEX
] = {
760 REG_A6XX_SP_VS_OUT_REG(0),
761 REG_A6XX_SP_VS_VPC_DST_REG(0),
762 REG_A6XX_VPC_VS_PACK
,
763 REG_A6XX_VPC_VS_CLIP_CNTL
,
764 REG_A6XX_GRAS_VS_CL_CNTL
,
765 REG_A6XX_PC_VS_OUT_CNTL
,
766 REG_A6XX_SP_VS_PRIMITIVE_CNTL
,
767 REG_A6XX_VPC_VS_LAYER_CNTL
,
768 REG_A6XX_GRAS_VS_LAYER_CNTL
770 [MESA_SHADER_TESS_EVAL
] = {
771 REG_A6XX_SP_DS_OUT_REG(0),
772 REG_A6XX_SP_DS_VPC_DST_REG(0),
773 REG_A6XX_VPC_DS_PACK
,
774 REG_A6XX_VPC_DS_CLIP_CNTL
,
775 REG_A6XX_GRAS_DS_CL_CNTL
,
776 REG_A6XX_PC_DS_OUT_CNTL
,
777 REG_A6XX_SP_DS_PRIMITIVE_CNTL
,
778 REG_A6XX_VPC_DS_LAYER_CNTL
,
779 REG_A6XX_GRAS_DS_LAYER_CNTL
781 [MESA_SHADER_GEOMETRY
] = {
782 REG_A6XX_SP_GS_OUT_REG(0),
783 REG_A6XX_SP_GS_VPC_DST_REG(0),
784 REG_A6XX_VPC_GS_PACK
,
785 REG_A6XX_VPC_GS_CLIP_CNTL
,
786 REG_A6XX_GRAS_GS_CL_CNTL
,
787 REG_A6XX_PC_GS_OUT_CNTL
,
788 REG_A6XX_SP_GS_PRIMITIVE_CNTL
,
789 REG_A6XX_VPC_GS_LAYER_CNTL
,
790 REG_A6XX_GRAS_GS_LAYER_CNTL
794 const struct ir3_shader_variant
*last_shader
;
803 const struct reg_config
*cfg
= ®_config
[last_shader
->type
];
805 struct ir3_shader_linkage linkage
= { .primid_loc
= 0xff };
807 ir3_link_shaders(&linkage
, last_shader
, fs
, true);
809 if (last_shader
->shader
->stream_output
.num_outputs
)
810 tu6_link_streamout(&linkage
, last_shader
);
812 /* We do this after linking shaders in order to know whether PrimID
813 * passthrough needs to be enabled.
815 bool primid_passthru
= linkage
.primid_loc
!= 0xff;
816 tu6_emit_vs_system_values(cs
, vs
, hs
, ds
, gs
, primid_passthru
);
818 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
819 tu_cs_emit(cs
, ~linkage
.varmask
[0]);
820 tu_cs_emit(cs
, ~linkage
.varmask
[1]);
821 tu_cs_emit(cs
, ~linkage
.varmask
[2]);
822 tu_cs_emit(cs
, ~linkage
.varmask
[3]);
824 /* a6xx finds position/pointsize at the end */
825 const uint32_t position_regid
=
826 ir3_find_output_regid(last_shader
, VARYING_SLOT_POS
);
827 const uint32_t pointsize_regid
=
828 ir3_find_output_regid(last_shader
, VARYING_SLOT_PSIZ
);
829 const uint32_t layer_regid
=
830 ir3_find_output_regid(last_shader
, VARYING_SLOT_LAYER
);
831 uint32_t primitive_regid
= gs
?
832 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
) : regid(63, 0);
833 uint32_t flags_regid
= gs
?
834 ir3_find_output_regid(gs
, VARYING_SLOT_GS_VERTEX_FLAGS_IR3
) : 0;
836 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff, layer_loc
= 0xff;
837 if (layer_regid
!= regid(63, 0)) {
838 layer_loc
= linkage
.max_loc
;
839 ir3_link_add(&linkage
, layer_regid
, 0x1, linkage
.max_loc
);
841 if (position_regid
!= regid(63, 0)) {
842 position_loc
= linkage
.max_loc
;
843 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
845 if (pointsize_regid
!= regid(63, 0)) {
846 pointsize_loc
= linkage
.max_loc
;
847 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
850 tu6_setup_streamout(cs
, last_shader
, &linkage
);
852 /* The GPU hangs on some models when there are no outputs (xs_pack::CNT),
853 * at least when a DS is the last stage, so add a dummy output to keep it
854 * happy if there aren't any. We do this late in order to avoid emitting
855 * any unused code and make sure that optimizations don't remove it.
857 if (linkage
.cnt
== 0)
858 ir3_link_add(&linkage
, 0, 0x1, linkage
.max_loc
);
860 /* map outputs of the last shader to VPC */
861 assert(linkage
.cnt
<= 32);
862 const uint32_t sp_out_count
= DIV_ROUND_UP(linkage
.cnt
, 2);
863 const uint32_t sp_vpc_dst_count
= DIV_ROUND_UP(linkage
.cnt
, 4);
865 uint32_t sp_vpc_dst
[8];
866 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
867 ((uint16_t *) sp_out
)[i
] =
868 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
869 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
870 ((uint8_t *) sp_vpc_dst
)[i
] =
871 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
874 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_out_reg
, sp_out_count
);
875 tu_cs_emit_array(cs
, sp_out
, sp_out_count
);
877 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_vpc_dst_reg
, sp_vpc_dst_count
);
878 tu_cs_emit_array(cs
, sp_vpc_dst
, sp_vpc_dst_count
);
880 tu_cs_emit_pkt4(cs
, cfg
->reg_vpc_xs_pack
, 1);
881 tu_cs_emit(cs
, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc
) |
882 A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc
) |
883 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
885 tu_cs_emit_pkt4(cs
, cfg
->reg_vpc_xs_clip_cntl
, 1);
886 tu_cs_emit(cs
, 0xffff00);
888 tu_cs_emit_pkt4(cs
, cfg
->reg_gras_xs_cl_cntl
, 1);
891 tu_cs_emit_pkt4(cs
, cfg
->reg_pc_xs_out_cntl
, 1);
892 tu_cs_emit(cs
, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage
.max_loc
) |
893 CONDREG(pointsize_regid
, A6XX_PC_VS_OUT_CNTL_PSIZE
) |
894 CONDREG(layer_regid
, A6XX_PC_VS_OUT_CNTL_LAYER
) |
895 CONDREG(primitive_regid
, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID
));
897 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_primitive_cntl
, 1);
898 tu_cs_emit(cs
, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage
.cnt
) |
899 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid
));
901 tu_cs_emit_pkt4(cs
, cfg
->reg_vpc_xs_layer_cntl
, 1);
902 tu_cs_emit(cs
, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc
) | 0xff00);
904 tu_cs_emit_pkt4(cs
, cfg
->reg_gras_xs_layer_cntl
, 1);
905 tu_cs_emit(cs
, CONDREG(layer_regid
, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER
));
907 tu_cs_emit_regs(cs
, A6XX_PC_PRIMID_PASSTHRU(primid_passthru
));
909 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
910 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
? fs
->total_in
: 0) |
911 COND(fs
&& fs
->total_in
, A6XX_VPC_CNTL_0_VARYING
) |
912 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage
.primid_loc
) |
913 A6XX_VPC_CNTL_0_UNKLOC(0xff));
916 shader_info
*hs_info
= &hs
->shader
->nir
->info
;
917 uint32_t unknown_a831
= vs
->output_size
;
919 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_TESS_NUM_VERTEX
, 1);
920 tu_cs_emit(cs
, hs_info
->tess
.tcs_vertices_out
);
922 /* Total attribute slots in HS incoming patch. */
923 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_HS_INPUT_SIZE
, 1);
924 tu_cs_emit(cs
, patch_control_points
* vs
->output_size
/ 4);
926 /* for A650 this value seems to be local memory size per wave */
927 if (vshs_workgroup
) {
928 const uint32_t wavesize
= 64;
929 /* note: if HS is really just the VS extended, then this
930 * should be by MAX2(patch_control_points, hs_info->tess.tcs_vertices_out)
931 * however that doesn't match the blob, and fails some dEQP tests.
933 uint32_t prims_per_wave
= wavesize
/ hs_info
->tess
.tcs_vertices_out
;
934 uint32_t total_size
= vs
->output_size
* patch_control_points
* prims_per_wave
;
935 unknown_a831
= DIV_ROUND_UP(total_size
, wavesize
);
938 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
939 tu_cs_emit(cs
, unknown_a831
);
941 /* In SPIR-V generated from GLSL, the tessellation primitive params are
942 * are specified in the tess eval shader, but in SPIR-V generated from
943 * HLSL, they are specified in the tess control shader. */
944 shader_info
*tess_info
=
945 ds
->shader
->nir
->info
.tess
.spacing
== TESS_SPACING_UNSPECIFIED
?
946 &hs
->shader
->nir
->info
: &ds
->shader
->nir
->info
;
947 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_TESS_CNTL
, 1);
949 if (tess_info
->tess
.point_mode
)
950 output
= TESS_POINTS
;
951 else if (tess_info
->tess
.primitive_mode
== GL_ISOLINES
)
953 else if (tess_info
->tess
.ccw
)
954 output
= TESS_CCW_TRIS
;
956 output
= TESS_CW_TRIS
;
958 enum a6xx_tess_spacing spacing
;
959 switch (tess_info
->tess
.spacing
) {
960 case TESS_SPACING_EQUAL
:
961 spacing
= TESS_EQUAL
;
963 case TESS_SPACING_FRACTIONAL_ODD
:
964 spacing
= TESS_FRACTIONAL_ODD
;
966 case TESS_SPACING_FRACTIONAL_EVEN
:
967 spacing
= TESS_FRACTIONAL_EVEN
;
969 case TESS_SPACING_UNSPECIFIED
:
971 unreachable("invalid tess spacing");
973 tu_cs_emit(cs
, A6XX_PC_TESS_CNTL_SPACING(spacing
) |
974 A6XX_PC_TESS_CNTL_OUTPUT(output
));
976 tu6_emit_link_map(cs
, vs
, hs
, SB6_HS_SHADER
);
977 tu6_emit_link_map(cs
, hs
, ds
, SB6_DS_SHADER
);
982 uint32_t vertices_out
, invocations
, output
, vec4_size
;
983 /* this detects the tu_clear_blit path, which doesn't set ->nir */
984 if (gs
->shader
->nir
) {
986 tu6_emit_link_map(cs
, ds
, gs
, SB6_GS_SHADER
);
988 tu6_emit_link_map(cs
, vs
, gs
, SB6_GS_SHADER
);
990 vertices_out
= gs
->shader
->nir
->info
.gs
.vertices_out
- 1;
991 output
= gl_primitive_to_tess(gs
->shader
->nir
->info
.gs
.output_primitive
);
992 invocations
= gs
->shader
->nir
->info
.gs
.invocations
- 1;
993 /* Size of per-primitive alloction in ldlw memory in vec4s. */
994 vec4_size
= gs
->shader
->nir
->info
.gs
.vertices_in
*
995 DIV_ROUND_UP(vs
->output_size
, 4);
998 output
= TESS_CW_TRIS
;
1003 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_5
, 1);
1005 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out
) |
1006 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output
) |
1007 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations
));
1009 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_3
, 1);
1012 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9100
, 1);
1013 tu_cs_emit(cs
, 0xff);
1015 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
1016 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size
));
1018 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 1);
1021 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_PRIM_SIZE
, 1);
1022 tu_cs_emit(cs
, vs
->output_size
);
1027 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
1029 uint8_t *interp_mode
,
1030 uint8_t *ps_repl_mode
)
1044 PS_REPL_ONE_MINUS_T
= 3,
1047 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
1049 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1050 * fourth component occupy three consecutive varying slots
1055 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
1056 if (compmask
& 0x1) {
1057 *ps_repl_mode
|= PS_REPL_S
<< shift
;
1060 if (compmask
& 0x2) {
1061 *ps_repl_mode
|= PS_REPL_T
<< shift
;
1064 if (compmask
& 0x4) {
1065 *interp_mode
|= INTERP_ZERO
<< shift
;
1068 if (compmask
& 0x8) {
1069 *interp_mode
|= INTERP_ONE
<< 6;
1072 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
1073 fs
->inputs
[index
].rasterflat
) {
1074 for (int i
= 0; i
< 4; i
++) {
1075 if (compmask
& (1 << i
)) {
1076 *interp_mode
|= INTERP_FLAT
<< shift
;
1086 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
1087 const struct ir3_shader_variant
*fs
)
1089 uint32_t interp_modes
[8] = { 0 };
1090 uint32_t ps_repl_modes
[8] = { 0 };
1094 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
1096 /* get the mode for input i */
1097 uint8_t interp_mode
;
1098 uint8_t ps_repl_mode
;
1100 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
1102 /* OR the mode into the array */
1103 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
1104 uint32_t n
= inloc
/ 32;
1105 uint32_t shift
= inloc
% 32;
1106 interp_modes
[n
] |= interp_mode
<< shift
;
1107 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
1108 if (shift
+ bits
> 32) {
1112 interp_modes
[n
] |= interp_mode
>> shift
;
1113 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
1118 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1119 tu_cs_emit_array(cs
, interp_modes
, 8);
1121 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1122 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
1126 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
1128 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
1129 uint32_t ij_regid
[IJ_COUNT
];
1130 uint32_t smask_in_regid
;
1132 bool sample_shading
= fs
->per_samp
| fs
->key
.sample_shading
;
1133 bool enable_varyings
= fs
->total_in
> 0;
1135 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
1136 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
1137 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
1138 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
1139 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
1140 for (unsigned i
= 0; i
< ARRAY_SIZE(ij_regid
); i
++)
1141 ij_regid
[i
] = ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
+ i
);
1143 if (VALIDREG(ij_regid
[IJ_LINEAR_SAMPLE
]))
1144 tu_finishme("linear sample varying");
1146 if (VALIDREG(ij_regid
[IJ_LINEAR_CENTROID
]))
1147 tu_finishme("linear centroid varying");
1149 if (fs
->num_sampler_prefetch
> 0) {
1150 assert(VALIDREG(ij_regid
[IJ_PERSP_PIXEL
]));
1151 /* also, it seems like ij_pix is *required* to be r0.x */
1152 assert(ij_regid
[IJ_PERSP_PIXEL
] == regid(0, 0));
1155 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
1156 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
1157 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1159 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1160 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1161 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
1162 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
1163 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
1164 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
1165 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
1166 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
1167 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
1170 if (fs
->num_sampler_prefetch
> 0) {
1171 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs
->num_sampler_prefetch
);
1172 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1173 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1175 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_bindless_id
) |
1176 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch
->tex_bindless_id
));
1180 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
1181 tu_cs_emit(cs
, 0x7);
1182 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
1183 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
1184 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
1185 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid
[IJ_PERSP_SIZE
]));
1186 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid
[IJ_PERSP_PIXEL
]) |
1187 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid
[IJ_LINEAR_PIXEL
]) |
1188 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid
[IJ_PERSP_CENTROID
]) |
1189 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid
[IJ_LINEAR_CENTROID
]));
1190 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
1191 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
1192 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid
[IJ_PERSP_SAMPLE
]) |
1193 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid
[IJ_LINEAR_SAMPLE
]));
1194 tu_cs_emit(cs
, 0xfc);
1196 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
1197 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
1199 bool need_size
= fs
->frag_face
|| fs
->fragcoord_compmask
!= 0;
1200 bool need_size_persamp
= false;
1201 if (VALIDREG(ij_regid
[IJ_PERSP_SIZE
])) {
1203 need_size_persamp
= true;
1207 if (VALIDREG(ij_regid
[IJ_LINEAR_PIXEL
]))
1210 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
1212 CONDREG(ij_regid
[IJ_PERSP_PIXEL
], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL
) |
1213 CONDREG(ij_regid
[IJ_PERSP_CENTROID
], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID
) |
1214 CONDREG(ij_regid
[IJ_PERSP_SAMPLE
], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE
) |
1215 COND(need_size
, A6XX_GRAS_CNTL_SIZE
) |
1216 COND(need_size_persamp
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
1217 COND(fs
->fragcoord_compmask
!= 0, A6XX_GRAS_CNTL_COORD_MASK(fs
->fragcoord_compmask
)));
1219 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
1221 CONDREG(ij_regid
[IJ_PERSP_PIXEL
], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL
) |
1222 CONDREG(ij_regid
[IJ_PERSP_CENTROID
], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID
) |
1223 CONDREG(ij_regid
[IJ_PERSP_SAMPLE
], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE
) |
1224 COND(need_size
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
1225 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
1226 COND(need_size_persamp
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
1227 COND(fs
->fragcoord_compmask
!= 0,
1228 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs
->fragcoord_compmask
)));
1230 /* these two bits (UNK4/UNK5) relate to fragcoord
1231 * without them, fragcoord is the same for all samples
1233 COND(sample_shading
, A6XX_RB_RENDER_CONTROL1_UNK4
) |
1234 COND(sample_shading
, A6XX_RB_RENDER_CONTROL1_UNK5
) |
1235 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
1236 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
1237 CONDREG(ij_regid
[IJ_PERSP_SIZE
], A6XX_RB_RENDER_CONTROL1_SIZE
) |
1238 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
1240 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
1241 tu_cs_emit(cs
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
1243 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
1244 tu_cs_emit(cs
, COND(sample_shading
, 0x6)); // XXX
1246 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
1247 tu_cs_emit(cs
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
1251 tu6_emit_fs_outputs(struct tu_cs
*cs
,
1252 const struct ir3_shader_variant
*fs
,
1253 uint32_t mrt_count
, bool dual_src_blend
,
1254 uint32_t render_components
,
1257 uint32_t smask_regid
, posz_regid
, stencilref_regid
;
1259 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
1260 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
1261 stencilref_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_STENCIL
);
1263 uint32_t fragdata_regid
[8];
1264 if (fs
->color0_mrt
) {
1265 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
1266 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1267 fragdata_regid
[i
] = fragdata_regid
[0];
1269 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1270 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
1273 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
1274 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
1275 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
1276 A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid
) |
1277 COND(dual_src_blend
, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE
));
1278 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1280 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1281 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
1282 // TODO we could have a mix of half and full precision outputs,
1283 // we really need to figure out half-precision from IR3_REG_HALF
1284 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
1285 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
1289 A6XX_SP_FS_RENDER_COMPONENTS(.dword
= render_components
));
1291 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
1292 tu_cs_emit(cs
, COND(fs
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
) |
1293 COND(fs
->writes_smask
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK
) |
1294 COND(fs
->writes_stencilref
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF
) |
1295 COND(dual_src_blend
, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE
));
1296 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1299 A6XX_RB_RENDER_COMPONENTS(.dword
= render_components
));
1301 enum a6xx_ztest_mode zmode
;
1303 if (fs
->no_earlyz
|| fs
->has_kill
|| fs
->writes_pos
|| fs
->writes_stencilref
|| is_s8_uint
) {
1304 zmode
= A6XX_LATE_Z
;
1306 zmode
= A6XX_EARLY_Z
;
1309 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
1310 tu_cs_emit(cs
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode
));
1312 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
1313 tu_cs_emit(cs
, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode
));
1317 tu6_emit_geom_tess_consts(struct tu_cs
*cs
,
1318 const struct ir3_shader_variant
*vs
,
1319 const struct ir3_shader_variant
*hs
,
1320 const struct ir3_shader_variant
*ds
,
1321 const struct ir3_shader_variant
*gs
,
1322 uint32_t cps_per_patch
)
1324 uint32_t num_vertices
=
1325 hs
? cps_per_patch
: gs
->shader
->nir
->info
.gs
.vertices_in
;
1327 uint32_t vs_params
[4] = {
1328 vs
->output_size
* num_vertices
* 4, /* vs primitive stride */
1329 vs
->output_size
* 4, /* vs vertex stride */
1333 uint32_t vs_base
= ir3_const_state(vs
)->offsets
.primitive_param
;
1334 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, vs_base
, SB6_VS_SHADER
, 0,
1335 ARRAY_SIZE(vs_params
), vs_params
);
1338 assert(ds
->type
!= MESA_SHADER_NONE
);
1339 uint32_t hs_params
[4] = {
1340 vs
->output_size
* num_vertices
* 4, /* hs primitive stride */
1341 vs
->output_size
* 4, /* hs vertex stride */
1346 uint32_t hs_base
= hs
->const_state
->offsets
.primitive_param
;
1347 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, hs_base
, SB6_HS_SHADER
, 0,
1348 ARRAY_SIZE(hs_params
), hs_params
);
1350 num_vertices
= gs
->shader
->nir
->info
.gs
.vertices_in
;
1352 uint32_t ds_params
[4] = {
1353 ds
->output_size
* num_vertices
* 4, /* ds primitive stride */
1354 ds
->output_size
* 4, /* ds vertex stride */
1355 hs
->output_size
, /* hs vertex stride (dwords) */
1356 hs
->shader
->nir
->info
.tess
.tcs_vertices_out
1359 uint32_t ds_base
= ds
->const_state
->offsets
.primitive_param
;
1360 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, ds_base
, SB6_DS_SHADER
, 0,
1361 ARRAY_SIZE(ds_params
), ds_params
);
1365 const struct ir3_shader_variant
*prev
= ds
? ds
: vs
;
1366 uint32_t gs_params
[4] = {
1367 prev
->output_size
* num_vertices
* 4, /* gs primitive stride */
1368 prev
->output_size
* 4, /* gs vertex stride */
1372 uint32_t gs_base
= gs
->const_state
->offsets
.primitive_param
;
1373 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, gs_base
, SB6_GS_SHADER
, 0,
1374 ARRAY_SIZE(gs_params
), gs_params
);
1379 tu6_emit_program(struct tu_cs
*cs
,
1380 struct tu_pipeline_builder
*builder
,
1383 const struct ir3_shader_variant
*vs
= builder
->variants
[MESA_SHADER_VERTEX
];
1384 const struct ir3_shader_variant
*bs
= builder
->binning_variant
;
1385 const struct ir3_shader_variant
*hs
= builder
->variants
[MESA_SHADER_TESS_CTRL
];
1386 const struct ir3_shader_variant
*ds
= builder
->variants
[MESA_SHADER_TESS_EVAL
];
1387 const struct ir3_shader_variant
*gs
= builder
->variants
[MESA_SHADER_GEOMETRY
];
1388 const struct ir3_shader_variant
*fs
= builder
->variants
[MESA_SHADER_FRAGMENT
];
1389 gl_shader_stage stage
= MESA_SHADER_VERTEX
;
1390 uint32_t cps_per_patch
= builder
->create_info
->pTessellationState
?
1391 builder
->create_info
->pTessellationState
->patchControlPoints
: 0;
1393 STATIC_ASSERT(MESA_SHADER_VERTEX
== 0);
1395 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(
1403 /* Don't use the binning pass variant when GS is present because we don't
1404 * support compiling correct binning pass variants with GS.
1406 if (binning_pass
&& !gs
) {
1408 tu6_emit_xs_config(cs
, stage
, bs
, builder
->binning_vs_iova
);
1412 for (; stage
< ARRAY_SIZE(builder
->shaders
); stage
++) {
1413 const struct ir3_shader_variant
*xs
= builder
->variants
[stage
];
1415 if (stage
== MESA_SHADER_FRAGMENT
&& binning_pass
)
1418 tu6_emit_xs_config(cs
, stage
, xs
, builder
->shader_iova
[stage
]);
1421 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
1424 tu6_emit_vpc(cs
, vs
, hs
, ds
, gs
, fs
, cps_per_patch
,
1425 builder
->device
->physical_device
->gpu_id
== 650);
1426 tu6_emit_vpc_varying_modes(cs
, fs
);
1429 tu6_emit_fs_inputs(cs
, fs
);
1430 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
,
1431 builder
->use_dual_src_blend
,
1432 builder
->render_components
,
1433 builder
->depth_attachment_format
== VK_FORMAT_S8_UINT
);
1435 /* TODO: check if these can be skipped if fs is disabled */
1436 struct ir3_shader_variant dummy_variant
= {};
1437 tu6_emit_fs_inputs(cs
, &dummy_variant
);
1438 tu6_emit_fs_outputs(cs
, &dummy_variant
, builder
->color_attachment_count
,
1439 builder
->use_dual_src_blend
,
1440 builder
->render_components
,
1441 builder
->depth_attachment_format
== VK_FORMAT_S8_UINT
);
1445 tu6_emit_geom_tess_consts(cs
, vs
, hs
, ds
, gs
, cps_per_patch
);
1450 tu6_emit_vertex_input(struct tu_cs
*cs
,
1451 const struct ir3_shader_variant
*vs
,
1452 const VkPipelineVertexInputStateCreateInfo
*info
,
1453 uint32_t *bindings_used
)
1455 uint32_t vfd_decode_idx
= 0;
1456 uint32_t binding_instanced
= 0; /* bitmask of instanced bindings */
1457 uint32_t step_rate
[MAX_VBS
];
1459 for (uint32_t i
= 0; i
< info
->vertexBindingDescriptionCount
; i
++) {
1460 const VkVertexInputBindingDescription
*binding
=
1461 &info
->pVertexBindingDescriptions
[i
];
1464 A6XX_VFD_FETCH_STRIDE(binding
->binding
, binding
->stride
));
1466 if (binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1467 binding_instanced
|= 1 << binding
->binding
;
1469 *bindings_used
|= 1 << binding
->binding
;
1470 step_rate
[binding
->binding
] = 1;
1473 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*div_state
=
1474 vk_find_struct_const(info
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1476 for (uint32_t i
= 0; i
< div_state
->vertexBindingDivisorCount
; i
++) {
1477 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1478 &div_state
->pVertexBindingDivisors
[i
];
1479 step_rate
[desc
->binding
] = desc
->divisor
;
1483 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1485 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
1486 const VkVertexInputAttributeDescription
*attr
=
1487 &info
->pVertexAttributeDescriptions
[i
];
1490 assert(*bindings_used
& BIT(attr
->binding
));
1492 for (input_idx
= 0; input_idx
< vs
->inputs_count
; input_idx
++) {
1493 if ((vs
->inputs
[input_idx
].slot
- VERT_ATTRIB_GENERIC0
) == attr
->location
)
1497 /* attribute not used, skip it */
1498 if (input_idx
== vs
->inputs_count
)
1501 const struct tu_native_format format
= tu6_format_vtx(attr
->format
);
1503 A6XX_VFD_DECODE_INSTR(vfd_decode_idx
,
1504 .idx
= attr
->binding
,
1505 .offset
= attr
->offset
,
1506 .instanced
= binding_instanced
& (1 << attr
->binding
),
1507 .format
= format
.fmt
,
1508 .swap
= format
.swap
,
1510 ._float
= !vk_format_is_int(attr
->format
)),
1511 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx
, step_rate
[attr
->binding
]));
1514 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx
,
1515 .writemask
= vs
->inputs
[input_idx
].compmask
,
1516 .regid
= vs
->inputs
[input_idx
].regid
));
1523 .fetch_cnt
= vfd_decode_idx
, /* decode_cnt for binning pass ? */
1524 .decode_cnt
= vfd_decode_idx
));
1528 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1532 scales
[0] = viewport
->width
/ 2.0f
;
1533 scales
[1] = viewport
->height
/ 2.0f
;
1534 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1535 offsets
[0] = viewport
->x
+ scales
[0];
1536 offsets
[1] = viewport
->y
+ scales
[1];
1537 offsets
[2] = viewport
->minDepth
;
1541 min
.x
= (int32_t) viewport
->x
;
1542 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1543 if (viewport
->height
>= 0.0f
) {
1544 min
.y
= (int32_t) viewport
->y
;
1545 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1547 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1548 max
.y
= (int32_t) ceilf(viewport
->y
);
1550 /* the spec allows viewport->height to be 0.0f */
1553 assert(min
.x
>= 0 && min
.x
< max
.x
);
1554 assert(min
.y
>= 0 && min
.y
< max
.y
);
1556 VkExtent2D guardband_adj
;
1557 guardband_adj
.width
= fd_calc_guardband(offsets
[0], scales
[0], false);
1558 guardband_adj
.height
= fd_calc_guardband(offsets
[1], scales
[1], false);
1561 A6XX_GRAS_CL_VPORT_XOFFSET(0, offsets
[0]),
1562 A6XX_GRAS_CL_VPORT_XSCALE(0, scales
[0]),
1563 A6XX_GRAS_CL_VPORT_YOFFSET(0, offsets
[1]),
1564 A6XX_GRAS_CL_VPORT_YSCALE(0, scales
[1]),
1565 A6XX_GRAS_CL_VPORT_ZOFFSET(0, offsets
[2]),
1566 A6XX_GRAS_CL_VPORT_ZSCALE(0, scales
[2]));
1568 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(0), 2);
1569 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(min
.x
) |
1570 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(min
.y
));
1571 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(max
.x
- 1) |
1572 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(max
.y
- 1));
1574 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1576 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1577 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1579 float z_clamp_min
= MIN2(viewport
->minDepth
, viewport
->maxDepth
);
1580 float z_clamp_max
= MAX2(viewport
->minDepth
, viewport
->maxDepth
);
1583 A6XX_GRAS_CL_Z_CLAMP_MIN(0, z_clamp_min
),
1584 A6XX_GRAS_CL_Z_CLAMP_MAX(0, z_clamp_max
));
1587 A6XX_RB_Z_CLAMP_MIN(z_clamp_min
),
1588 A6XX_RB_Z_CLAMP_MAX(z_clamp_max
));
1592 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1594 VkOffset2D min
= scissor
->offset
;
1596 scissor
->offset
.x
+ scissor
->extent
.width
,
1597 scissor
->offset
.y
+ scissor
->extent
.height
,
1600 /* special case for empty scissor with max == 0 to avoid overflow */
1606 /* avoid overflow with large scissor
1607 * note the max will be limited to min - 1, so that empty scissor works
1609 uint32_t scissor_max
= BITFIELD_MASK(15);
1610 min
.x
= MIN2(scissor_max
, min
.x
);
1611 min
.y
= MIN2(scissor_max
, min
.y
);
1612 max
.x
= MIN2(scissor_max
, max
.x
);
1613 max
.y
= MIN2(scissor_max
, max
.y
);
1616 A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0, .x
= min
.x
, .y
= min
.y
),
1617 A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0, .x
= max
.x
- 1, .y
= max
.y
- 1));
1621 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
)
1624 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 1);
1627 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 1);
1630 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 1);
1635 assert(samp_loc
->sampleLocationsPerPixel
== samp_loc
->sampleLocationsCount
);
1636 assert(samp_loc
->sampleLocationGridSize
.width
== 1);
1637 assert(samp_loc
->sampleLocationGridSize
.height
== 1);
1639 uint32_t sample_config
=
1640 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE
;
1641 uint32_t sample_locations
= 0;
1642 for (uint32_t i
= 0; i
< samp_loc
->sampleLocationsCount
; i
++) {
1644 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc
->pSampleLocations
[i
].x
) |
1645 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc
->pSampleLocations
[i
].y
)) << i
*8;
1648 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 2);
1649 tu_cs_emit(cs
, sample_config
);
1650 tu_cs_emit(cs
, sample_locations
);
1652 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 2);
1653 tu_cs_emit(cs
, sample_config
);
1654 tu_cs_emit(cs
, sample_locations
);
1656 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 2);
1657 tu_cs_emit(cs
, sample_config
);
1658 tu_cs_emit(cs
, sample_locations
);
1662 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1663 VkSampleCountFlagBits samples
)
1665 uint32_t gras_su_cntl
= 0;
1667 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1668 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1669 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1670 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1672 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1673 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1675 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1677 if (rast_info
->depthBiasEnable
)
1678 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1680 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1681 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1683 return gras_su_cntl
;
1687 tu6_emit_depth_bias(struct tu_cs
*cs
,
1688 float constant_factor
,
1692 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1693 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
).value
);
1694 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
).value
);
1695 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
).value
);
1699 tu6_emit_depth_control(struct tu_cs
*cs
,
1700 const VkPipelineDepthStencilStateCreateInfo
*ds_info
,
1701 const VkPipelineRasterizationStateCreateInfo
*rast_info
)
1703 uint32_t rb_depth_cntl
= 0;
1704 if (ds_info
->depthTestEnable
) {
1706 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1707 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1708 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
; /* TODO: don't set for ALWAYS/NEVER */
1710 if (rast_info
->depthClampEnable
)
1711 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE
;
1713 if (ds_info
->depthWriteEnable
)
1714 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1717 if (ds_info
->depthBoundsTestEnable
)
1718 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE
| A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1720 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1721 tu_cs_emit(cs
, rb_depth_cntl
);
1725 tu6_emit_stencil_control(struct tu_cs
*cs
,
1726 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1728 uint32_t rb_stencil_control
= 0;
1729 if (ds_info
->stencilTestEnable
) {
1730 const VkStencilOpState
*front
= &ds_info
->front
;
1731 const VkStencilOpState
*back
= &ds_info
->back
;
1732 rb_stencil_control
|=
1733 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1734 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1735 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1736 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1737 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1738 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1739 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1740 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1741 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1742 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1743 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1746 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1747 tu_cs_emit(cs
, rb_stencil_control
);
1751 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1754 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1755 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1756 has_alpha
? att
->srcColorBlendFactor
1757 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1758 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1759 has_alpha
? att
->dstColorBlendFactor
1760 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1761 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1762 const enum adreno_rb_blend_factor src_alpha_factor
=
1763 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1764 const enum adreno_rb_blend_factor dst_alpha_factor
=
1765 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1767 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1768 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1769 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1770 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1771 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1772 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1776 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1777 uint32_t rb_mrt_control_rop
,
1781 uint32_t rb_mrt_control
=
1782 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1784 /* ignore blending and logic op for integer attachments */
1786 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1787 return rb_mrt_control
;
1790 rb_mrt_control
|= rb_mrt_control_rop
;
1792 if (att
->blendEnable
) {
1793 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1796 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1799 return rb_mrt_control
;
1803 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1804 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1805 const VkFormat attachment_formats
[MAX_RTS
],
1806 uint32_t *blend_enable_mask
)
1808 *blend_enable_mask
= 0;
1810 bool rop_reads_dst
= false;
1811 uint32_t rb_mrt_control_rop
= 0;
1812 if (blend_info
->logicOpEnable
) {
1813 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1814 rb_mrt_control_rop
=
1815 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1816 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1819 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
1820 const VkPipelineColorBlendAttachmentState
*att
=
1821 &blend_info
->pAttachments
[i
];
1822 const VkFormat format
= attachment_formats
[i
];
1824 uint32_t rb_mrt_control
= 0;
1825 uint32_t rb_mrt_blend_control
= 0;
1826 if (format
!= VK_FORMAT_UNDEFINED
) {
1827 const bool is_int
= vk_format_is_int(format
);
1828 const bool has_alpha
= vk_format_has_alpha(format
);
1831 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
1832 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
1834 if (att
->blendEnable
|| rop_reads_dst
)
1835 *blend_enable_mask
|= 1 << i
;
1838 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1839 tu_cs_emit(cs
, rb_mrt_control
);
1840 tu_cs_emit(cs
, rb_mrt_blend_control
);
1845 tu6_emit_blend_control(struct tu_cs
*cs
,
1846 uint32_t blend_enable_mask
,
1847 bool dual_src_blend
,
1848 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
1850 const uint32_t sample_mask
=
1851 msaa_info
->pSampleMask
? (*msaa_info
->pSampleMask
& 0xffff)
1852 : ((1 << msaa_info
->rasterizationSamples
) - 1);
1855 A6XX_SP_BLEND_CNTL(.enabled
= blend_enable_mask
,
1856 .dual_color_in_enable
= dual_src_blend
,
1857 .alpha_to_coverage
= msaa_info
->alphaToCoverageEnable
,
1860 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1862 A6XX_RB_BLEND_CNTL(.enable_blend
= blend_enable_mask
,
1863 .independent_blend
= true,
1864 .sample_mask
= sample_mask
,
1865 .dual_color_in_enable
= dual_src_blend
,
1866 .alpha_to_coverage
= msaa_info
->alphaToCoverageEnable
,
1867 .alpha_to_one
= msaa_info
->alphaToOneEnable
));
1871 tu_pipeline_allocate_cs(struct tu_device
*dev
,
1872 struct tu_pipeline
*pipeline
,
1873 struct tu_pipeline_builder
*builder
,
1874 struct ir3_shader_variant
*compute
)
1876 uint32_t size
= 2048 + tu6_load_state_size(pipeline
, compute
);
1878 /* graphics case: */
1880 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1881 if (builder
->variants
[i
])
1882 size
+= builder
->variants
[i
]->info
.sizedwords
;
1885 size
+= builder
->binning_variant
->info
.sizedwords
;
1887 size
+= compute
->info
.sizedwords
;
1890 tu_cs_init(&pipeline
->cs
, dev
, TU_CS_MODE_SUB_STREAM
, size
);
1892 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1893 * that LOAD_STATE can potentially take up a large amount of space so we
1894 * calculate its size explicitly.
1896 return tu_cs_reserve_space(&pipeline
->cs
, size
);
1900 tu_pipeline_shader_key_init(struct ir3_shader_key
*key
,
1901 const VkGraphicsPipelineCreateInfo
*pipeline_info
)
1903 for (uint32_t i
= 0; i
< pipeline_info
->stageCount
; i
++) {
1904 if (pipeline_info
->pStages
[i
].stage
== VK_SHADER_STAGE_GEOMETRY_BIT
) {
1910 if (pipeline_info
->pRasterizationState
->rasterizerDiscardEnable
)
1913 const VkPipelineMultisampleStateCreateInfo
*msaa_info
= pipeline_info
->pMultisampleState
;
1914 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
1915 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1916 if (msaa_info
->rasterizationSamples
> 1 ||
1917 /* also set msaa key when sample location is not the default
1918 * since this affects varying interpolation */
1919 (sample_locations
&& sample_locations
->sampleLocationsEnable
)) {
1923 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1924 if (msaa_info
->sampleShadingEnable
)
1925 key
->sample_shading
= true;
1927 /* We set this after we compile to NIR because we need the prim mode */
1928 key
->tessellation
= IR3_TESS_NONE
;
1932 tu6_get_tessmode(struct tu_shader
* shader
)
1934 uint32_t primitive_mode
= shader
->ir3_shader
->nir
->info
.tess
.primitive_mode
;
1935 switch (primitive_mode
) {
1937 return IR3_TESS_ISOLINES
;
1939 return IR3_TESS_TRIANGLES
;
1941 return IR3_TESS_QUADS
;
1943 return IR3_TESS_NONE
;
1945 unreachable("bad tessmode");
1950 tu_upload_variant(struct tu_pipeline
*pipeline
,
1951 const struct ir3_shader_variant
*variant
)
1953 struct tu_cs_memory memory
;
1958 /* this expects to get enough alignment because shaders are allocated first
1959 * and sizedwords is always aligned correctly
1960 * note: an assert in tu6_emit_xs_config validates the alignment
1962 tu_cs_alloc(&pipeline
->cs
, variant
->info
.sizedwords
, 1, &memory
);
1964 memcpy(memory
.map
, variant
->bin
, sizeof(uint32_t) * variant
->info
.sizedwords
);
1969 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
,
1970 struct tu_pipeline
*pipeline
)
1972 const struct ir3_compiler
*compiler
= builder
->device
->compiler
;
1973 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
1976 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1977 gl_shader_stage stage
=
1978 vk_to_mesa_shader_stage(builder
->create_info
->pStages
[i
].stage
);
1979 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
1982 struct ir3_shader_key key
= {};
1983 tu_pipeline_shader_key_init(&key
, builder
->create_info
);
1985 for (gl_shader_stage stage
= MESA_SHADER_VERTEX
;
1986 stage
< MESA_SHADER_STAGES
; stage
++) {
1987 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
1988 if (!stage_info
&& stage
!= MESA_SHADER_FRAGMENT
)
1991 struct tu_shader
*shader
=
1992 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->layout
,
1995 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1997 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
1998 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
1999 * the mode is specified in the tessellation control shader. */
2000 if ((stage
== MESA_SHADER_TESS_EVAL
|| stage
== MESA_SHADER_TESS_CTRL
) &&
2001 key
.tessellation
== IR3_TESS_NONE
) {
2002 key
.tessellation
= tu6_get_tessmode(shader
);
2005 builder
->shaders
[stage
] = shader
;
2008 struct tu_shader
*gs
= builder
->shaders
[MESA_SHADER_GEOMETRY
];
2010 !gs
|| !(gs
->ir3_shader
->nir
->info
.outputs_written
& VARYING_SLOT_LAYER
);
2012 pipeline
->tess
.patch_type
= key
.tessellation
;
2014 for (gl_shader_stage stage
= MESA_SHADER_VERTEX
;
2015 stage
< MESA_SHADER_STAGES
; stage
++) {
2016 if (!builder
->shaders
[stage
])
2020 builder
->variants
[stage
] =
2021 ir3_shader_get_variant(builder
->shaders
[stage
]->ir3_shader
,
2022 &key
, false, &created
);
2023 if (!builder
->variants
[stage
])
2024 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2027 uint32_t safe_constlens
= ir3_trim_constlen(builder
->variants
, compiler
);
2029 key
.safe_constlen
= true;
2031 for (gl_shader_stage stage
= MESA_SHADER_VERTEX
;
2032 stage
< MESA_SHADER_STAGES
; stage
++) {
2033 if (!builder
->shaders
[stage
])
2036 if (safe_constlens
& (1 << stage
)) {
2038 builder
->variants
[stage
] =
2039 ir3_shader_get_variant(builder
->shaders
[stage
]->ir3_shader
,
2040 &key
, false, &created
);
2041 if (!builder
->variants
[stage
])
2042 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2046 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
2047 struct ir3_shader_variant
*variant
;
2049 if (vs
->ir3_shader
->stream_output
.num_outputs
||
2050 !ir3_has_binning_vs(&key
)) {
2051 variant
= builder
->variants
[MESA_SHADER_VERTEX
];
2054 key
.safe_constlen
= !!(safe_constlens
& (1 << MESA_SHADER_VERTEX
));
2055 variant
= ir3_shader_get_variant(vs
->ir3_shader
, &key
,
2058 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2061 builder
->binning_variant
= variant
;
2067 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
2068 struct tu_pipeline
*pipeline
)
2070 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
2071 builder
->create_info
->pDynamicState
;
2076 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
2077 VkDynamicState state
= dynamic_info
->pDynamicStates
[i
];
2079 case VK_DYNAMIC_STATE_VIEWPORT
... VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2080 pipeline
->dynamic_state_mask
|= BIT(state
);
2082 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
2083 pipeline
->dynamic_state_mask
|= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
);
2086 assert(!"unsupported dynamic state");
2093 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage
*link
,
2094 struct tu_shader
*shader
,
2095 struct ir3_shader_variant
*v
)
2097 link
->const_state
= *ir3_const_state(v
);
2098 link
->constlen
= v
->constlen
;
2099 link
->push_consts
= shader
->push_consts
;
2103 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
2104 struct tu_pipeline
*pipeline
)
2106 struct tu_cs prog_cs
;
2107 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2108 tu6_emit_program(&prog_cs
, builder
, false);
2109 pipeline
->program
.state
= tu_cs_end_draw_state(&pipeline
->cs
, &prog_cs
);
2111 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2112 tu6_emit_program(&prog_cs
, builder
, true);
2113 pipeline
->program
.binning_state
= tu_cs_end_draw_state(&pipeline
->cs
, &prog_cs
);
2115 VkShaderStageFlags stages
= 0;
2116 for (unsigned i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
2117 stages
|= builder
->create_info
->pStages
[i
].stage
;
2119 pipeline
->active_stages
= stages
;
2121 uint32_t desc_sets
= 0;
2122 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2123 if (!builder
->shaders
[i
])
2126 tu_pipeline_set_linkage(&pipeline
->program
.link
[i
],
2127 builder
->shaders
[i
],
2128 builder
->variants
[i
]);
2129 desc_sets
|= builder
->shaders
[i
]->active_desc_sets
;
2131 pipeline
->active_desc_sets
= desc_sets
;
2135 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
2136 struct tu_pipeline
*pipeline
)
2138 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
2139 builder
->create_info
->pVertexInputState
;
2140 const struct ir3_shader_variant
*vs
= builder
->variants
[MESA_SHADER_VERTEX
];
2141 const struct ir3_shader_variant
*bs
= builder
->binning_variant
;
2144 tu_cs_begin_sub_stream(&pipeline
->cs
,
2145 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2146 tu6_emit_vertex_input(&vi_cs
, vs
, vi_info
,
2147 &pipeline
->vi
.bindings_used
);
2148 pipeline
->vi
.state
= tu_cs_end_draw_state(&pipeline
->cs
, &vi_cs
);
2151 tu_cs_begin_sub_stream(&pipeline
->cs
,
2152 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2153 tu6_emit_vertex_input(
2154 &vi_cs
, bs
, vi_info
, &pipeline
->vi
.bindings_used
);
2155 pipeline
->vi
.binning_state
=
2156 tu_cs_end_draw_state(&pipeline
->cs
, &vi_cs
);
2161 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
2162 struct tu_pipeline
*pipeline
)
2164 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
2165 builder
->create_info
->pInputAssemblyState
;
2167 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
2168 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
2172 tu_pipeline_static_state(struct tu_pipeline
*pipeline
, struct tu_cs
*cs
,
2173 uint32_t id
, uint32_t size
)
2175 assert(id
< ARRAY_SIZE(pipeline
->dynamic_state
));
2177 if (pipeline
->dynamic_state_mask
& BIT(id
))
2180 pipeline
->dynamic_state
[id
] = tu_cs_draw_state(&pipeline
->cs
, cs
, size
);
2185 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder
*builder
,
2186 struct tu_pipeline
*pipeline
)
2188 const VkPipelineTessellationStateCreateInfo
*tess_info
=
2189 builder
->create_info
->pTessellationState
;
2194 assert(pipeline
->ia
.primtype
== DI_PT_PATCHES0
);
2195 assert(tess_info
->patchControlPoints
<= 32);
2196 pipeline
->ia
.primtype
+= tess_info
->patchControlPoints
;
2197 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_info
=
2198 vk_find_struct_const(tess_info
->pNext
, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2199 pipeline
->tess
.upper_left_domain_origin
= !domain_info
||
2200 domain_info
->domainOrigin
== VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
;
2201 const struct ir3_shader_variant
*hs
= builder
->variants
[MESA_SHADER_TESS_CTRL
];
2202 const struct ir3_shader_variant
*ds
= builder
->variants
[MESA_SHADER_TESS_EVAL
];
2203 pipeline
->tess
.param_stride
= hs
->output_size
* 4;
2204 pipeline
->tess
.hs_bo_regid
= hs
->const_state
->offsets
.primitive_param
+ 1;
2205 pipeline
->tess
.ds_bo_regid
= ds
->const_state
->offsets
.primitive_param
+ 1;
2209 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
2210 struct tu_pipeline
*pipeline
)
2214 * pViewportState is a pointer to an instance of the
2215 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2216 * pipeline has rasterization disabled."
2218 * We leave the relevant registers stale in that case.
2220 if (builder
->rasterizer_discard
)
2223 const VkPipelineViewportStateCreateInfo
*vp_info
=
2224 builder
->create_info
->pViewportState
;
2228 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_VIEWPORT
, 18))
2229 tu6_emit_viewport(&cs
, vp_info
->pViewports
);
2231 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_SCISSOR
, 3))
2232 tu6_emit_scissor(&cs
, vp_info
->pScissors
);
2236 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
2237 struct tu_pipeline
*pipeline
)
2239 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
2240 builder
->create_info
->pRasterizationState
;
2242 enum a6xx_polygon_mode mode
= tu6_polygon_mode(rast_info
->polygonMode
);
2244 bool depth_clip_disable
= rast_info
->depthClampEnable
;
2246 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
2247 vk_find_struct_const(rast_info
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
2248 if (depth_clip_state
)
2249 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
2252 pipeline
->rast_state
= tu_cs_draw_state(&pipeline
->cs
, &cs
, 9);
2254 tu_cs_emit_regs(&cs
,
2256 .znear_clip_disable
= depth_clip_disable
,
2257 .zfar_clip_disable
= depth_clip_disable
,
2258 /* TODO should this be depth_clip_disable instead? */
2259 .unk5
= rast_info
->depthClampEnable
,
2260 .zero_gb_scale_z
= 1,
2261 .vp_clip_code_ignore
= 1));
2263 tu_cs_emit_regs(&cs
,
2264 A6XX_VPC_POLYGON_MODE(mode
));
2266 tu_cs_emit_regs(&cs
,
2267 A6XX_PC_POLYGON_MODE(mode
));
2269 /* move to hw ctx init? */
2270 tu_cs_emit_regs(&cs
,
2271 A6XX_GRAS_SU_POINT_MINMAX(.min
= 1.0f
/ 16.0f
, .max
= 4092.0f
),
2272 A6XX_GRAS_SU_POINT_SIZE(1.0f
));
2274 pipeline
->gras_su_cntl
=
2275 tu6_gras_su_cntl(rast_info
, builder
->samples
);
2277 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2)) {
2278 pipeline
->gras_su_cntl
|=
2279 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info
->lineWidth
/ 2.0f
);
2280 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= pipeline
->gras_su_cntl
));
2283 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4)) {
2284 tu6_emit_depth_bias(&cs
, rast_info
->depthBiasConstantFactor
,
2285 rast_info
->depthBiasClamp
,
2286 rast_info
->depthBiasSlopeFactor
);
2292 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
2293 struct tu_pipeline
*pipeline
)
2297 * pDepthStencilState is a pointer to an instance of the
2298 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2299 * the pipeline has rasterization disabled or if the subpass of the
2300 * render pass the pipeline is created against does not use a
2301 * depth/stencil attachment.
2303 * Disable both depth and stencil tests if there is no ds attachment,
2304 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2305 * only the separate stencil attachment
2307 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
2308 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
2309 builder
->depth_attachment_format
!= VK_FORMAT_UNDEFINED
2310 ? builder
->create_info
->pDepthStencilState
2312 const VkPipelineDepthStencilStateCreateInfo
*ds_info_depth
=
2313 builder
->depth_attachment_format
!= VK_FORMAT_S8_UINT
2314 ? ds_info
: &dummy_ds_info
;
2317 pipeline
->ds_state
= tu_cs_draw_state(&pipeline
->cs
, &cs
, 6);
2319 /* move to hw ctx init? */
2320 tu_cs_emit_regs(&cs
, A6XX_RB_ALPHA_CONTROL());
2321 tu6_emit_depth_control(&cs
, ds_info_depth
,
2322 builder
->create_info
->pRasterizationState
);
2323 tu6_emit_stencil_control(&cs
, ds_info
);
2325 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_DEPTH_BOUNDS
, 3)) {
2326 tu_cs_emit_regs(&cs
,
2327 A6XX_RB_Z_BOUNDS_MIN(ds_info
->minDepthBounds
),
2328 A6XX_RB_Z_BOUNDS_MAX(ds_info
->maxDepthBounds
));
2331 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2)) {
2332 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.mask
= ds_info
->front
.compareMask
& 0xff,
2333 .bfmask
= ds_info
->back
.compareMask
& 0xff));
2336 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2)) {
2337 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.wrmask
= ds_info
->front
.writeMask
& 0xff,
2338 .bfwrmask
= ds_info
->back
.writeMask
& 0xff));
2341 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2)) {
2342 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.ref
= ds_info
->front
.reference
& 0xff,
2343 .bfref
= ds_info
->back
.reference
& 0xff));
2348 tu_pipeline_builder_parse_multisample_and_color_blend(
2349 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
2353 * pMultisampleState is a pointer to an instance of the
2354 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2355 * has rasterization disabled.
2359 * pColorBlendState is a pointer to an instance of the
2360 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2361 * pipeline has rasterization disabled or if the subpass of the render
2362 * pass the pipeline is created against does not use any color
2365 * We leave the relevant registers stale when rasterization is disabled.
2367 if (builder
->rasterizer_discard
)
2370 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
2371 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
2372 builder
->create_info
->pMultisampleState
;
2373 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
2374 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
2375 : &dummy_blend_info
;
2378 pipeline
->blend_state
=
2379 tu_cs_draw_state(&pipeline
->cs
, &cs
, blend_info
->attachmentCount
* 3 + 4);
2381 uint32_t blend_enable_mask
;
2382 tu6_emit_rb_mrt_controls(&cs
, blend_info
,
2383 builder
->color_attachment_formats
,
2384 &blend_enable_mask
);
2386 tu6_emit_blend_control(&cs
, blend_enable_mask
,
2387 builder
->use_dual_src_blend
, msaa_info
);
2389 assert(cs
.cur
== cs
.end
); /* validate draw state size */
2391 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5)) {
2392 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2393 tu_cs_emit_array(&cs
, (const uint32_t *) blend_info
->blendConstants
, 4);
2396 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
2397 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
2398 const VkSampleLocationsInfoEXT
*samp_loc
= NULL
;
2400 if (sample_locations
&& sample_locations
->sampleLocationsEnable
)
2401 samp_loc
= &sample_locations
->sampleLocationsInfo
;
2403 if (tu_pipeline_static_state(pipeline
, &cs
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
,
2404 samp_loc
? 9 : 6)) {
2405 tu6_emit_sample_locations(&cs
, samp_loc
);
2410 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
2411 struct tu_device
*dev
,
2412 const VkAllocationCallbacks
*alloc
)
2414 tu_cs_finish(&pipeline
->cs
);
2418 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
2419 struct tu_pipeline
**pipeline
)
2423 *pipeline
= vk_object_zalloc(&builder
->device
->vk
, builder
->alloc
,
2424 sizeof(**pipeline
), VK_OBJECT_TYPE_PIPELINE
);
2426 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2428 (*pipeline
)->layout
= builder
->layout
;
2430 /* compile and upload shaders */
2431 result
= tu_pipeline_builder_compile_shaders(builder
, *pipeline
);
2432 if (result
!= VK_SUCCESS
) {
2433 vk_object_free(&builder
->device
->vk
, builder
->alloc
, *pipeline
);
2437 result
= tu_pipeline_allocate_cs(builder
->device
, *pipeline
, builder
, NULL
);
2438 if (result
!= VK_SUCCESS
) {
2439 vk_object_free(&builder
->device
->vk
, builder
->alloc
, *pipeline
);
2443 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
2444 builder
->shader_iova
[i
] = tu_upload_variant(*pipeline
, builder
->variants
[i
]);
2446 builder
->binning_vs_iova
=
2447 tu_upload_variant(*pipeline
, builder
->binning_variant
);
2449 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
2450 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
2451 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
2452 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
2453 tu_pipeline_builder_parse_tessellation(builder
, *pipeline
);
2454 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
2455 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
2456 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
2457 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
2458 tu6_emit_load_state(*pipeline
, false);
2460 /* we should have reserved enough space upfront such that the CS never
2463 assert((*pipeline
)->cs
.bo_count
== 1);
2469 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
2471 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2472 if (!builder
->shaders
[i
])
2474 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
2479 tu_pipeline_builder_init_graphics(
2480 struct tu_pipeline_builder
*builder
,
2481 struct tu_device
*dev
,
2482 struct tu_pipeline_cache
*cache
,
2483 const VkGraphicsPipelineCreateInfo
*create_info
,
2484 const VkAllocationCallbacks
*alloc
)
2486 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, create_info
->layout
);
2488 *builder
= (struct tu_pipeline_builder
) {
2491 .create_info
= create_info
,
2496 builder
->rasterizer_discard
=
2497 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
2499 if (builder
->rasterizer_discard
) {
2500 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
2502 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
2504 const struct tu_render_pass
*pass
=
2505 tu_render_pass_from_handle(create_info
->renderPass
);
2506 const struct tu_subpass
*subpass
=
2507 &pass
->subpasses
[create_info
->subpass
];
2509 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
2510 builder
->depth_attachment_format
= (a
!= VK_ATTACHMENT_UNUSED
) ?
2511 pass
->attachments
[a
].format
: VK_FORMAT_UNDEFINED
;
2513 assert(subpass
->color_count
== 0 ||
2514 !create_info
->pColorBlendState
||
2515 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
2516 builder
->color_attachment_count
= subpass
->color_count
;
2517 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
2518 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
2519 if (a
== VK_ATTACHMENT_UNUSED
)
2522 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
2523 builder
->use_color_attachments
= true;
2524 builder
->render_components
|= 0xf << (i
* 4);
2527 if (tu_blend_state_is_dual_src(create_info
->pColorBlendState
)) {
2528 builder
->color_attachment_count
++;
2529 builder
->use_dual_src_blend
= true;
2530 /* dual source blending has an extra fs output in the 2nd slot */
2531 if (subpass
->color_attachments
[0].attachment
!= VK_ATTACHMENT_UNUSED
)
2532 builder
->render_components
|= 0xf << 4;
2538 tu_graphics_pipeline_create(VkDevice device
,
2539 VkPipelineCache pipelineCache
,
2540 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2541 const VkAllocationCallbacks
*pAllocator
,
2542 VkPipeline
*pPipeline
)
2544 TU_FROM_HANDLE(tu_device
, dev
, device
);
2545 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
2547 struct tu_pipeline_builder builder
;
2548 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
2549 pCreateInfo
, pAllocator
);
2551 struct tu_pipeline
*pipeline
= NULL
;
2552 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
2553 tu_pipeline_builder_finish(&builder
);
2555 if (result
== VK_SUCCESS
)
2556 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2558 *pPipeline
= VK_NULL_HANDLE
;
2564 tu_CreateGraphicsPipelines(VkDevice device
,
2565 VkPipelineCache pipelineCache
,
2567 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
2568 const VkAllocationCallbacks
*pAllocator
,
2569 VkPipeline
*pPipelines
)
2571 VkResult final_result
= VK_SUCCESS
;
2573 for (uint32_t i
= 0; i
< count
; i
++) {
2574 VkResult result
= tu_graphics_pipeline_create(device
, pipelineCache
,
2575 &pCreateInfos
[i
], pAllocator
,
2578 if (result
!= VK_SUCCESS
)
2579 final_result
= result
;
2582 return final_result
;
2586 tu_compute_pipeline_create(VkDevice device
,
2587 VkPipelineCache _cache
,
2588 const VkComputePipelineCreateInfo
*pCreateInfo
,
2589 const VkAllocationCallbacks
*pAllocator
,
2590 VkPipeline
*pPipeline
)
2592 TU_FROM_HANDLE(tu_device
, dev
, device
);
2593 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, pCreateInfo
->layout
);
2594 const VkPipelineShaderStageCreateInfo
*stage_info
= &pCreateInfo
->stage
;
2597 struct tu_pipeline
*pipeline
;
2599 *pPipeline
= VK_NULL_HANDLE
;
2601 pipeline
= vk_object_zalloc(&dev
->vk
, pAllocator
, sizeof(*pipeline
),
2602 VK_OBJECT_TYPE_PIPELINE
);
2604 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2606 pipeline
->layout
= layout
;
2608 struct ir3_shader_key key
= {};
2610 struct tu_shader
*shader
=
2611 tu_shader_create(dev
, MESA_SHADER_COMPUTE
, stage_info
, layout
, pAllocator
);
2613 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2617 pipeline
->active_desc_sets
= shader
->active_desc_sets
;
2620 struct ir3_shader_variant
*v
=
2621 ir3_shader_get_variant(shader
->ir3_shader
, &key
, false, &created
);
2623 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2627 tu_pipeline_set_linkage(&pipeline
->program
.link
[MESA_SHADER_COMPUTE
],
2630 result
= tu_pipeline_allocate_cs(dev
, pipeline
, NULL
, v
);
2631 if (result
!= VK_SUCCESS
)
2634 uint64_t shader_iova
= tu_upload_variant(pipeline
, v
);
2636 for (int i
= 0; i
< 3; i
++)
2637 pipeline
->compute
.local_size
[i
] = v
->shader
->nir
->info
.cs
.local_size
[i
];
2639 struct tu_cs prog_cs
;
2640 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2641 tu6_emit_cs_config(&prog_cs
, shader
, v
, shader_iova
);
2642 pipeline
->program
.state
= tu_cs_end_draw_state(&pipeline
->cs
, &prog_cs
);
2644 tu6_emit_load_state(pipeline
, true);
2646 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2651 tu_shader_destroy(dev
, shader
, pAllocator
);
2653 vk_object_free(&dev
->vk
, pAllocator
, pipeline
);
2659 tu_CreateComputePipelines(VkDevice device
,
2660 VkPipelineCache pipelineCache
,
2662 const VkComputePipelineCreateInfo
*pCreateInfos
,
2663 const VkAllocationCallbacks
*pAllocator
,
2664 VkPipeline
*pPipelines
)
2666 VkResult final_result
= VK_SUCCESS
;
2668 for (uint32_t i
= 0; i
< count
; i
++) {
2669 VkResult result
= tu_compute_pipeline_create(device
, pipelineCache
,
2671 pAllocator
, &pPipelines
[i
]);
2672 if (result
!= VK_SUCCESS
)
2673 final_result
= result
;
2676 return final_result
;
2680 tu_DestroyPipeline(VkDevice _device
,
2681 VkPipeline _pipeline
,
2682 const VkAllocationCallbacks
*pAllocator
)
2684 TU_FROM_HANDLE(tu_device
, dev
, _device
);
2685 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2690 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2691 vk_object_free(&dev
->vk
, pAllocator
, pipeline
);