projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "common/freedreno_guardband.h"
29 #include "tu_private.h"
30
31 #include "ir3/ir3_nir.h"
32 #include "main/menums.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "util/debug.h"
37 #include "util/mesa-sha1.h"
38 #include "util/u_atomic.h"
39 #include "vk_format.h"
40 #include "vk_util.h"
41
42 #include "tu_cs.h"
43
44 /* Emit IB that preloads the descriptors that the shader uses */
45
46 static void
47 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
48 enum a6xx_state_block sb, unsigned base, unsigned offset,
49 unsigned count)
50 {
51 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
52 * clear if emitting more packets will even help anything. Presumably the
53 * descriptor cache is relatively small, and these packets stop doing
54 * anything when there are too many descriptors.
55 */
56 tu_cs_emit_pkt7(cs, opcode, 3);
57 tu_cs_emit(cs,
58 CP_LOAD_STATE6_0_STATE_TYPE(st) |
59 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
60 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
61 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
62 tu_cs_emit_qw(cs, offset | (base << 28));
63 }
64
65 static unsigned
66 tu6_load_state_size(struct tu_pipeline *pipeline, bool compute)
67 {
68 const unsigned load_state_size = 4;
69 unsigned size = 0;
70 for (unsigned i = 0; i < pipeline->layout->num_sets; i++) {
71 if (pipeline && !(pipeline->active_desc_sets & (1u << i)))
72 continue;
73
74 struct tu_descriptor_set_layout *set_layout = pipeline->layout->set[i].layout;
75 for (unsigned j = 0; j < set_layout->binding_count; j++) {
76 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
77 unsigned count = 0;
78 /* Note: some users, like amber for example, pass in
79 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
80 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
81 */
82 VkShaderStageFlags stages = compute ?
83 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
84 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
85 unsigned stage_count = util_bitcount(stages);
86
87 if (!binding->array_size)
88 continue;
89
90 switch (binding->type) {
91 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
92 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
93 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
94 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
95 /* IBO-backed resources only need one packet for all graphics stages */
96 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
97 count += 1;
98 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
99 count += 1;
100 break;
101 case VK_DESCRIPTOR_TYPE_SAMPLER:
102 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
103 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
104 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
105 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
106 /* Textures and UBO's needs a packet for each stage */
107 count = stage_count;
108 break;
109 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
110 /* Because of how we pack combined images and samplers, we
111 * currently can't use one packet for the whole array.
112 */
113 count = stage_count * binding->array_size * 2;
114 break;
115 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
116 break;
117 default:
118 unreachable("bad descriptor type");
119 }
120 size += count * load_state_size;
121 }
122 }
123 return size;
124 }
125
126 static void
127 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
128 {
129 unsigned size = tu6_load_state_size(pipeline, compute);
130 if (size == 0)
131 return;
132
133 struct tu_cs cs;
134 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
135
136 struct tu_pipeline_layout *layout = pipeline->layout;
137 for (unsigned i = 0; i < layout->num_sets; i++) {
138 /* From 13.2.7. Descriptor Set Binding:
139 *
140 * A compatible descriptor set must be bound for all set numbers that
141 * any shaders in a pipeline access, at the time that a draw or
142 * dispatch command is recorded to execute using that pipeline.
143 * However, if none of the shaders in a pipeline statically use any
144 * bindings with a particular set number, then no descriptor set need
145 * be bound for that set number, even if the pipeline layout includes
146 * a non-trivial descriptor set layout for that set number.
147 *
148 * This means that descriptor sets unused by the pipeline may have a
149 * garbage or 0 BINDLESS_BASE register, which will cause context faults
150 * when prefetching descriptors from these sets. Skip prefetching for
151 * descriptors from them to avoid this. This is also an optimization,
152 * since these prefetches would be useless.
153 */
154 if (!(pipeline->active_desc_sets & (1u << i)))
155 continue;
156
157 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
158 for (unsigned j = 0; j < set_layout->binding_count; j++) {
159 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
160 unsigned base = i;
161 unsigned offset = binding->offset / 4;
162 /* Note: some users, like amber for example, pass in
163 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
164 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
165 */
166 VkShaderStageFlags stages = compute ?
167 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
168 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
169 unsigned count = binding->array_size;
170 if (count == 0 || stages == 0)
171 continue;
172 switch (binding->type) {
173 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
174 base = MAX_SETS;
175 offset = (layout->set[i].dynamic_offset_start +
176 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
177 /* fallthrough */
178 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
179 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
180 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
181 /* IBO-backed resources only need one packet for all graphics stages */
182 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
183 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
184 base, offset, count);
185 }
186 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
187 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
188 base, offset, count);
189 }
190 break;
191 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
192 /* nothing - input attachment doesn't use bindless */
193 break;
194 case VK_DESCRIPTOR_TYPE_SAMPLER:
195 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
196 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
197 tu_foreach_stage(stage, stages) {
198 emit_load_state(&cs, tu6_stage2opcode(stage),
199 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
200 ST6_SHADER : ST6_CONSTANTS,
201 tu6_stage2texsb(stage), base, offset, count);
202 }
203 break;
204 }
205 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
206 base = MAX_SETS;
207 offset = (layout->set[i].dynamic_offset_start +
208 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
209 /* fallthrough */
210 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
211 tu_foreach_stage(stage, stages) {
212 emit_load_state(&cs, tu6_stage2opcode(stage), ST6_UBO,
213 tu6_stage2shadersb(stage), base, offset, count);
214 }
215 break;
216 }
217 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
218 tu_foreach_stage(stage, stages) {
219 /* TODO: We could emit less CP_LOAD_STATE6 if we used
220 * struct-of-arrays instead of array-of-structs.
221 */
222 for (unsigned i = 0; i < count; i++) {
223 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
224 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
225 emit_load_state(&cs, tu6_stage2opcode(stage),
226 ST6_CONSTANTS, tu6_stage2texsb(stage),
227 base, tex_offset, 1);
228 emit_load_state(&cs, tu6_stage2opcode(stage),
229 ST6_SHADER, tu6_stage2texsb(stage),
230 base, sam_offset, 1);
231 }
232 }
233 break;
234 }
235 default:
236 unreachable("bad descriptor type");
237 }
238 }
239 }
240
241 pipeline->load_state = tu_cs_end_draw_state(&pipeline->cs, &cs);
242 }
243
244 struct tu_pipeline_builder
245 {
246 struct tu_device *device;
247 struct tu_pipeline_cache *cache;
248 struct tu_pipeline_layout *layout;
249 const VkAllocationCallbacks *alloc;
250 const VkGraphicsPipelineCreateInfo *create_info;
251
252 struct tu_shader *shaders[MESA_SHADER_STAGES];
253 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
254 struct ir3_shader_variant *binning_variant;
255 uint64_t shader_iova[MESA_SHADER_STAGES];
256 uint64_t binning_vs_iova;
257
258 bool rasterizer_discard;
259 /* these states are affectd by rasterizer_discard */
260 VkSampleCountFlagBits samples;
261 bool use_color_attachments;
262 bool use_dual_src_blend;
263 uint32_t color_attachment_count;
264 VkFormat color_attachment_formats[MAX_RTS];
265 VkFormat depth_attachment_format;
266 uint32_t render_components;
267 uint32_t multiview_mask;
268 };
269
270 static bool
271 tu_logic_op_reads_dst(VkLogicOp op)
272 {
273 switch (op) {
274 case VK_LOGIC_OP_CLEAR:
275 case VK_LOGIC_OP_COPY:
276 case VK_LOGIC_OP_COPY_INVERTED:
277 case VK_LOGIC_OP_SET:
278 return false;
279 default:
280 return true;
281 }
282 }
283
284 static VkBlendFactor
285 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
286 {
287 /* treat dst alpha as 1.0 and avoid reading it */
288 switch (factor) {
289 case VK_BLEND_FACTOR_DST_ALPHA:
290 return VK_BLEND_FACTOR_ONE;
291 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
292 return VK_BLEND_FACTOR_ZERO;
293 default:
294 return factor;
295 }
296 }
297
298 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
299 {
300 switch (factor) {
301 case VK_BLEND_FACTOR_SRC1_COLOR:
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
303 case VK_BLEND_FACTOR_SRC1_ALPHA:
304 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
305 return true;
306 default:
307 return false;
308 }
309 }
310
311 static bool
312 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
313 {
314 if (!info)
315 return false;
316
317 for (unsigned i = 0; i < info->attachmentCount; i++) {
318 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
319 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
320 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
321 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
322 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
323 return true;
324 }
325
326 return false;
327 }
328
329 void
330 tu6_emit_xs_config(struct tu_cs *cs,
331 gl_shader_stage stage, /* xs->type, but xs may be NULL */
332 const struct ir3_shader_variant *xs,
333 uint64_t binary_iova)
334 {
335 static const struct xs_config {
336 uint16_t reg_sp_xs_ctrl;
337 uint16_t reg_sp_xs_config;
338 uint16_t reg_hlsq_xs_ctrl;
339 uint16_t reg_sp_vs_obj_start;
340 } xs_config[] = {
341 [MESA_SHADER_VERTEX] = {
342 REG_A6XX_SP_VS_CTRL_REG0,
343 REG_A6XX_SP_VS_CONFIG,
344 REG_A6XX_HLSQ_VS_CNTL,
345 REG_A6XX_SP_VS_OBJ_START_LO,
346 },
347 [MESA_SHADER_TESS_CTRL] = {
348 REG_A6XX_SP_HS_CTRL_REG0,
349 REG_A6XX_SP_HS_CONFIG,
350 REG_A6XX_HLSQ_HS_CNTL,
351 REG_A6XX_SP_HS_OBJ_START_LO,
352 },
353 [MESA_SHADER_TESS_EVAL] = {
354 REG_A6XX_SP_DS_CTRL_REG0,
355 REG_A6XX_SP_DS_CONFIG,
356 REG_A6XX_HLSQ_DS_CNTL,
357 REG_A6XX_SP_DS_OBJ_START_LO,
358 },
359 [MESA_SHADER_GEOMETRY] = {
360 REG_A6XX_SP_GS_CTRL_REG0,
361 REG_A6XX_SP_GS_CONFIG,
362 REG_A6XX_HLSQ_GS_CNTL,
363 REG_A6XX_SP_GS_OBJ_START_LO,
364 },
365 [MESA_SHADER_FRAGMENT] = {
366 REG_A6XX_SP_FS_CTRL_REG0,
367 REG_A6XX_SP_FS_CONFIG,
368 REG_A6XX_HLSQ_FS_CNTL,
369 REG_A6XX_SP_FS_OBJ_START_LO,
370 },
371 [MESA_SHADER_COMPUTE] = {
372 REG_A6XX_SP_CS_CTRL_REG0,
373 REG_A6XX_SP_CS_CONFIG,
374 REG_A6XX_HLSQ_CS_CNTL,
375 REG_A6XX_SP_CS_OBJ_START_LO,
376 },
377 };
378 const struct xs_config *cfg = &xs_config[stage];
379
380 if (!xs) {
381 /* shader stage disabled */
382 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
383 tu_cs_emit(cs, 0);
384
385 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
386 tu_cs_emit(cs, 0);
387 return;
388 }
389
390 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
391 enum a3xx_threadsize threadsize = FOUR_QUADS;
392
393 /* TODO:
394 * the "threadsize" field may have nothing to do with threadsize,
395 * use a value that matches the blob until it is figured out
396 */
397 if (xs->type == MESA_SHADER_GEOMETRY)
398 threadsize = TWO_QUADS;
399
400 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
401 tu_cs_emit(cs,
402 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
403 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
404 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs->info.max_half_reg + 1) |
405 COND(xs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
406 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
407 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
408 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
409 /* only fragment shader sets VARYING bit */
410 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
411 /* unknown bit, seems unnecessary */
412 COND(is_fs, 0x1000000));
413
414 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
415 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
416 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
417 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
418 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
419 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
420 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
421 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
422 tu_cs_emit(cs, xs->instrlen);
423
424 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
425 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) |
426 A6XX_HLSQ_VS_CNTL_ENABLED);
427
428 /* emit program binary
429 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
430 */
431
432 assert((binary_iova & 0x7f) == 0);
433
434 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
435 tu_cs_emit_qw(cs, binary_iova);
436
437 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
438 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
439 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
440 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
441 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
442 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
443 tu_cs_emit_qw(cs, binary_iova);
444
445 /* emit immediates */
446
447 const struct ir3_const_state *const_state = ir3_const_state(xs);
448 uint32_t base = const_state->offsets.immediate;
449 int size = DIV_ROUND_UP(const_state->immediates_count, 4);
450
451 /* truncate size to avoid writing constants that shader
452 * does not use:
453 */
454 size = MIN2(size + base, xs->constlen) - base;
455
456 if (size <= 0)
457 return;
458
459 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + size * 4);
460 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
461 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
462 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
463 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
464 CP_LOAD_STATE6_0_NUM_UNIT(size));
465 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
466 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
467
468 tu_cs_emit_array(cs, const_state->immediates, size * 4);
469 }
470
471 static void
472 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
473 const struct ir3_shader_variant *v,
474 uint32_t binary_iova)
475 {
476 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
477 .cs_state = true,
478 .cs_ibo = true));
479
480 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
481
482 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
483 tu_cs_emit(cs, 0x41);
484
485 uint32_t local_invocation_id =
486 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
487 uint32_t work_group_id =
488 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
489
490 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
491 tu_cs_emit(cs,
492 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
493 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
494 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
495 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
496 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
497 }
498
499 static void
500 tu6_emit_vs_system_values(struct tu_cs *cs,
501 const struct ir3_shader_variant *vs,
502 const struct ir3_shader_variant *hs,
503 const struct ir3_shader_variant *ds,
504 const struct ir3_shader_variant *gs,
505 bool primid_passthru)
506 {
507 const uint32_t vertexid_regid =
508 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
509 const uint32_t instanceid_regid =
510 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
511 const uint32_t tess_coord_x_regid = hs ?
512 ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD) :
513 regid(63, 0);
514 const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ?
515 tess_coord_x_regid + 1 :
516 regid(63, 0);
517 const uint32_t hs_patch_regid = hs ?
518 ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
519 regid(63, 0);
520 const uint32_t ds_patch_regid = hs ?
521 ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
522 regid(63, 0);
523 const uint32_t hs_invocation_regid = hs ?
524 ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) :
525 regid(63, 0);
526 const uint32_t primitiveid_regid = gs ?
527 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
528 regid(63, 0);
529 const uint32_t gsheader_regid = gs ?
530 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
531 regid(63, 0);
532
533 /* Note: we currently don't support multiview with tess or GS. If we did,
534 * and the HW actually works, then we'd have to somehow share this across
535 * stages. Note that the blob doesn't support this either.
536 */
537 const uint32_t viewid_regid =
538 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VIEW_INDEX);
539
540 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
541 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
542 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
543 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
544 A6XX_VFD_CONTROL_1_REGID4VIEWID(viewid_regid));
545 tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
546 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
547 tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
548 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
549 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
550 0xfc);
551 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
552 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
553 0xfc00); /* VFD_CONTROL_5 */
554 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
555 }
556
557 /* Add any missing varyings needed for stream-out. Otherwise varyings not
558 * used by fragment shader will be stripped out.
559 */
560 static void
561 tu6_link_streamout(struct ir3_shader_linkage *l,
562 const struct ir3_shader_variant *v)
563 {
564 const struct ir3_stream_output_info *info = &v->shader->stream_output;
565
566 /*
567 * First, any stream-out varyings not already in linkage map (ie. also
568 * consumed by frag shader) need to be added:
569 */
570 for (unsigned i = 0; i < info->num_outputs; i++) {
571 const struct ir3_stream_output *out = &info->output[i];
572 unsigned compmask =
573 (1 << (out->num_components + out->start_component)) - 1;
574 unsigned k = out->register_index;
575 unsigned idx, nextloc = 0;
576
577 /* psize/pos need to be the last entries in linkage map, and will
578 * get added link_stream_out, so skip over them:
579 */
580 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
581 v->outputs[k].slot == VARYING_SLOT_POS)
582 continue;
583
584 for (idx = 0; idx < l->cnt; idx++) {
585 if (l->var[idx].regid == v->outputs[k].regid)
586 break;
587 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
588 }
589
590 /* add if not already in linkage map: */
591 if (idx == l->cnt)
592 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
593
594 /* expand component-mask if needed, ie streaming out all components
595 * but frag shader doesn't consume all components:
596 */
597 if (compmask & ~l->var[idx].compmask) {
598 l->var[idx].compmask |= compmask;
599 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
600 util_last_bit(l->var[idx].compmask));
601 }
602 }
603 }
604
605 static void
606 tu6_setup_streamout(struct tu_cs *cs,
607 const struct ir3_shader_variant *v,
608 struct ir3_shader_linkage *l)
609 {
610 const struct ir3_stream_output_info *info = &v->shader->stream_output;
611 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2] = {};
612 uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {};
613 uint32_t prog_count = align(l->max_loc, 2) / 2;
614
615 /* TODO: streamout state should be in a non-GMEM draw state */
616
617 /* no streamout: */
618 if (info->num_outputs == 0) {
619 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
620 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
621 tu_cs_emit(cs, 0);
622 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
623 tu_cs_emit(cs, 0);
624 return;
625 }
626
627 /* is there something to do with info->stride[i]? */
628
629 for (unsigned i = 0; i < info->num_outputs; i++) {
630 const struct ir3_stream_output *out = &info->output[i];
631 unsigned k = out->register_index;
632 unsigned idx;
633
634 /* Skip it, if there's an unused reg in the middle of outputs. */
635 if (v->outputs[k].regid == INVALID_REG)
636 continue;
637
638 ncomp[out->output_buffer] += out->num_components;
639
640 /* linkage map sorted by order frag shader wants things, so
641 * a bit less ideal here..
642 */
643 for (idx = 0; idx < l->cnt; idx++)
644 if (l->var[idx].regid == v->outputs[k].regid)
645 break;
646
647 debug_assert(idx < l->cnt);
648
649 for (unsigned j = 0; j < out->num_components; j++) {
650 unsigned c = j + out->start_component;
651 unsigned loc = l->var[idx].loc + c;
652 unsigned off = j + out->dst_offset; /* in dwords */
653
654 if (loc & 1) {
655 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
656 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
657 A6XX_VPC_SO_PROG_B_OFF(off * 4);
658 } else {
659 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
660 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
661 A6XX_VPC_SO_PROG_A_OFF(off * 4);
662 }
663 }
664 }
665
666 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count);
667 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
668 tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE |
669 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
670 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
671 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
672 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
673 for (uint32_t i = 0; i < 4; i++) {
674 tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
675 tu_cs_emit(cs, ncomp[i]);
676 }
677 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
678 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
679 tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
680 for (uint32_t i = 0; i < prog_count; i++) {
681 tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
682 tu_cs_emit(cs, prog[i]);
683 }
684 }
685
686 static void
687 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
688 enum a6xx_state_block block, uint32_t offset,
689 uint32_t size, uint32_t *dwords) {
690 assert(size % 4 == 0);
691
692 tu_cs_emit_pkt7(cs, opcode, 3 + size);
693 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
694 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
695 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
696 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
697 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
698
699 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
700 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
701 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
702
703 tu_cs_emit_array(cs, dwords, size);
704 }
705
706 static void
707 tu6_emit_link_map(struct tu_cs *cs,
708 const struct ir3_shader_variant *producer,
709 const struct ir3_shader_variant *consumer,
710 enum a6xx_state_block sb)
711 {
712 const struct ir3_const_state *const_state = ir3_const_state(consumer);
713 uint32_t base = const_state->offsets.primitive_map;
714 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
715 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
716 int size = DIV_ROUND_UP(num_loc, 4);
717
718 size = (MIN2(size + base, consumer->constlen) - base) * 4;
719 if (size <= 0)
720 return;
721
722 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, sb, 0, size,
723 patch_locs);
724 }
725
726 static uint16_t
727 gl_primitive_to_tess(uint16_t primitive) {
728 switch (primitive) {
729 case GL_POINTS:
730 return TESS_POINTS;
731 case GL_LINE_STRIP:
732 return TESS_LINES;
733 case GL_TRIANGLE_STRIP:
734 return TESS_CW_TRIS;
735 default:
736 unreachable("");
737 }
738 }
739
740 void
741 tu6_emit_vpc(struct tu_cs *cs,
742 const struct ir3_shader_variant *vs,
743 const struct ir3_shader_variant *hs,
744 const struct ir3_shader_variant *ds,
745 const struct ir3_shader_variant *gs,
746 const struct ir3_shader_variant *fs,
747 uint32_t patch_control_points,
748 bool vshs_workgroup)
749 {
750 /* note: doesn't compile as static because of the array regs.. */
751 const struct reg_config {
752 uint16_t reg_sp_xs_out_reg;
753 uint16_t reg_sp_xs_vpc_dst_reg;
754 uint16_t reg_vpc_xs_pack;
755 uint16_t reg_vpc_xs_clip_cntl;
756 uint16_t reg_gras_xs_cl_cntl;
757 uint16_t reg_pc_xs_out_cntl;
758 uint16_t reg_sp_xs_primitive_cntl;
759 uint16_t reg_vpc_xs_layer_cntl;
760 uint16_t reg_gras_xs_layer_cntl;
761 } reg_config[] = {
762 [MESA_SHADER_VERTEX] = {
763 REG_A6XX_SP_VS_OUT_REG(0),
764 REG_A6XX_SP_VS_VPC_DST_REG(0),
765 REG_A6XX_VPC_VS_PACK,
766 REG_A6XX_VPC_VS_CLIP_CNTL,
767 REG_A6XX_GRAS_VS_CL_CNTL,
768 REG_A6XX_PC_VS_OUT_CNTL,
769 REG_A6XX_SP_VS_PRIMITIVE_CNTL,
770 REG_A6XX_VPC_VS_LAYER_CNTL,
771 REG_A6XX_GRAS_VS_LAYER_CNTL
772 },
773 [MESA_SHADER_TESS_EVAL] = {
774 REG_A6XX_SP_DS_OUT_REG(0),
775 REG_A6XX_SP_DS_VPC_DST_REG(0),
776 REG_A6XX_VPC_DS_PACK,
777 REG_A6XX_VPC_DS_CLIP_CNTL,
778 REG_A6XX_GRAS_DS_CL_CNTL,
779 REG_A6XX_PC_DS_OUT_CNTL,
780 REG_A6XX_SP_DS_PRIMITIVE_CNTL,
781 REG_A6XX_VPC_DS_LAYER_CNTL,
782 REG_A6XX_GRAS_DS_LAYER_CNTL
783 },
784 [MESA_SHADER_GEOMETRY] = {
785 REG_A6XX_SP_GS_OUT_REG(0),
786 REG_A6XX_SP_GS_VPC_DST_REG(0),
787 REG_A6XX_VPC_GS_PACK,
788 REG_A6XX_VPC_GS_CLIP_CNTL,
789 REG_A6XX_GRAS_GS_CL_CNTL,
790 REG_A6XX_PC_GS_OUT_CNTL,
791 REG_A6XX_SP_GS_PRIMITIVE_CNTL,
792 REG_A6XX_VPC_GS_LAYER_CNTL,
793 REG_A6XX_GRAS_GS_LAYER_CNTL
794 },
795 };
796
797 const struct ir3_shader_variant *last_shader;
798 if (gs) {
799 last_shader = gs;
800 } else if (hs) {
801 last_shader = ds;
802 } else {
803 last_shader = vs;
804 }
805
806 const struct reg_config *cfg = &reg_config[last_shader->type];
807
808 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
809 if (fs)
810 ir3_link_shaders(&linkage, last_shader, fs, true);
811
812 if (last_shader->shader->stream_output.num_outputs)
813 tu6_link_streamout(&linkage, last_shader);
814
815 /* We do this after linking shaders in order to know whether PrimID
816 * passthrough needs to be enabled.
817 */
818 bool primid_passthru = linkage.primid_loc != 0xff;
819 tu6_emit_vs_system_values(cs, vs, hs, ds, gs, primid_passthru);
820
821 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
822 tu_cs_emit(cs, ~linkage.varmask[0]);
823 tu_cs_emit(cs, ~linkage.varmask[1]);
824 tu_cs_emit(cs, ~linkage.varmask[2]);
825 tu_cs_emit(cs, ~linkage.varmask[3]);
826
827 /* a6xx finds position/pointsize at the end */
828 const uint32_t position_regid =
829 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
830 const uint32_t pointsize_regid =
831 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
832 const uint32_t layer_regid =
833 ir3_find_output_regid(last_shader, VARYING_SLOT_LAYER);
834 uint32_t primitive_regid = gs ?
835 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) : regid(63, 0);
836 uint32_t flags_regid = gs ?
837 ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3) : 0;
838
839 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
840 if (layer_regid != regid(63, 0)) {
841 layer_loc = linkage.max_loc;
842 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
843 }
844 if (position_regid != regid(63, 0)) {
845 position_loc = linkage.max_loc;
846 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
847 }
848 if (pointsize_regid != regid(63, 0)) {
849 pointsize_loc = linkage.max_loc;
850 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
851 }
852
853 tu6_setup_streamout(cs, last_shader, &linkage);
854
855 /* The GPU hangs on some models when there are no outputs (xs_pack::CNT),
856 * at least when a DS is the last stage, so add a dummy output to keep it
857 * happy if there aren't any. We do this late in order to avoid emitting
858 * any unused code and make sure that optimizations don't remove it.
859 */
860 if (linkage.cnt == 0)
861 ir3_link_add(&linkage, 0, 0x1, linkage.max_loc);
862
863 /* map outputs of the last shader to VPC */
864 assert(linkage.cnt <= 32);
865 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
866 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
867 uint32_t sp_out[16];
868 uint32_t sp_vpc_dst[8];
869 for (uint32_t i = 0; i < linkage.cnt; i++) {
870 ((uint16_t *) sp_out)[i] =
871 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
872 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
873 ((uint8_t *) sp_vpc_dst)[i] =
874 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
875 }
876
877 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_out_reg, sp_out_count);
878 tu_cs_emit_array(cs, sp_out, sp_out_count);
879
880 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_vpc_dst_reg, sp_vpc_dst_count);
881 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
882
883 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_pack, 1);
884 tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
885 A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) |
886 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc));
887
888 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_clip_cntl, 1);
889 tu_cs_emit(cs, 0xffff00);
890
891 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_cl_cntl, 1);
892 tu_cs_emit(cs, 0);
893
894 tu_cs_emit_pkt4(cs, cfg->reg_pc_xs_out_cntl, 1);
895 tu_cs_emit(cs, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
896 CONDREG(pointsize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
897 CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
898 CONDREG(primitive_regid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID));
899
900 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_primitive_cntl, 1);
901 tu_cs_emit(cs, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt) |
902 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
903
904 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_layer_cntl, 1);
905 tu_cs_emit(cs, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
906
907 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_layer_cntl, 1);
908 tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
909
910 tu_cs_emit_regs(cs, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
911
912 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
913 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
914 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
915 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
916 A6XX_VPC_CNTL_0_VIEWIDLOC(linkage.viewid_loc));
917
918 if (hs) {
919 shader_info *hs_info = &hs->shader->nir->info;
920 uint32_t unknown_a831 = vs->output_size;
921
922 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
923 tu_cs_emit(cs, hs_info->tess.tcs_vertices_out);
924
925 /* Total attribute slots in HS incoming patch. */
926 tu_cs_emit_pkt4(cs, REG_A6XX_PC_HS_INPUT_SIZE, 1);
927 tu_cs_emit(cs, patch_control_points * vs->output_size / 4);
928
929 /* for A650 this value seems to be local memory size per wave */
930 if (vshs_workgroup) {
931 const uint32_t wavesize = 64;
932 /* note: if HS is really just the VS extended, then this
933 * should be by MAX2(patch_control_points, hs_info->tess.tcs_vertices_out)
934 * however that doesn't match the blob, and fails some dEQP tests.
935 */
936 uint32_t prims_per_wave = wavesize / hs_info->tess.tcs_vertices_out;
937 uint32_t total_size = vs->output_size * patch_control_points * prims_per_wave;
938 unknown_a831 = DIV_ROUND_UP(total_size, wavesize);
939 }
940
941 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
942 tu_cs_emit(cs, unknown_a831);
943
944 /* In SPIR-V generated from GLSL, the tessellation primitive params are
945 * are specified in the tess eval shader, but in SPIR-V generated from
946 * HLSL, they are specified in the tess control shader. */
947 shader_info *tess_info =
948 ds->shader->nir->info.tess.spacing == TESS_SPACING_UNSPECIFIED ?
949 &hs->shader->nir->info : &ds->shader->nir->info;
950 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_CNTL, 1);
951 uint32_t output;
952 if (tess_info->tess.point_mode)
953 output = TESS_POINTS;
954 else if (tess_info->tess.primitive_mode == GL_ISOLINES)
955 output = TESS_LINES;
956 else if (tess_info->tess.ccw)
957 output = TESS_CCW_TRIS;
958 else
959 output = TESS_CW_TRIS;
960
961 enum a6xx_tess_spacing spacing;
962 switch (tess_info->tess.spacing) {
963 case TESS_SPACING_EQUAL:
964 spacing = TESS_EQUAL;
965 break;
966 case TESS_SPACING_FRACTIONAL_ODD:
967 spacing = TESS_FRACTIONAL_ODD;
968 break;
969 case TESS_SPACING_FRACTIONAL_EVEN:
970 spacing = TESS_FRACTIONAL_EVEN;
971 break;
972 case TESS_SPACING_UNSPECIFIED:
973 default:
974 unreachable("invalid tess spacing");
975 }
976 tu_cs_emit(cs, A6XX_PC_TESS_CNTL_SPACING(spacing) |
977 A6XX_PC_TESS_CNTL_OUTPUT(output));
978
979 tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
980 tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER);
981 }
982
983
984 if (gs) {
985 uint32_t vertices_out, invocations, output, vec4_size;
986 /* this detects the tu_clear_blit path, which doesn't set ->nir */
987 if (gs->shader->nir) {
988 if (hs) {
989 tu6_emit_link_map(cs, ds, gs, SB6_GS_SHADER);
990 } else {
991 tu6_emit_link_map(cs, vs, gs, SB6_GS_SHADER);
992 }
993 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
994 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
995 invocations = gs->shader->nir->info.gs.invocations - 1;
996 /* Size of per-primitive alloction in ldlw memory in vec4s. */
997 vec4_size = gs->shader->nir->info.gs.vertices_in *
998 DIV_ROUND_UP(vs->output_size, 4);
999 } else {
1000 vertices_out = 3;
1001 output = TESS_CW_TRIS;
1002 invocations = 0;
1003 vec4_size = 0;
1004 }
1005
1006 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1007 tu_cs_emit(cs,
1008 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1009 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1010 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1011
1012 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1013 tu_cs_emit(cs, 0);
1014
1015 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1016 tu_cs_emit(cs, 0xff);
1017
1018 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1019 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1020
1021 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1022 tu_cs_emit(cs, vs->output_size);
1023 }
1024 }
1025
1026 static int
1027 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1028 uint32_t index,
1029 uint8_t *interp_mode,
1030 uint8_t *ps_repl_mode)
1031 {
1032 enum
1033 {
1034 INTERP_SMOOTH = 0,
1035 INTERP_FLAT = 1,
1036 INTERP_ZERO = 2,
1037 INTERP_ONE = 3,
1038 };
1039 enum
1040 {
1041 PS_REPL_NONE = 0,
1042 PS_REPL_S = 1,
1043 PS_REPL_T = 2,
1044 PS_REPL_ONE_MINUS_T = 3,
1045 };
1046
1047 const uint32_t compmask = fs->inputs[index].compmask;
1048
1049 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1050 * fourth component occupy three consecutive varying slots
1051 */
1052 int shift = 0;
1053 *interp_mode = 0;
1054 *ps_repl_mode = 0;
1055 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1056 if (compmask & 0x1) {
1057 *ps_repl_mode |= PS_REPL_S << shift;
1058 shift += 2;
1059 }
1060 if (compmask & 0x2) {
1061 *ps_repl_mode |= PS_REPL_T << shift;
1062 shift += 2;
1063 }
1064 if (compmask & 0x4) {
1065 *interp_mode |= INTERP_ZERO << shift;
1066 shift += 2;
1067 }
1068 if (compmask & 0x8) {
1069 *interp_mode |= INTERP_ONE << 6;
1070 shift += 2;
1071 }
1072 } else if (fs->inputs[index].flat) {
1073 for (int i = 0; i < 4; i++) {
1074 if (compmask & (1 << i)) {
1075 *interp_mode |= INTERP_FLAT << shift;
1076 shift += 2;
1077 }
1078 }
1079 }
1080
1081 return shift;
1082 }
1083
1084 static void
1085 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1086 const struct ir3_shader_variant *fs)
1087 {
1088 uint32_t interp_modes[8] = { 0 };
1089 uint32_t ps_repl_modes[8] = { 0 };
1090
1091 if (fs) {
1092 for (int i = -1;
1093 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1094
1095 /* get the mode for input i */
1096 uint8_t interp_mode;
1097 uint8_t ps_repl_mode;
1098 const int bits =
1099 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1100
1101 /* OR the mode into the array */
1102 const uint32_t inloc = fs->inputs[i].inloc * 2;
1103 uint32_t n = inloc / 32;
1104 uint32_t shift = inloc % 32;
1105 interp_modes[n] |= interp_mode << shift;
1106 ps_repl_modes[n] |= ps_repl_mode << shift;
1107 if (shift + bits > 32) {
1108 n++;
1109 shift = 32 - shift;
1110
1111 interp_modes[n] |= interp_mode >> shift;
1112 ps_repl_modes[n] |= ps_repl_mode >> shift;
1113 }
1114 }
1115 }
1116
1117 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1118 tu_cs_emit_array(cs, interp_modes, 8);
1119
1120 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1121 tu_cs_emit_array(cs, ps_repl_modes, 8);
1122 }
1123
1124 void
1125 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1126 {
1127 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1128 uint32_t ij_regid[IJ_COUNT];
1129 uint32_t smask_in_regid;
1130
1131 bool sample_shading = fs->per_samp | fs->key.sample_shading;
1132 bool enable_varyings = fs->total_in > 0;
1133
1134 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1135 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1136 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1137 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1138 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1139 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
1140 ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
1141
1142 if (VALIDREG(ij_regid[IJ_LINEAR_SAMPLE]))
1143 tu_finishme("linear sample varying");
1144
1145 if (VALIDREG(ij_regid[IJ_LINEAR_CENTROID]))
1146 tu_finishme("linear centroid varying");
1147
1148 if (fs->num_sampler_prefetch > 0) {
1149 assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
1150 /* also, it seems like ij_pix is *required* to be r0.x */
1151 assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
1152 }
1153
1154 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1155 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1156 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1157 0x7000); // XXX);
1158 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1159 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1160 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1161 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1162 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1163 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1164 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1165 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1166 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1167 }
1168
1169 if (fs->num_sampler_prefetch > 0) {
1170 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1171 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1172 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1173 tu_cs_emit(cs,
1174 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1175 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1176 }
1177 }
1178
1179 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1180 tu_cs_emit(cs, 0x7);
1181 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1182 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1183 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1184 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
1185 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
1186 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
1187 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
1188 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
1189 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1190 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1191 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
1192 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
1193 tu_cs_emit(cs, 0xfc);
1194
1195 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1196 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1197
1198 bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
1199 bool need_size_persamp = false;
1200 if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
1201 if (sample_shading)
1202 need_size_persamp = true;
1203 else
1204 need_size = true;
1205 }
1206 if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
1207 need_size = true;
1208
1209 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1210 tu_cs_emit(cs,
1211 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
1212 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
1213 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
1214 COND(need_size, A6XX_GRAS_CNTL_SIZE) |
1215 COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1216 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
1217
1218 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1219 tu_cs_emit(cs,
1220 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
1221 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
1222 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
1223 COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
1224 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1225 COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1226 COND(fs->fragcoord_compmask != 0,
1227 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
1228 tu_cs_emit(cs,
1229 /* these two bits (UNK4/UNK5) relate to fragcoord
1230 * without them, fragcoord is the same for all samples
1231 */
1232 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) |
1233 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) |
1234 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1235 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1236 CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
1237 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1238
1239 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1240 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1241
1242 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1243 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1244
1245 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1246 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1247 }
1248
1249 static void
1250 tu6_emit_fs_outputs(struct tu_cs *cs,
1251 const struct ir3_shader_variant *fs,
1252 uint32_t mrt_count, bool dual_src_blend,
1253 uint32_t render_components,
1254 bool is_s8_uint)
1255 {
1256 uint32_t smask_regid, posz_regid, stencilref_regid;
1257
1258 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1259 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1260 stencilref_regid = ir3_find_output_regid(fs, FRAG_RESULT_STENCIL);
1261
1262 uint32_t fragdata_regid[8];
1263 if (fs->color0_mrt) {
1264 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1265 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1266 fragdata_regid[i] = fragdata_regid[0];
1267 } else {
1268 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1269 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1270 }
1271
1272 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1273 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1274 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1275 A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid) |
1276 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1277 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1278
1279 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1280 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1281 // TODO we could have a mix of half and full precision outputs,
1282 // we really need to figure out half-precision from IR3_REG_HALF
1283 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1284 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1285 }
1286
1287 tu_cs_emit_regs(cs,
1288 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1289
1290 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1291 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1292 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1293 COND(fs->writes_stencilref, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF) |
1294 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1295 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1296
1297 tu_cs_emit_regs(cs,
1298 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1299
1300 enum a6xx_ztest_mode zmode;
1301
1302 if (fs->no_earlyz || fs->has_kill || fs->writes_pos || fs->writes_stencilref || is_s8_uint) {
1303 zmode = A6XX_LATE_Z;
1304 } else {
1305 zmode = A6XX_EARLY_Z;
1306 }
1307
1308 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1309 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1310
1311 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1312 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1313 }
1314
1315 static void
1316 tu6_emit_geom_tess_consts(struct tu_cs *cs,
1317 const struct ir3_shader_variant *vs,
1318 const struct ir3_shader_variant *hs,
1319 const struct ir3_shader_variant *ds,
1320 const struct ir3_shader_variant *gs,
1321 uint32_t cps_per_patch)
1322 {
1323 uint32_t num_vertices =
1324 hs ? cps_per_patch : gs->shader->nir->info.gs.vertices_in;
1325
1326 uint32_t vs_params[4] = {
1327 vs->output_size * num_vertices * 4, /* vs primitive stride */
1328 vs->output_size * 4, /* vs vertex stride */
1329 0,
1330 0,
1331 };
1332 uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param;
1333 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1334 ARRAY_SIZE(vs_params), vs_params);
1335
1336 if (hs) {
1337 assert(ds->type != MESA_SHADER_NONE);
1338 uint32_t hs_params[4] = {
1339 vs->output_size * num_vertices * 4, /* hs primitive stride */
1340 vs->output_size * 4, /* hs vertex stride */
1341 hs->output_size,
1342 cps_per_patch,
1343 };
1344
1345 uint32_t hs_base = hs->const_state->offsets.primitive_param;
1346 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, hs_base, SB6_HS_SHADER, 0,
1347 ARRAY_SIZE(hs_params), hs_params);
1348 if (gs)
1349 num_vertices = gs->shader->nir->info.gs.vertices_in;
1350
1351 uint32_t ds_params[4] = {
1352 ds->output_size * num_vertices * 4, /* ds primitive stride */
1353 ds->output_size * 4, /* ds vertex stride */
1354 hs->output_size, /* hs vertex stride (dwords) */
1355 hs->shader->nir->info.tess.tcs_vertices_out
1356 };
1357
1358 uint32_t ds_base = ds->const_state->offsets.primitive_param;
1359 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, ds_base, SB6_DS_SHADER, 0,
1360 ARRAY_SIZE(ds_params), ds_params);
1361 }
1362
1363 if (gs) {
1364 const struct ir3_shader_variant *prev = ds ? ds : vs;
1365 uint32_t gs_params[4] = {
1366 prev->output_size * num_vertices * 4, /* gs primitive stride */
1367 prev->output_size * 4, /* gs vertex stride */
1368 0,
1369 0,
1370 };
1371 uint32_t gs_base = gs->const_state->offsets.primitive_param;
1372 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1373 ARRAY_SIZE(gs_params), gs_params);
1374 }
1375 }
1376
1377 static void
1378 tu6_emit_program(struct tu_cs *cs,
1379 struct tu_pipeline_builder *builder,
1380 bool binning_pass)
1381 {
1382 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
1383 const struct ir3_shader_variant *bs = builder->binning_variant;
1384 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
1385 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
1386 const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
1387 const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
1388 gl_shader_stage stage = MESA_SHADER_VERTEX;
1389 uint32_t cps_per_patch = builder->create_info->pTessellationState ?
1390 builder->create_info->pTessellationState->patchControlPoints : 0;
1391
1392 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1393
1394 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
1395 .vs_state = true,
1396 .hs_state = true,
1397 .ds_state = true,
1398 .gs_state = true,
1399 .fs_state = true,
1400 .gfx_ibo = true));
1401
1402 /* Don't use the binning pass variant when GS is present because we don't
1403 * support compiling correct binning pass variants with GS.
1404 */
1405 if (binning_pass && !gs) {
1406 vs = bs;
1407 tu6_emit_xs_config(cs, stage, bs, builder->binning_vs_iova);
1408 stage++;
1409 }
1410
1411 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1412 const struct ir3_shader_variant *xs = builder->variants[stage];
1413
1414 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1415 fs = xs = NULL;
1416
1417 tu6_emit_xs_config(cs, stage, xs, builder->shader_iova[stage]);
1418 }
1419
1420 if (!binning_pass) {
1421 uint32_t multiview_views = util_logbase2(builder->multiview_mask) + 1;
1422 uint32_t multiview_cntl = builder->multiview_mask ?
1423 A6XX_PC_MULTIVIEW_CNTL_ENABLE |
1424 A6XX_PC_MULTIVIEW_CNTL_VIEWS(multiview_views) |
1425 A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS /* TODO multi-pos output */
1426 : 0;
1427
1428 /* Copy what the blob does here. This will emit an extra 0x3f
1429 * CP_EVENT_WRITE when multiview is disabled. I'm not exactly sure what
1430 * this is working around yet.
1431 */
1432 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
1433 tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(UNK_EVENT_WRITE));
1434 tu_cs_emit(cs, REG_A6XX_PC_MULTIVIEW_CNTL);
1435 tu_cs_emit(cs, multiview_cntl);
1436
1437 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MULTIVIEW_CNTL, 1);
1438 tu_cs_emit(cs, multiview_cntl);
1439
1440 if (multiview_cntl &&
1441 builder->device->physical_device->supports_multiview_mask) {
1442 tu_cs_emit_pkt4(cs, REG_A6XX_PC_MULTIVIEW_MASK, 1);
1443 tu_cs_emit(cs, builder->multiview_mask);
1444 }
1445 }
1446
1447 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1448 tu_cs_emit(cs, 0);
1449
1450 tu6_emit_vpc(cs, vs, hs, ds, gs, fs, cps_per_patch,
1451 builder->device->physical_device->gpu_id == 650);
1452 tu6_emit_vpc_varying_modes(cs, fs);
1453
1454 if (fs) {
1455 tu6_emit_fs_inputs(cs, fs);
1456 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1457 builder->use_dual_src_blend,
1458 builder->render_components,
1459 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1460 } else {
1461 /* TODO: check if these can be skipped if fs is disabled */
1462 struct ir3_shader_variant dummy_variant = {};
1463 tu6_emit_fs_inputs(cs, &dummy_variant);
1464 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1465 builder->use_dual_src_blend,
1466 builder->render_components,
1467 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1468 }
1469
1470 if (gs || hs) {
1471 tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch);
1472 }
1473 }
1474
1475 static void
1476 tu6_emit_vertex_input(struct tu_cs *cs,
1477 const struct ir3_shader_variant *vs,
1478 const VkPipelineVertexInputStateCreateInfo *info,
1479 uint32_t *bindings_used)
1480 {
1481 uint32_t vfd_decode_idx = 0;
1482 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1483 uint32_t step_rate[MAX_VBS];
1484
1485 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1486 const VkVertexInputBindingDescription *binding =
1487 &info->pVertexBindingDescriptions[i];
1488
1489 tu_cs_emit_regs(cs,
1490 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1491
1492 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1493 binding_instanced |= 1 << binding->binding;
1494
1495 *bindings_used |= 1 << binding->binding;
1496 step_rate[binding->binding] = 1;
1497 }
1498
1499 const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_state =
1500 vk_find_struct_const(info->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1501 if (div_state) {
1502 for (uint32_t i = 0; i < div_state->vertexBindingDivisorCount; i++) {
1503 const VkVertexInputBindingDivisorDescriptionEXT *desc =
1504 &div_state->pVertexBindingDivisors[i];
1505 step_rate[desc->binding] = desc->divisor;
1506 }
1507 }
1508
1509 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1510
1511 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1512 const VkVertexInputAttributeDescription *attr =
1513 &info->pVertexAttributeDescriptions[i];
1514 uint32_t input_idx;
1515
1516 assert(*bindings_used & BIT(attr->binding));
1517
1518 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1519 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1520 break;
1521 }
1522
1523 /* attribute not used, skip it */
1524 if (input_idx == vs->inputs_count)
1525 continue;
1526
1527 const struct tu_native_format format = tu6_format_vtx(attr->format);
1528 tu_cs_emit_regs(cs,
1529 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1530 .idx = attr->binding,
1531 .offset = attr->offset,
1532 .instanced = binding_instanced & (1 << attr->binding),
1533 .format = format.fmt,
1534 .swap = format.swap,
1535 .unk30 = 1,
1536 ._float = !vk_format_is_int(attr->format)),
1537 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, step_rate[attr->binding]));
1538
1539 tu_cs_emit_regs(cs,
1540 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1541 .writemask = vs->inputs[input_idx].compmask,
1542 .regid = vs->inputs[input_idx].regid));
1543
1544 vfd_decode_idx++;
1545 }
1546
1547 tu_cs_emit_regs(cs,
1548 A6XX_VFD_CONTROL_0(
1549 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1550 .decode_cnt = vfd_decode_idx));
1551 }
1552
1553 void
1554 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1555 {
1556 float offsets[3];
1557 float scales[3];
1558 scales[0] = viewport->width / 2.0f;
1559 scales[1] = viewport->height / 2.0f;
1560 scales[2] = viewport->maxDepth - viewport->minDepth;
1561 offsets[0] = viewport->x + scales[0];
1562 offsets[1] = viewport->y + scales[1];
1563 offsets[2] = viewport->minDepth;
1564
1565 VkOffset2D min;
1566 VkOffset2D max;
1567 min.x = (int32_t) viewport->x;
1568 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1569 if (viewport->height >= 0.0f) {
1570 min.y = (int32_t) viewport->y;
1571 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1572 } else {
1573 min.y = (int32_t)(viewport->y + viewport->height);
1574 max.y = (int32_t) ceilf(viewport->y);
1575 }
1576 /* the spec allows viewport->height to be 0.0f */
1577 if (min.y == max.y)
1578 max.y++;
1579 assert(min.x >= 0 && min.x < max.x);
1580 assert(min.y >= 0 && min.y < max.y);
1581
1582 VkExtent2D guardband_adj;
1583 guardband_adj.width = fd_calc_guardband(offsets[0], scales[0], false);
1584 guardband_adj.height = fd_calc_guardband(offsets[1], scales[1], false);
1585
1586 tu_cs_emit_regs(cs,
1587 A6XX_GRAS_CL_VPORT_XOFFSET(0, offsets[0]),
1588 A6XX_GRAS_CL_VPORT_XSCALE(0, scales[0]),
1589 A6XX_GRAS_CL_VPORT_YOFFSET(0, offsets[1]),
1590 A6XX_GRAS_CL_VPORT_YSCALE(0, scales[1]),
1591 A6XX_GRAS_CL_VPORT_ZOFFSET(0, offsets[2]),
1592 A6XX_GRAS_CL_VPORT_ZSCALE(0, scales[2]));
1593
1594 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(0), 2);
1595 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(min.x) |
1596 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(min.y));
1597 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(max.x - 1) |
1598 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(max.y - 1));
1599
1600 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1601 tu_cs_emit(cs,
1602 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1603 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1604
1605 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1606 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1607
1608 tu_cs_emit_regs(cs,
1609 A6XX_GRAS_CL_Z_CLAMP_MIN(0, z_clamp_min),
1610 A6XX_GRAS_CL_Z_CLAMP_MAX(0, z_clamp_max));
1611
1612 tu_cs_emit_regs(cs,
1613 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1614 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1615 }
1616
1617 void
1618 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1619 {
1620 VkOffset2D min = scissor->offset;
1621 VkOffset2D max = {
1622 scissor->offset.x + scissor->extent.width,
1623 scissor->offset.y + scissor->extent.height,
1624 };
1625
1626 /* special case for empty scissor with max == 0 to avoid overflow */
1627 if (max.x == 0)
1628 min.x = max.x = 1;
1629 if (max.y == 0)
1630 min.y = max.y = 1;
1631
1632 /* avoid overflow with large scissor
1633 * note the max will be limited to min - 1, so that empty scissor works
1634 */
1635 uint32_t scissor_max = BITFIELD_MASK(15);
1636 min.x = MIN2(scissor_max, min.x);
1637 min.y = MIN2(scissor_max, min.y);
1638 max.x = MIN2(scissor_max, max.x);
1639 max.y = MIN2(scissor_max, max.y);
1640
1641 tu_cs_emit_regs(cs,
1642 A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0, .x = min.x, .y = min.y),
1643 A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0, .x = max.x - 1, .y = max.y - 1));
1644 }
1645
1646 void
1647 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1648 {
1649 if (!samp_loc) {
1650 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1651 tu_cs_emit(cs, 0);
1652
1653 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1654 tu_cs_emit(cs, 0);
1655
1656 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1657 tu_cs_emit(cs, 0);
1658 return;
1659 }
1660
1661 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1662 assert(samp_loc->sampleLocationGridSize.width == 1);
1663 assert(samp_loc->sampleLocationGridSize.height == 1);
1664
1665 uint32_t sample_config =
1666 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1667 uint32_t sample_locations = 0;
1668 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1669 sample_locations |=
1670 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1671 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1672 }
1673
1674 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1675 tu_cs_emit(cs, sample_config);
1676 tu_cs_emit(cs, sample_locations);
1677
1678 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1679 tu_cs_emit(cs, sample_config);
1680 tu_cs_emit(cs, sample_locations);
1681
1682 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1683 tu_cs_emit(cs, sample_config);
1684 tu_cs_emit(cs, sample_locations);
1685 }
1686
1687 static uint32_t
1688 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1689 VkSampleCountFlagBits samples,
1690 bool multiview)
1691 {
1692 uint32_t gras_su_cntl = 0;
1693
1694 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1695 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1696 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1697 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1698
1699 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1700 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1701
1702 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1703
1704 if (rast_info->depthBiasEnable)
1705 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1706
1707 if (samples > VK_SAMPLE_COUNT_1_BIT)
1708 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1709
1710 if (multiview) {
1711 gras_su_cntl |=
1712 A6XX_GRAS_SU_CNTL_UNK17 |
1713 A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE;
1714 }
1715
1716 return gras_su_cntl;
1717 }
1718
1719 void
1720 tu6_emit_depth_bias(struct tu_cs *cs,
1721 float constant_factor,
1722 float clamp,
1723 float slope_factor)
1724 {
1725 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1726 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1727 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1728 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1729 }
1730
1731 static void
1732 tu6_emit_depth_control(struct tu_cs *cs,
1733 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1734 const VkPipelineRasterizationStateCreateInfo *rast_info)
1735 {
1736 uint32_t rb_depth_cntl = 0;
1737 if (ds_info->depthTestEnable) {
1738 rb_depth_cntl |=
1739 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1740 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1741 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
1742
1743 if (rast_info->depthClampEnable)
1744 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1745
1746 if (ds_info->depthWriteEnable)
1747 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1748 }
1749
1750 if (ds_info->depthBoundsTestEnable)
1751 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1752
1753 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1754 tu_cs_emit(cs, rb_depth_cntl);
1755 }
1756
1757 static void
1758 tu6_emit_stencil_control(struct tu_cs *cs,
1759 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1760 {
1761 uint32_t rb_stencil_control = 0;
1762 if (ds_info->stencilTestEnable) {
1763 const VkStencilOpState *front = &ds_info->front;
1764 const VkStencilOpState *back = &ds_info->back;
1765 rb_stencil_control |=
1766 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1767 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1768 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1769 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1770 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1771 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1772 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1773 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1774 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1775 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1776 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1777 }
1778
1779 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1780 tu_cs_emit(cs, rb_stencil_control);
1781 }
1782
1783 static uint32_t
1784 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1785 bool has_alpha)
1786 {
1787 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1788 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1789 has_alpha ? att->srcColorBlendFactor
1790 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1791 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1792 has_alpha ? att->dstColorBlendFactor
1793 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1794 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1795 const enum adreno_rb_blend_factor src_alpha_factor =
1796 tu6_blend_factor(att->srcAlphaBlendFactor);
1797 const enum adreno_rb_blend_factor dst_alpha_factor =
1798 tu6_blend_factor(att->dstAlphaBlendFactor);
1799
1800 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1801 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1802 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1803 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1804 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1805 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1806 }
1807
1808 static uint32_t
1809 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1810 uint32_t rb_mrt_control_rop,
1811 bool is_int,
1812 bool has_alpha)
1813 {
1814 uint32_t rb_mrt_control =
1815 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1816
1817 /* ignore blending and logic op for integer attachments */
1818 if (is_int) {
1819 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1820 return rb_mrt_control;
1821 }
1822
1823 rb_mrt_control |= rb_mrt_control_rop;
1824
1825 if (att->blendEnable) {
1826 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1827
1828 if (has_alpha)
1829 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1830 }
1831
1832 return rb_mrt_control;
1833 }
1834
1835 static void
1836 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1837 const VkPipelineColorBlendStateCreateInfo *blend_info,
1838 const VkFormat attachment_formats[MAX_RTS],
1839 uint32_t *blend_enable_mask)
1840 {
1841 *blend_enable_mask = 0;
1842
1843 bool rop_reads_dst = false;
1844 uint32_t rb_mrt_control_rop = 0;
1845 if (blend_info->logicOpEnable) {
1846 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1847 rb_mrt_control_rop =
1848 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1849 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1850 }
1851
1852 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1853 const VkPipelineColorBlendAttachmentState *att =
1854 &blend_info->pAttachments[i];
1855 const VkFormat format = attachment_formats[i];
1856
1857 uint32_t rb_mrt_control = 0;
1858 uint32_t rb_mrt_blend_control = 0;
1859 if (format != VK_FORMAT_UNDEFINED) {
1860 const bool is_int = vk_format_is_int(format);
1861 const bool has_alpha = vk_format_has_alpha(format);
1862
1863 rb_mrt_control =
1864 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1865 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1866
1867 if (att->blendEnable || rop_reads_dst)
1868 *blend_enable_mask |= 1 << i;
1869 }
1870
1871 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1872 tu_cs_emit(cs, rb_mrt_control);
1873 tu_cs_emit(cs, rb_mrt_blend_control);
1874 }
1875 }
1876
1877 static void
1878 tu6_emit_blend_control(struct tu_cs *cs,
1879 uint32_t blend_enable_mask,
1880 bool dual_src_blend,
1881 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1882 {
1883 const uint32_t sample_mask =
1884 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1885 : ((1 << msaa_info->rasterizationSamples) - 1);
1886
1887 tu_cs_emit_regs(cs,
1888 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1889 .dual_color_in_enable = dual_src_blend,
1890 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1891 .unk8 = true));
1892
1893 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1894 tu_cs_emit_regs(cs,
1895 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1896 .independent_blend = true,
1897 .sample_mask = sample_mask,
1898 .dual_color_in_enable = dual_src_blend,
1899 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1900 .alpha_to_one = msaa_info->alphaToOneEnable));
1901 }
1902
1903 static VkResult
1904 tu_pipeline_allocate_cs(struct tu_device *dev,
1905 struct tu_pipeline *pipeline,
1906 struct tu_pipeline_builder *builder,
1907 struct ir3_shader_variant *compute)
1908 {
1909 uint32_t size = 2048 + tu6_load_state_size(pipeline, compute);
1910
1911 /* graphics case: */
1912 if (builder) {
1913 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1914 if (builder->variants[i])
1915 size += builder->variants[i]->info.sizedwords;
1916 }
1917
1918 size += builder->binning_variant->info.sizedwords;
1919 } else {
1920 size += compute->info.sizedwords;
1921 }
1922
1923 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, size);
1924
1925 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1926 * that LOAD_STATE can potentially take up a large amount of space so we
1927 * calculate its size explicitly.
1928 */
1929 return tu_cs_reserve_space(&pipeline->cs, size);
1930 }
1931
1932 static void
1933 tu_pipeline_shader_key_init(struct ir3_shader_key *key,
1934 const VkGraphicsPipelineCreateInfo *pipeline_info)
1935 {
1936 for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
1937 if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
1938 key->has_gs = true;
1939 break;
1940 }
1941 }
1942
1943 if (pipeline_info->pRasterizationState->rasterizerDiscardEnable)
1944 return;
1945
1946 const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
1947 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
1948 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1949 if (msaa_info->rasterizationSamples > 1 ||
1950 /* also set msaa key when sample location is not the default
1951 * since this affects varying interpolation */
1952 (sample_locations && sample_locations->sampleLocationsEnable)) {
1953 key->msaa = true;
1954 }
1955
1956 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1957 if (msaa_info->sampleShadingEnable)
1958 key->sample_shading = true;
1959
1960 /* We set this after we compile to NIR because we need the prim mode */
1961 key->tessellation = IR3_TESS_NONE;
1962 }
1963
1964 static uint32_t
1965 tu6_get_tessmode(struct tu_shader* shader)
1966 {
1967 uint32_t primitive_mode = shader->ir3_shader->nir->info.tess.primitive_mode;
1968 switch (primitive_mode) {
1969 case GL_ISOLINES:
1970 return IR3_TESS_ISOLINES;
1971 case GL_TRIANGLES:
1972 return IR3_TESS_TRIANGLES;
1973 case GL_QUADS:
1974 return IR3_TESS_QUADS;
1975 case GL_NONE:
1976 return IR3_TESS_NONE;
1977 default:
1978 unreachable("bad tessmode");
1979 }
1980 }
1981
1982 static uint64_t
1983 tu_upload_variant(struct tu_pipeline *pipeline,
1984 const struct ir3_shader_variant *variant)
1985 {
1986 struct tu_cs_memory memory;
1987
1988 if (!variant)
1989 return 0;
1990
1991 /* this expects to get enough alignment because shaders are allocated first
1992 * and sizedwords is always aligned correctly
1993 * note: an assert in tu6_emit_xs_config validates the alignment
1994 */
1995 tu_cs_alloc(&pipeline->cs, variant->info.sizedwords, 1, &memory);
1996
1997 memcpy(memory.map, variant->bin, sizeof(uint32_t) * variant->info.sizedwords);
1998 return memory.iova;
1999 }
2000
2001 static VkResult
2002 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
2003 struct tu_pipeline *pipeline)
2004 {
2005 const struct ir3_compiler *compiler = builder->device->compiler;
2006 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
2007 NULL
2008 };
2009 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
2010 gl_shader_stage stage =
2011 vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage);
2012 stage_infos[stage] = &builder->create_info->pStages[i];
2013 }
2014
2015 struct ir3_shader_key key = {};
2016 tu_pipeline_shader_key_init(&key, builder->create_info);
2017
2018 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2019 stage < MESA_SHADER_STAGES; stage++) {
2020 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
2021 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
2022 continue;
2023
2024 struct tu_shader *shader =
2025 tu_shader_create(builder->device, stage, stage_info, builder->multiview_mask,
2026 builder->layout, builder->alloc);
2027 if (!shader)
2028 return VK_ERROR_OUT_OF_HOST_MEMORY;
2029
2030 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
2031 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
2032 * the mode is specified in the tessellation control shader. */
2033 if ((stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_TESS_CTRL) &&
2034 key.tessellation == IR3_TESS_NONE) {
2035 key.tessellation = tu6_get_tessmode(shader);
2036 }
2037
2038 builder->shaders[stage] = shader;
2039 }
2040
2041 struct tu_shader *gs = builder->shaders[MESA_SHADER_GEOMETRY];
2042 key.layer_zero =
2043 !gs || !(gs->ir3_shader->nir->info.outputs_written & VARYING_SLOT_LAYER);
2044
2045 pipeline->tess.patch_type = key.tessellation;
2046
2047 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2048 stage < MESA_SHADER_STAGES; stage++) {
2049 if (!builder->shaders[stage])
2050 continue;
2051
2052 bool created;
2053 builder->variants[stage] =
2054 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2055 &key, false, &created);
2056 if (!builder->variants[stage])
2057 return VK_ERROR_OUT_OF_HOST_MEMORY;
2058 }
2059
2060 uint32_t safe_constlens = ir3_trim_constlen(builder->variants, compiler);
2061
2062 key.safe_constlen = true;
2063
2064 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2065 stage < MESA_SHADER_STAGES; stage++) {
2066 if (!builder->shaders[stage])
2067 continue;
2068
2069 if (safe_constlens & (1 << stage)) {
2070 bool created;
2071 builder->variants[stage] =
2072 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2073 &key, false, &created);
2074 if (!builder->variants[stage])
2075 return VK_ERROR_OUT_OF_HOST_MEMORY;
2076 }
2077 }
2078
2079 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2080 struct ir3_shader_variant *variant;
2081
2082 if (vs->ir3_shader->stream_output.num_outputs ||
2083 !ir3_has_binning_vs(&key)) {
2084 variant = builder->variants[MESA_SHADER_VERTEX];
2085 } else {
2086 bool created;
2087 key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX));
2088 variant = ir3_shader_get_variant(vs->ir3_shader, &key,
2089 true, &created);
2090 if (!variant)
2091 return VK_ERROR_OUT_OF_HOST_MEMORY;
2092 }
2093
2094 builder->binning_variant = variant;
2095
2096 return VK_SUCCESS;
2097 }
2098
2099 static void
2100 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2101 struct tu_pipeline *pipeline)
2102 {
2103 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2104 builder->create_info->pDynamicState;
2105
2106 if (!dynamic_info)
2107 return;
2108
2109 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2110 VkDynamicState state = dynamic_info->pDynamicStates[i];
2111 switch (state) {
2112 case VK_DYNAMIC_STATE_VIEWPORT ... VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2113 pipeline->dynamic_state_mask |= BIT(state);
2114 break;
2115 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
2116 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS);
2117 break;
2118 default:
2119 assert(!"unsupported dynamic state");
2120 break;
2121 }
2122 }
2123 }
2124
2125 static void
2126 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2127 struct tu_shader *shader,
2128 struct ir3_shader_variant *v)
2129 {
2130 link->const_state = *ir3_const_state(v);
2131 link->constlen = v->constlen;
2132 link->push_consts = shader->push_consts;
2133 }
2134
2135 static void
2136 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2137 struct tu_pipeline *pipeline)
2138 {
2139 struct tu_cs prog_cs;
2140 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2141 tu6_emit_program(&prog_cs, builder, false);
2142 pipeline->program.state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2143
2144 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2145 tu6_emit_program(&prog_cs, builder, true);
2146 pipeline->program.binning_state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2147
2148 VkShaderStageFlags stages = 0;
2149 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2150 stages |= builder->create_info->pStages[i].stage;
2151 }
2152 pipeline->active_stages = stages;
2153
2154 uint32_t desc_sets = 0;
2155 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2156 if (!builder->shaders[i])
2157 continue;
2158
2159 tu_pipeline_set_linkage(&pipeline->program.link[i],
2160 builder->shaders[i],
2161 builder->variants[i]);
2162 desc_sets |= builder->shaders[i]->active_desc_sets;
2163 }
2164 pipeline->active_desc_sets = desc_sets;
2165 }
2166
2167 static void
2168 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2169 struct tu_pipeline *pipeline)
2170 {
2171 const VkPipelineVertexInputStateCreateInfo *vi_info =
2172 builder->create_info->pVertexInputState;
2173 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
2174 const struct ir3_shader_variant *bs = builder->binning_variant;
2175
2176 struct tu_cs vi_cs;
2177 tu_cs_begin_sub_stream(&pipeline->cs,
2178 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2179 tu6_emit_vertex_input(&vi_cs, vs, vi_info,
2180 &pipeline->vi.bindings_used);
2181 pipeline->vi.state = tu_cs_end_draw_state(&pipeline->cs, &vi_cs);
2182
2183 if (bs) {
2184 tu_cs_begin_sub_stream(&pipeline->cs,
2185 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2186 tu6_emit_vertex_input(
2187 &vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
2188 pipeline->vi.binning_state =
2189 tu_cs_end_draw_state(&pipeline->cs, &vi_cs);
2190 }
2191 }
2192
2193 static void
2194 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2195 struct tu_pipeline *pipeline)
2196 {
2197 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2198 builder->create_info->pInputAssemblyState;
2199
2200 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2201 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2202 }
2203
2204 static bool
2205 tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs,
2206 uint32_t id, uint32_t size)
2207 {
2208 assert(id < ARRAY_SIZE(pipeline->dynamic_state));
2209
2210 if (pipeline->dynamic_state_mask & BIT(id))
2211 return false;
2212
2213 pipeline->dynamic_state[id] = tu_cs_draw_state(&pipeline->cs, cs, size);
2214 return true;
2215 }
2216
2217 static void
2218 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder,
2219 struct tu_pipeline *pipeline)
2220 {
2221 const VkPipelineTessellationStateCreateInfo *tess_info =
2222 builder->create_info->pTessellationState;
2223
2224 if (!tess_info)
2225 return;
2226
2227 assert(pipeline->ia.primtype == DI_PT_PATCHES0);
2228 assert(tess_info->patchControlPoints <= 32);
2229 pipeline->ia.primtype += tess_info->patchControlPoints;
2230 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info =
2231 vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2232 pipeline->tess.upper_left_domain_origin = !domain_info ||
2233 domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
2234 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
2235 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
2236 pipeline->tess.param_stride = hs->output_size * 4;
2237 pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1;
2238 pipeline->tess.ds_bo_regid = ds->const_state->offsets.primitive_param + 1;
2239 }
2240
2241 static void
2242 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2243 struct tu_pipeline *pipeline)
2244 {
2245 /* The spec says:
2246 *
2247 * pViewportState is a pointer to an instance of the
2248 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2249 * pipeline has rasterization disabled."
2250 *
2251 * We leave the relevant registers stale in that case.
2252 */
2253 if (builder->rasterizer_discard)
2254 return;
2255
2256 const VkPipelineViewportStateCreateInfo *vp_info =
2257 builder->create_info->pViewportState;
2258
2259 struct tu_cs cs;
2260
2261 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_VIEWPORT, 18))
2262 tu6_emit_viewport(&cs, vp_info->pViewports);
2263
2264 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_SCISSOR, 3))
2265 tu6_emit_scissor(&cs, vp_info->pScissors);
2266 }
2267
2268 static void
2269 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2270 struct tu_pipeline *pipeline)
2271 {
2272 const VkPipelineRasterizationStateCreateInfo *rast_info =
2273 builder->create_info->pRasterizationState;
2274
2275 enum a6xx_polygon_mode mode = tu6_polygon_mode(rast_info->polygonMode);
2276
2277 bool depth_clip_disable = rast_info->depthClampEnable;
2278
2279 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
2280 vk_find_struct_const(rast_info, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
2281 if (depth_clip_state)
2282 depth_clip_disable = !depth_clip_state->depthClipEnable;
2283
2284 struct tu_cs cs;
2285 pipeline->rast_state = tu_cs_draw_state(&pipeline->cs, &cs, 9);
2286
2287 tu_cs_emit_regs(&cs,
2288 A6XX_GRAS_CL_CNTL(
2289 .znear_clip_disable = depth_clip_disable,
2290 .zfar_clip_disable = depth_clip_disable,
2291 /* TODO should this be depth_clip_disable instead? */
2292 .unk5 = rast_info->depthClampEnable,
2293 .zero_gb_scale_z = 1,
2294 .vp_clip_code_ignore = 1));
2295
2296 tu_cs_emit_regs(&cs,
2297 A6XX_VPC_POLYGON_MODE(mode));
2298
2299 tu_cs_emit_regs(&cs,
2300 A6XX_PC_POLYGON_MODE(mode));
2301
2302 /* move to hw ctx init? */
2303 tu_cs_emit_regs(&cs,
2304 A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
2305 A6XX_GRAS_SU_POINT_SIZE(1.0f));
2306
2307 pipeline->gras_su_cntl =
2308 tu6_gras_su_cntl(rast_info, builder->samples, builder->multiview_mask != 0);
2309
2310 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_LINE_WIDTH, 2)) {
2311 pipeline->gras_su_cntl |=
2312 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info->lineWidth / 2.0f);
2313 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = pipeline->gras_su_cntl));
2314 }
2315
2316 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BIAS, 4)) {
2317 tu6_emit_depth_bias(&cs, rast_info->depthBiasConstantFactor,
2318 rast_info->depthBiasClamp,
2319 rast_info->depthBiasSlopeFactor);
2320 }
2321
2322 }
2323
2324 static void
2325 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2326 struct tu_pipeline *pipeline)
2327 {
2328 /* The spec says:
2329 *
2330 * pDepthStencilState is a pointer to an instance of the
2331 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2332 * the pipeline has rasterization disabled or if the subpass of the
2333 * render pass the pipeline is created against does not use a
2334 * depth/stencil attachment.
2335 *
2336 * Disable both depth and stencil tests if there is no ds attachment,
2337 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2338 * only the separate stencil attachment
2339 */
2340 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2341 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2342 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2343 ? builder->create_info->pDepthStencilState
2344 : &dummy_ds_info;
2345 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2346 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2347 ? ds_info : &dummy_ds_info;
2348
2349 struct tu_cs cs;
2350 pipeline->ds_state = tu_cs_draw_state(&pipeline->cs, &cs, 6);
2351
2352 /* move to hw ctx init? */
2353 tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
2354 tu6_emit_depth_control(&cs, ds_info_depth,
2355 builder->create_info->pRasterizationState);
2356 tu6_emit_stencil_control(&cs, ds_info);
2357
2358 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
2359 tu_cs_emit_regs(&cs,
2360 A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
2361 A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
2362 }
2363
2364 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
2365 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
2366 .bfmask = ds_info->back.compareMask & 0xff));
2367 }
2368
2369 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2)) {
2370 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.wrmask = ds_info->front.writeMask & 0xff,
2371 .bfwrmask = ds_info->back.writeMask & 0xff));
2372 }
2373
2374 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2)) {
2375 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.ref = ds_info->front.reference & 0xff,
2376 .bfref = ds_info->back.reference & 0xff));
2377 }
2378 }
2379
2380 static void
2381 tu_pipeline_builder_parse_multisample_and_color_blend(
2382 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2383 {
2384 /* The spec says:
2385 *
2386 * pMultisampleState is a pointer to an instance of the
2387 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2388 * has rasterization disabled.
2389 *
2390 * Also,
2391 *
2392 * pColorBlendState is a pointer to an instance of the
2393 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2394 * pipeline has rasterization disabled or if the subpass of the render
2395 * pass the pipeline is created against does not use any color
2396 * attachments.
2397 *
2398 * We leave the relevant registers stale when rasterization is disabled.
2399 */
2400 if (builder->rasterizer_discard)
2401 return;
2402
2403 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2404 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2405 builder->create_info->pMultisampleState;
2406 const VkPipelineColorBlendStateCreateInfo *blend_info =
2407 builder->use_color_attachments ? builder->create_info->pColorBlendState
2408 : &dummy_blend_info;
2409
2410 struct tu_cs cs;
2411 pipeline->blend_state =
2412 tu_cs_draw_state(&pipeline->cs, &cs, blend_info->attachmentCount * 3 + 4);
2413
2414 uint32_t blend_enable_mask;
2415 tu6_emit_rb_mrt_controls(&cs, blend_info,
2416 builder->color_attachment_formats,
2417 &blend_enable_mask);
2418
2419 tu6_emit_blend_control(&cs, blend_enable_mask,
2420 builder->use_dual_src_blend, msaa_info);
2421
2422 assert(cs.cur == cs.end); /* validate draw state size */
2423
2424 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5)) {
2425 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2426 tu_cs_emit_array(&cs, (const uint32_t *) blend_info->blendConstants, 4);
2427 }
2428
2429 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2430 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2431 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2432
2433 if (sample_locations && sample_locations->sampleLocationsEnable)
2434 samp_loc = &sample_locations->sampleLocationsInfo;
2435
2436 if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
2437 samp_loc ? 9 : 6)) {
2438 tu6_emit_sample_locations(&cs, samp_loc);
2439 }
2440 }
2441
2442 static void
2443 tu_pipeline_finish(struct tu_pipeline *pipeline,
2444 struct tu_device *dev,
2445 const VkAllocationCallbacks *alloc)
2446 {
2447 tu_cs_finish(&pipeline->cs);
2448 }
2449
2450 static VkResult
2451 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2452 struct tu_pipeline **pipeline)
2453 {
2454 VkResult result;
2455
2456 *pipeline = vk_object_zalloc(&builder->device->vk, builder->alloc,
2457 sizeof(**pipeline), VK_OBJECT_TYPE_PIPELINE);
2458 if (!*pipeline)
2459 return VK_ERROR_OUT_OF_HOST_MEMORY;
2460
2461 (*pipeline)->layout = builder->layout;
2462
2463 /* compile and upload shaders */
2464 result = tu_pipeline_builder_compile_shaders(builder, *pipeline);
2465 if (result != VK_SUCCESS) {
2466 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2467 return result;
2468 }
2469
2470 result = tu_pipeline_allocate_cs(builder->device, *pipeline, builder, NULL);
2471 if (result != VK_SUCCESS) {
2472 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2473 return result;
2474 }
2475
2476 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2477 builder->shader_iova[i] = tu_upload_variant(*pipeline, builder->variants[i]);
2478
2479 builder->binning_vs_iova =
2480 tu_upload_variant(*pipeline, builder->binning_variant);
2481
2482 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2483 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2484 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2485 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2486 tu_pipeline_builder_parse_tessellation(builder, *pipeline);
2487 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2488 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2489 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2490 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2491 tu6_emit_load_state(*pipeline, false);
2492
2493 /* we should have reserved enough space upfront such that the CS never
2494 * grows
2495 */
2496 assert((*pipeline)->cs.bo_count == 1);
2497
2498 return VK_SUCCESS;
2499 }
2500
2501 static void
2502 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2503 {
2504 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2505 if (!builder->shaders[i])
2506 continue;
2507 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2508 }
2509 }
2510
2511 static void
2512 tu_pipeline_builder_init_graphics(
2513 struct tu_pipeline_builder *builder,
2514 struct tu_device *dev,
2515 struct tu_pipeline_cache *cache,
2516 const VkGraphicsPipelineCreateInfo *create_info,
2517 const VkAllocationCallbacks *alloc)
2518 {
2519 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2520
2521 *builder = (struct tu_pipeline_builder) {
2522 .device = dev,
2523 .cache = cache,
2524 .create_info = create_info,
2525 .alloc = alloc,
2526 .layout = layout,
2527 };
2528
2529 const struct tu_render_pass *pass =
2530 tu_render_pass_from_handle(create_info->renderPass);
2531 const struct tu_subpass *subpass =
2532 &pass->subpasses[create_info->subpass];
2533
2534 builder->multiview_mask = subpass->multiview_mask;
2535
2536 builder->rasterizer_discard =
2537 create_info->pRasterizationState->rasterizerDiscardEnable;
2538
2539 if (builder->rasterizer_discard) {
2540 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2541 } else {
2542 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2543
2544 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2545 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2546 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2547
2548 assert(subpass->color_count == 0 ||
2549 !create_info->pColorBlendState ||
2550 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2551 builder->color_attachment_count = subpass->color_count;
2552 for (uint32_t i = 0; i < subpass->color_count; i++) {
2553 const uint32_t a = subpass->color_attachments[i].attachment;
2554 if (a == VK_ATTACHMENT_UNUSED)
2555 continue;
2556
2557 builder->color_attachment_formats[i] = pass->attachments[a].format;
2558 builder->use_color_attachments = true;
2559 builder->render_components |= 0xf << (i * 4);
2560 }
2561
2562 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2563 builder->color_attachment_count++;
2564 builder->use_dual_src_blend = true;
2565 /* dual source blending has an extra fs output in the 2nd slot */
2566 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2567 builder->render_components |= 0xf << 4;
2568 }
2569 }
2570 }
2571
2572 static VkResult
2573 tu_graphics_pipeline_create(VkDevice device,
2574 VkPipelineCache pipelineCache,
2575 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2576 const VkAllocationCallbacks *pAllocator,
2577 VkPipeline *pPipeline)
2578 {
2579 TU_FROM_HANDLE(tu_device, dev, device);
2580 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2581
2582 struct tu_pipeline_builder builder;
2583 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2584 pCreateInfo, pAllocator);
2585
2586 struct tu_pipeline *pipeline = NULL;
2587 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2588 tu_pipeline_builder_finish(&builder);
2589
2590 if (result == VK_SUCCESS)
2591 *pPipeline = tu_pipeline_to_handle(pipeline);
2592 else
2593 *pPipeline = VK_NULL_HANDLE;
2594
2595 return result;
2596 }
2597
2598 VkResult
2599 tu_CreateGraphicsPipelines(VkDevice device,
2600 VkPipelineCache pipelineCache,
2601 uint32_t count,
2602 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2603 const VkAllocationCallbacks *pAllocator,
2604 VkPipeline *pPipelines)
2605 {
2606 VkResult final_result = VK_SUCCESS;
2607
2608 for (uint32_t i = 0; i < count; i++) {
2609 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2610 &pCreateInfos[i], pAllocator,
2611 &pPipelines[i]);
2612
2613 if (result != VK_SUCCESS)
2614 final_result = result;
2615 }
2616
2617 return final_result;
2618 }
2619
2620 static VkResult
2621 tu_compute_pipeline_create(VkDevice device,
2622 VkPipelineCache _cache,
2623 const VkComputePipelineCreateInfo *pCreateInfo,
2624 const VkAllocationCallbacks *pAllocator,
2625 VkPipeline *pPipeline)
2626 {
2627 TU_FROM_HANDLE(tu_device, dev, device);
2628 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2629 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2630 VkResult result;
2631
2632 struct tu_pipeline *pipeline;
2633
2634 *pPipeline = VK_NULL_HANDLE;
2635
2636 pipeline = vk_object_zalloc(&dev->vk, pAllocator, sizeof(*pipeline),
2637 VK_OBJECT_TYPE_PIPELINE);
2638 if (!pipeline)
2639 return VK_ERROR_OUT_OF_HOST_MEMORY;
2640
2641 pipeline->layout = layout;
2642
2643 struct ir3_shader_key key = {};
2644
2645 struct tu_shader *shader =
2646 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, 0, layout, pAllocator);
2647 if (!shader) {
2648 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2649 goto fail;
2650 }
2651
2652 pipeline->active_desc_sets = shader->active_desc_sets;
2653
2654 bool created;
2655 struct ir3_shader_variant *v =
2656 ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
2657 if (!v) {
2658 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2659 goto fail;
2660 }
2661
2662 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2663 shader, v);
2664
2665 result = tu_pipeline_allocate_cs(dev, pipeline, NULL, v);
2666 if (result != VK_SUCCESS)
2667 goto fail;
2668
2669 uint64_t shader_iova = tu_upload_variant(pipeline, v);
2670
2671 for (int i = 0; i < 3; i++)
2672 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2673
2674 struct tu_cs prog_cs;
2675 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2676 tu6_emit_cs_config(&prog_cs, shader, v, shader_iova);
2677 pipeline->program.state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2678
2679 tu6_emit_load_state(pipeline, true);
2680
2681 *pPipeline = tu_pipeline_to_handle(pipeline);
2682 return VK_SUCCESS;
2683
2684 fail:
2685 if (shader)
2686 tu_shader_destroy(dev, shader, pAllocator);
2687
2688 vk_object_free(&dev->vk, pAllocator, pipeline);
2689
2690 return result;
2691 }
2692
2693 VkResult
2694 tu_CreateComputePipelines(VkDevice device,
2695 VkPipelineCache pipelineCache,
2696 uint32_t count,
2697 const VkComputePipelineCreateInfo *pCreateInfos,
2698 const VkAllocationCallbacks *pAllocator,
2699 VkPipeline *pPipelines)
2700 {
2701 VkResult final_result = VK_SUCCESS;
2702
2703 for (uint32_t i = 0; i < count; i++) {
2704 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2705 &pCreateInfos[i],
2706 pAllocator, &pPipelines[i]);
2707 if (result != VK_SUCCESS)
2708 final_result = result;
2709 }
2710
2711 return final_result;
2712 }
2713
2714 void
2715 tu_DestroyPipeline(VkDevice _device,
2716 VkPipeline _pipeline,
2717 const VkAllocationCallbacks *pAllocator)
2718 {
2719 TU_FROM_HANDLE(tu_device, dev, _device);
2720 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2721
2722 if (!_pipeline)
2723 return;
2724
2725 tu_pipeline_finish(pipeline, dev, pAllocator);
2726 vk_object_free(&dev->vk, pAllocator, pipeline);
2727 }