projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
tu: Align GMEM resolve blit scissor
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static inline uint32_t
46 tu6_vkstage2opcode(VkShaderStageFlags stage)
47 {
48 switch (stage) {
49 case VK_SHADER_STAGE_VERTEX_BIT:
50 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
51 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
52 case VK_SHADER_STAGE_GEOMETRY_BIT:
53 return CP_LOAD_STATE6_GEOM;
54 case VK_SHADER_STAGE_FRAGMENT_BIT:
55 case VK_SHADER_STAGE_COMPUTE_BIT:
56 return CP_LOAD_STATE6_FRAG;
57 default:
58 unreachable("bad shader type");
59 }
60 }
61
62 static enum a6xx_state_block
63 tu6_tex_stage2sb(VkShaderStageFlags stage)
64 {
65 switch (stage) {
66 case VK_SHADER_STAGE_VERTEX_BIT:
67 return SB6_VS_TEX;
68 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
69 return SB6_HS_TEX;
70 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
71 return SB6_DS_TEX;
72 case VK_SHADER_STAGE_GEOMETRY_BIT:
73 return SB6_GS_TEX;
74 case VK_SHADER_STAGE_FRAGMENT_BIT:
75 return SB6_FS_TEX;
76 case VK_SHADER_STAGE_COMPUTE_BIT:
77 return SB6_CS_TEX;
78 default:
79 unreachable("bad shader stage");
80 }
81 }
82
83 static enum a6xx_state_block
84 tu6_ubo_stage2sb(VkShaderStageFlags stage)
85 {
86 switch (stage) {
87 case VK_SHADER_STAGE_VERTEX_BIT:
88 return SB6_VS_SHADER;
89 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
90 return SB6_HS_SHADER;
91 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
92 return SB6_DS_SHADER;
93 case VK_SHADER_STAGE_GEOMETRY_BIT:
94 return SB6_GS_SHADER;
95 case VK_SHADER_STAGE_FRAGMENT_BIT:
96 return SB6_FS_SHADER;
97 case VK_SHADER_STAGE_COMPUTE_BIT:
98 return SB6_CS_SHADER;
99 default:
100 unreachable("bad shader stage");
101 }
102 }
103
104 static void
105 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
106 enum a6xx_state_block sb, unsigned base, unsigned offset,
107 unsigned count)
108 {
109 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
110 * clear if emitting more packets will even help anything. Presumably the
111 * descriptor cache is relatively small, and these packets stop doing
112 * anything when there are too many descriptors.
113 */
114 tu_cs_emit_pkt7(cs, opcode, 3);
115 tu_cs_emit(cs,
116 CP_LOAD_STATE6_0_STATE_TYPE(st) |
117 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
118 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
119 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
120 tu_cs_emit_qw(cs, offset | (base << 28));
121 }
122
123 static unsigned
124 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
125 {
126 const unsigned load_state_size = 4;
127 unsigned size = 0;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
130 for (unsigned j = 0; j < set_layout->binding_count; j++) {
131 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
132 unsigned count = 0;
133 /* Note: some users, like amber for example, pass in
134 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
135 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
136 */
137 VkShaderStageFlags stages = compute ?
138 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
139 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
140 unsigned stage_count = util_bitcount(stages);
141 switch (binding->type) {
142 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
143 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
144 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
145 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
146 /* IBO-backed resources only need one packet for all graphics stages */
147 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
148 count += 1;
149 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
150 count += 1;
151 break;
152 case VK_DESCRIPTOR_TYPE_SAMPLER:
153 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
154 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
155 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
156 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
157 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
158 /* Textures and UBO's needs a packet for each stage */
159 count = stage_count;
160 break;
161 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
162 /* Because of how we pack combined images and samplers, we
163 * currently can't use one packet for the whole array.
164 */
165 count = stage_count * binding->array_size * 2;
166 break;
167 default:
168 unreachable("bad descriptor type");
169 }
170 size += count * load_state_size;
171 }
172 }
173 return size;
174 }
175
176 static void
177 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
178 {
179 unsigned size = tu6_load_state_size(pipeline->layout, compute);
180 if (size == 0)
181 return;
182
183 struct tu_cs cs;
184 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
185
186 struct tu_pipeline_layout *layout = pipeline->layout;
187 for (unsigned i = 0; i < layout->num_sets; i++) {
188 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
189 for (unsigned j = 0; j < set_layout->binding_count; j++) {
190 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
191 unsigned base = i;
192 unsigned offset = binding->offset / 4;
193 /* Note: some users, like amber for example, pass in
194 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
195 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
196 */
197 VkShaderStageFlags stages = compute ?
198 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
199 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
200 unsigned count = binding->array_size;
201 if (count == 0 || stages == 0)
202 continue;
203 switch (binding->type) {
204 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
205 base = MAX_SETS;
206 offset = (layout->input_attachment_count +
207 layout->set[i].dynamic_offset_start +
208 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
209 /* fallthrough */
210 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
211 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
212 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
213 /* IBO-backed resources only need one packet for all graphics stages */
214 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
215 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
216 base, offset, count);
217 }
218 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
219 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
220 base, offset, count);
221 }
222 break;
223 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
224 base = MAX_SETS;
225 offset = (layout->set[i].input_attachment_start +
226 binding->input_attachment_offset) * A6XX_TEX_CONST_DWORDS;
227 case VK_DESCRIPTOR_TYPE_SAMPLER:
228 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
229 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
230 unsigned stage_log2;
231 for_each_bit(stage_log2, stages) {
232 VkShaderStageFlags stage = 1 << stage_log2;
233 emit_load_state(&cs, tu6_vkstage2opcode(stage),
234 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
235 ST6_SHADER : ST6_CONSTANTS,
236 tu6_tex_stage2sb(stage), base, offset, count);
237 }
238 break;
239 }
240 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
241 base = MAX_SETS;
242 offset = (layout->input_attachment_count +
243 layout->set[i].dynamic_offset_start +
244 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
245 /* fallthrough */
246 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
247 unsigned stage_log2;
248 for_each_bit(stage_log2, stages) {
249 VkShaderStageFlags stage = 1 << stage_log2;
250 emit_load_state(&cs, tu6_vkstage2opcode(stage), ST6_UBO,
251 tu6_ubo_stage2sb(stage), base, offset, count);
252 }
253 break;
254 }
255 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
256 unsigned stage_log2;
257 for_each_bit(stage_log2, stages) {
258 VkShaderStageFlags stage = 1 << stage_log2;
259 /* TODO: We could emit less CP_LOAD_STATE6 if we used
260 * struct-of-arrays instead of array-of-structs.
261 */
262 for (unsigned i = 0; i < count; i++) {
263 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
264 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
265 emit_load_state(&cs, tu6_vkstage2opcode(stage),
266 ST6_CONSTANTS, tu6_tex_stage2sb(stage),
267 base, tex_offset, 1);
268 emit_load_state(&cs, tu6_vkstage2opcode(stage),
269 ST6_SHADER, tu6_tex_stage2sb(stage),
270 base, sam_offset, 1);
271 }
272 }
273 break;
274 }
275 default:
276 unreachable("bad descriptor type");
277 }
278 }
279 }
280
281 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
282 }
283
284 struct tu_pipeline_builder
285 {
286 struct tu_device *device;
287 struct tu_pipeline_cache *cache;
288 struct tu_pipeline_layout *layout;
289 const VkAllocationCallbacks *alloc;
290 const VkGraphicsPipelineCreateInfo *create_info;
291
292 struct tu_shader *shaders[MESA_SHADER_STAGES];
293 uint32_t shader_offsets[MESA_SHADER_STAGES];
294 uint32_t binning_vs_offset;
295 uint32_t shader_total_size;
296
297 bool rasterizer_discard;
298 /* these states are affectd by rasterizer_discard */
299 VkSampleCountFlagBits samples;
300 bool use_depth_stencil_attachment;
301 bool use_color_attachments;
302 uint32_t color_attachment_count;
303 VkFormat color_attachment_formats[MAX_RTS];
304 };
305
306 static enum tu_dynamic_state_bits
307 tu_dynamic_state_bit(VkDynamicState state)
308 {
309 switch (state) {
310 case VK_DYNAMIC_STATE_VIEWPORT:
311 return TU_DYNAMIC_VIEWPORT;
312 case VK_DYNAMIC_STATE_SCISSOR:
313 return TU_DYNAMIC_SCISSOR;
314 case VK_DYNAMIC_STATE_LINE_WIDTH:
315 return TU_DYNAMIC_LINE_WIDTH;
316 case VK_DYNAMIC_STATE_DEPTH_BIAS:
317 return TU_DYNAMIC_DEPTH_BIAS;
318 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
319 return TU_DYNAMIC_BLEND_CONSTANTS;
320 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
321 return TU_DYNAMIC_DEPTH_BOUNDS;
322 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
323 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
324 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
325 return TU_DYNAMIC_STENCIL_WRITE_MASK;
326 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
327 return TU_DYNAMIC_STENCIL_REFERENCE;
328 default:
329 unreachable("invalid dynamic state");
330 return 0;
331 }
332 }
333
334 static gl_shader_stage
335 tu_shader_stage(VkShaderStageFlagBits stage)
336 {
337 switch (stage) {
338 case VK_SHADER_STAGE_VERTEX_BIT:
339 return MESA_SHADER_VERTEX;
340 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
341 return MESA_SHADER_TESS_CTRL;
342 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
343 return MESA_SHADER_TESS_EVAL;
344 case VK_SHADER_STAGE_GEOMETRY_BIT:
345 return MESA_SHADER_GEOMETRY;
346 case VK_SHADER_STAGE_FRAGMENT_BIT:
347 return MESA_SHADER_FRAGMENT;
348 case VK_SHADER_STAGE_COMPUTE_BIT:
349 return MESA_SHADER_COMPUTE;
350 default:
351 unreachable("invalid VkShaderStageFlagBits");
352 return MESA_SHADER_NONE;
353 }
354 }
355
356 static bool
357 tu_logic_op_reads_dst(VkLogicOp op)
358 {
359 switch (op) {
360 case VK_LOGIC_OP_CLEAR:
361 case VK_LOGIC_OP_COPY:
362 case VK_LOGIC_OP_COPY_INVERTED:
363 case VK_LOGIC_OP_SET:
364 return false;
365 default:
366 return true;
367 }
368 }
369
370 static VkBlendFactor
371 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
372 {
373 /* treat dst alpha as 1.0 and avoid reading it */
374 switch (factor) {
375 case VK_BLEND_FACTOR_DST_ALPHA:
376 return VK_BLEND_FACTOR_ONE;
377 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
378 return VK_BLEND_FACTOR_ZERO;
379 default:
380 return factor;
381 }
382 }
383
384 static enum pc_di_primtype
385 tu6_primtype(VkPrimitiveTopology topology)
386 {
387 switch (topology) {
388 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
389 return DI_PT_POINTLIST;
390 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
391 return DI_PT_LINELIST;
392 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
393 return DI_PT_LINESTRIP;
394 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
395 return DI_PT_TRILIST;
396 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
397 return DI_PT_TRISTRIP;
398 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
399 return DI_PT_TRIFAN;
400 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
401 return DI_PT_LINE_ADJ;
402 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
403 return DI_PT_LINESTRIP_ADJ;
404 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
405 return DI_PT_TRI_ADJ;
406 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
407 return DI_PT_TRISTRIP_ADJ;
408 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
409 default:
410 unreachable("invalid primitive topology");
411 return DI_PT_NONE;
412 }
413 }
414
415 static enum adreno_compare_func
416 tu6_compare_func(VkCompareOp op)
417 {
418 switch (op) {
419 case VK_COMPARE_OP_NEVER:
420 return FUNC_NEVER;
421 case VK_COMPARE_OP_LESS:
422 return FUNC_LESS;
423 case VK_COMPARE_OP_EQUAL:
424 return FUNC_EQUAL;
425 case VK_COMPARE_OP_LESS_OR_EQUAL:
426 return FUNC_LEQUAL;
427 case VK_COMPARE_OP_GREATER:
428 return FUNC_GREATER;
429 case VK_COMPARE_OP_NOT_EQUAL:
430 return FUNC_NOTEQUAL;
431 case VK_COMPARE_OP_GREATER_OR_EQUAL:
432 return FUNC_GEQUAL;
433 case VK_COMPARE_OP_ALWAYS:
434 return FUNC_ALWAYS;
435 default:
436 unreachable("invalid VkCompareOp");
437 return FUNC_NEVER;
438 }
439 }
440
441 static enum adreno_stencil_op
442 tu6_stencil_op(VkStencilOp op)
443 {
444 switch (op) {
445 case VK_STENCIL_OP_KEEP:
446 return STENCIL_KEEP;
447 case VK_STENCIL_OP_ZERO:
448 return STENCIL_ZERO;
449 case VK_STENCIL_OP_REPLACE:
450 return STENCIL_REPLACE;
451 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
452 return STENCIL_INCR_CLAMP;
453 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
454 return STENCIL_DECR_CLAMP;
455 case VK_STENCIL_OP_INVERT:
456 return STENCIL_INVERT;
457 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
458 return STENCIL_INCR_WRAP;
459 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
460 return STENCIL_DECR_WRAP;
461 default:
462 unreachable("invalid VkStencilOp");
463 return STENCIL_KEEP;
464 }
465 }
466
467 static enum a3xx_rop_code
468 tu6_rop(VkLogicOp op)
469 {
470 switch (op) {
471 case VK_LOGIC_OP_CLEAR:
472 return ROP_CLEAR;
473 case VK_LOGIC_OP_AND:
474 return ROP_AND;
475 case VK_LOGIC_OP_AND_REVERSE:
476 return ROP_AND_REVERSE;
477 case VK_LOGIC_OP_COPY:
478 return ROP_COPY;
479 case VK_LOGIC_OP_AND_INVERTED:
480 return ROP_AND_INVERTED;
481 case VK_LOGIC_OP_NO_OP:
482 return ROP_NOOP;
483 case VK_LOGIC_OP_XOR:
484 return ROP_XOR;
485 case VK_LOGIC_OP_OR:
486 return ROP_OR;
487 case VK_LOGIC_OP_NOR:
488 return ROP_NOR;
489 case VK_LOGIC_OP_EQUIVALENT:
490 return ROP_EQUIV;
491 case VK_LOGIC_OP_INVERT:
492 return ROP_INVERT;
493 case VK_LOGIC_OP_OR_REVERSE:
494 return ROP_OR_REVERSE;
495 case VK_LOGIC_OP_COPY_INVERTED:
496 return ROP_COPY_INVERTED;
497 case VK_LOGIC_OP_OR_INVERTED:
498 return ROP_OR_INVERTED;
499 case VK_LOGIC_OP_NAND:
500 return ROP_NAND;
501 case VK_LOGIC_OP_SET:
502 return ROP_SET;
503 default:
504 unreachable("invalid VkLogicOp");
505 return ROP_NOOP;
506 }
507 }
508
509 static enum adreno_rb_blend_factor
510 tu6_blend_factor(VkBlendFactor factor)
511 {
512 switch (factor) {
513 case VK_BLEND_FACTOR_ZERO:
514 return FACTOR_ZERO;
515 case VK_BLEND_FACTOR_ONE:
516 return FACTOR_ONE;
517 case VK_BLEND_FACTOR_SRC_COLOR:
518 return FACTOR_SRC_COLOR;
519 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
520 return FACTOR_ONE_MINUS_SRC_COLOR;
521 case VK_BLEND_FACTOR_DST_COLOR:
522 return FACTOR_DST_COLOR;
523 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
524 return FACTOR_ONE_MINUS_DST_COLOR;
525 case VK_BLEND_FACTOR_SRC_ALPHA:
526 return FACTOR_SRC_ALPHA;
527 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
528 return FACTOR_ONE_MINUS_SRC_ALPHA;
529 case VK_BLEND_FACTOR_DST_ALPHA:
530 return FACTOR_DST_ALPHA;
531 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
532 return FACTOR_ONE_MINUS_DST_ALPHA;
533 case VK_BLEND_FACTOR_CONSTANT_COLOR:
534 return FACTOR_CONSTANT_COLOR;
535 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
536 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
537 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
538 return FACTOR_CONSTANT_ALPHA;
539 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
540 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
541 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
542 return FACTOR_SRC_ALPHA_SATURATE;
543 case VK_BLEND_FACTOR_SRC1_COLOR:
544 return FACTOR_SRC1_COLOR;
545 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
546 return FACTOR_ONE_MINUS_SRC1_COLOR;
547 case VK_BLEND_FACTOR_SRC1_ALPHA:
548 return FACTOR_SRC1_ALPHA;
549 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
550 return FACTOR_ONE_MINUS_SRC1_ALPHA;
551 default:
552 unreachable("invalid VkBlendFactor");
553 return FACTOR_ZERO;
554 }
555 }
556
557 static enum a3xx_rb_blend_opcode
558 tu6_blend_op(VkBlendOp op)
559 {
560 switch (op) {
561 case VK_BLEND_OP_ADD:
562 return BLEND_DST_PLUS_SRC;
563 case VK_BLEND_OP_SUBTRACT:
564 return BLEND_SRC_MINUS_DST;
565 case VK_BLEND_OP_REVERSE_SUBTRACT:
566 return BLEND_DST_MINUS_SRC;
567 case VK_BLEND_OP_MIN:
568 return BLEND_MIN_DST_SRC;
569 case VK_BLEND_OP_MAX:
570 return BLEND_MAX_DST_SRC;
571 default:
572 unreachable("invalid VkBlendOp");
573 return BLEND_DST_PLUS_SRC;
574 }
575 }
576
577 static uint32_t
578 emit_xs_config(const struct ir3_shader_variant *sh)
579 {
580 if (sh->instrlen) {
581 return A6XX_SP_VS_CONFIG_ENABLED |
582 COND(sh->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
583 COND(sh->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
584 COND(sh->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
585 COND(sh->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO);
586 } else {
587 return 0;
588 }
589 }
590
591 static void
592 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
593 const struct ir3_shader_variant *vs)
594 {
595 uint32_t sp_vs_ctrl =
596 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
597 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
598 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
599 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
600 if (vs->need_pixlod)
601 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
602 if (vs->need_fine_derivatives)
603 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_DIFF_FINE;
604
605 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
606 tu_cs_emit(cs, sp_vs_ctrl);
607
608 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
609 tu_cs_emit(cs, emit_xs_config(vs));
610 tu_cs_emit(cs, vs->instrlen);
611
612 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
613 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
614 A6XX_HLSQ_VS_CNTL_ENABLED);
615 }
616
617 static void
618 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
619 const struct ir3_shader_variant *hs)
620 {
621 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
622 tu_cs_emit(cs, 0);
623
624 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
625 tu_cs_emit(cs, emit_xs_config(hs));
626 tu_cs_emit(cs, hs->instrlen);
627
628 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
629 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
630 }
631
632 static void
633 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
634 const struct ir3_shader_variant *ds)
635 {
636 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
637 tu_cs_emit(cs, emit_xs_config(ds));
638 tu_cs_emit(cs, ds->instrlen);
639
640 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
641 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
642 }
643
644 static void
645 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
646 const struct ir3_shader_variant *gs)
647 {
648 bool has_gs = gs->type != MESA_SHADER_NONE;
649 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
650 tu_cs_emit(cs, 0);
651
652 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
653 tu_cs_emit(cs, emit_xs_config(gs));
654 tu_cs_emit(cs, gs->instrlen);
655
656 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
657 tu_cs_emit(cs, COND(has_gs, A6XX_HLSQ_GS_CNTL_ENABLED) |
658 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
659 }
660
661 static void
662 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
663 const struct ir3_shader_variant *fs)
664 {
665 uint32_t sp_fs_ctrl =
666 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
667 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
668 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
669 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
670 if (fs->total_in > 0)
671 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
672 if (fs->need_pixlod)
673 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
674 if (fs->need_fine_derivatives)
675 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_DIFF_FINE;
676
677 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
678 tu_cs_emit(cs, sp_fs_ctrl);
679
680 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
681 tu_cs_emit(cs, emit_xs_config(fs));
682 tu_cs_emit(cs, fs->instrlen);
683
684 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
685 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
686 A6XX_HLSQ_FS_CNTL_ENABLED);
687 }
688
689 static void
690 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
691 const struct ir3_shader_variant *v)
692 {
693 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
694 tu_cs_emit(cs, 0xff);
695
696 unsigned constlen = align(v->constlen, 4);
697 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
698 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
699 A6XX_HLSQ_CS_CNTL_ENABLED);
700
701 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
702 tu_cs_emit(cs, emit_xs_config(v));
703 tu_cs_emit(cs, v->instrlen);
704
705 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
706 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
707 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
708 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
709 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
710 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE) |
711 COND(v->need_fine_derivatives, A6XX_SP_CS_CTRL_REG0_DIFF_FINE));
712
713 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
714 tu_cs_emit(cs, 0x41);
715
716 uint32_t local_invocation_id =
717 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
718 uint32_t work_group_id =
719 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
720
721 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
722 tu_cs_emit(cs,
723 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
724 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
725 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
726 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
727 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
728 }
729
730 static void
731 tu6_emit_vs_system_values(struct tu_cs *cs,
732 const struct ir3_shader_variant *vs,
733 const struct ir3_shader_variant *gs)
734 {
735 const uint32_t vertexid_regid =
736 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
737 const uint32_t instanceid_regid =
738 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
739 const uint32_t primitiveid_regid = gs->type != MESA_SHADER_NONE ?
740 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
741 regid(63, 0);
742 const uint32_t gsheader_regid = gs->type != MESA_SHADER_NONE ?
743 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
744 regid(63, 0);
745
746 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
747 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
748 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
749 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
750 0xfc000000);
751 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
752 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
753 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
754 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
755 0xfc00); /* VFD_CONTROL_5 */
756 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
757 }
758
759 /* Add any missing varyings needed for stream-out. Otherwise varyings not
760 * used by fragment shader will be stripped out.
761 */
762 static void
763 tu6_link_streamout(struct ir3_shader_linkage *l,
764 const struct ir3_shader_variant *v)
765 {
766 const struct ir3_stream_output_info *info = &v->shader->stream_output;
767
768 /*
769 * First, any stream-out varyings not already in linkage map (ie. also
770 * consumed by frag shader) need to be added:
771 */
772 for (unsigned i = 0; i < info->num_outputs; i++) {
773 const struct ir3_stream_output *out = &info->output[i];
774 unsigned compmask =
775 (1 << (out->num_components + out->start_component)) - 1;
776 unsigned k = out->register_index;
777 unsigned idx, nextloc = 0;
778
779 /* psize/pos need to be the last entries in linkage map, and will
780 * get added link_stream_out, so skip over them:
781 */
782 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
783 v->outputs[k].slot == VARYING_SLOT_POS)
784 continue;
785
786 for (idx = 0; idx < l->cnt; idx++) {
787 if (l->var[idx].regid == v->outputs[k].regid)
788 break;
789 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
790 }
791
792 /* add if not already in linkage map: */
793 if (idx == l->cnt)
794 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
795
796 /* expand component-mask if needed, ie streaming out all components
797 * but frag shader doesn't consume all components:
798 */
799 if (compmask & ~l->var[idx].compmask) {
800 l->var[idx].compmask |= compmask;
801 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
802 util_last_bit(l->var[idx].compmask));
803 }
804 }
805 }
806
807 static void
808 tu6_setup_streamout(const struct ir3_shader_variant *v,
809 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
810 {
811 const struct ir3_stream_output_info *info = &v->shader->stream_output;
812
813 memset(tf, 0, sizeof(*tf));
814
815 tf->prog_count = align(l->max_loc, 2) / 2;
816
817 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
818
819 /* set stride info to the streamout state */
820 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
821 tf->stride[i] = info->stride[i];
822
823 for (unsigned i = 0; i < info->num_outputs; i++) {
824 const struct ir3_stream_output *out = &info->output[i];
825 unsigned k = out->register_index;
826 unsigned idx;
827
828 tf->ncomp[out->output_buffer] += out->num_components;
829
830 /* linkage map sorted by order frag shader wants things, so
831 * a bit less ideal here..
832 */
833 for (idx = 0; idx < l->cnt; idx++)
834 if (l->var[idx].regid == v->outputs[k].regid)
835 break;
836
837 debug_assert(idx < l->cnt);
838
839 for (unsigned j = 0; j < out->num_components; j++) {
840 unsigned c = j + out->start_component;
841 unsigned loc = l->var[idx].loc + c;
842 unsigned off = j + out->dst_offset; /* in dwords */
843
844 if (loc & 1) {
845 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
846 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
847 A6XX_VPC_SO_PROG_B_OFF(off * 4);
848 } else {
849 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
850 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
851 A6XX_VPC_SO_PROG_A_OFF(off * 4);
852 }
853 }
854 }
855
856 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
857 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
858 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
859 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
860 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
861 }
862
863 static void
864 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
865 enum a6xx_state_block block, uint32_t offset,
866 uint32_t size, uint32_t *dwords) {
867 assert(size % 4 == 0);
868
869 tu_cs_emit_pkt7(cs, opcode, 3 + size);
870 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
871 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
872 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
873 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
874 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
875
876 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
877 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
878 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
879
880 tu_cs_emit_array(cs, dwords, size);
881 }
882
883 static void
884 tu6_emit_link_map(struct tu_cs *cs,
885 const struct ir3_shader_variant *producer,
886 const struct ir3_shader_variant *consumer) {
887 const struct ir3_const_state *const_state = &consumer->shader->const_state;
888 uint32_t base = const_state->offsets.primitive_map;
889 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
890 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
891 int size = DIV_ROUND_UP(num_loc, 4);
892
893 size = (MIN2(size + base, consumer->constlen) - base) * 4;
894
895 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
896 patch_locs);
897 }
898
899 static uint16_t
900 gl_primitive_to_tess(uint16_t primitive) {
901 switch (primitive) {
902 case GL_POINTS:
903 return TESS_POINTS;
904 case GL_LINE_STRIP:
905 return TESS_LINES;
906 case GL_TRIANGLE_STRIP:
907 return TESS_CW_TRIS;
908 default:
909 unreachable("");
910 }
911 }
912
913 static void
914 tu6_emit_vpc(struct tu_cs *cs,
915 const struct ir3_shader_variant *vs,
916 const struct ir3_shader_variant *gs,
917 const struct ir3_shader_variant *fs,
918 bool binning_pass,
919 struct tu_streamout_state *tf)
920 {
921 bool has_gs = gs->type != MESA_SHADER_NONE;
922 const struct ir3_shader_variant *last_shader = has_gs ? gs : vs;
923 struct ir3_shader_linkage linkage = { 0 };
924 ir3_link_shaders(&linkage, last_shader, fs);
925
926 if (last_shader->shader->stream_output.num_outputs)
927 tu6_link_streamout(&linkage, last_shader);
928
929 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
930 for (uint32_t i = 0; i < linkage.cnt; i++) {
931 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
932 for (uint32_t j = 0; j < comp_count; j++)
933 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
934 }
935
936 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
937 tu_cs_emit(cs, ~vpc_var_enables[0]);
938 tu_cs_emit(cs, ~vpc_var_enables[1]);
939 tu_cs_emit(cs, ~vpc_var_enables[2]);
940 tu_cs_emit(cs, ~vpc_var_enables[3]);
941
942 /* a6xx finds position/pointsize at the end */
943 const uint32_t position_regid =
944 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
945 const uint32_t pointsize_regid =
946 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
947 const uint32_t layer_regid = has_gs ?
948 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
949
950 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
951 if (layer_regid != regid(63, 0)) {
952 layer_loc = linkage.max_loc;
953 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
954 }
955 if (position_regid != regid(63, 0)) {
956 position_loc = linkage.max_loc;
957 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
958 }
959 if (pointsize_regid != regid(63, 0)) {
960 pointsize_loc = linkage.max_loc;
961 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
962 }
963
964 if (last_shader->shader->stream_output.num_outputs)
965 tu6_setup_streamout(last_shader, &linkage, tf);
966
967 /* map outputs of the last shader to VPC */
968 assert(linkage.cnt <= 32);
969 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
970 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
971 uint32_t sp_out[16];
972 uint32_t sp_vpc_dst[8];
973 for (uint32_t i = 0; i < linkage.cnt; i++) {
974 ((uint16_t *) sp_out)[i] =
975 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
976 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
977 ((uint8_t *) sp_vpc_dst)[i] =
978 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
979 }
980
981 if (has_gs)
982 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
983 else
984 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
985 tu_cs_emit_array(cs, sp_out, sp_out_count);
986
987 if (has_gs)
988 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
989 else
990 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
991 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
992
993 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
994 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
995 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
996 0xff00ff00);
997
998 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
999 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
1000 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
1001 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
1002
1003 if (has_gs) {
1004 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1005 tu_cs_emit(cs, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
1006 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
1007 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
1008 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
1009
1010 tu6_emit_link_map(cs, vs, gs);
1011
1012 uint32_t primitive_regid =
1013 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
1014 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
1015 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
1016 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
1017 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
1018
1019 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
1020 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
1021
1022 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
1023 tu_cs_emit(cs, CONDREG(layer_regid,
1024 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
1025
1026 uint32_t flags_regid = ir3_find_output_regid(gs,
1027 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
1028
1029 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
1030 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
1031 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
1032
1033 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
1034 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
1035 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
1036 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
1037 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
1038
1039 uint32_t vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
1040 uint16_t output =
1041 gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
1042 uint32_t invocations = gs->shader->nir->info.gs.invocations - 1;
1043 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1044 tu_cs_emit(cs,
1045 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1046 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1047 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1048
1049 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1050 tu_cs_emit(cs, 0);
1051
1052 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
1053 tu_cs_emit(cs, 0);
1054
1055 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1056 tu_cs_emit(cs, 0xff);
1057
1058 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
1059 tu_cs_emit(cs, 0xffff00);
1060
1061 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1062 uint32_t vec4_size =
1063 gs->shader->nir->info.gs.vertices_in *
1064 DIV_ROUND_UP(vs->shader->output_size, 4);
1065 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1066 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1067
1068 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
1069 tu_cs_emit(cs, 0);
1070
1071 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
1072 tu_cs_emit(cs, vs->shader->output_size);
1073 }
1074
1075 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
1076 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
1077
1078 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
1079 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
1080 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
1081 }
1082
1083 static int
1084 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1085 uint32_t index,
1086 uint8_t *interp_mode,
1087 uint8_t *ps_repl_mode)
1088 {
1089 enum
1090 {
1091 INTERP_SMOOTH = 0,
1092 INTERP_FLAT = 1,
1093 INTERP_ZERO = 2,
1094 INTERP_ONE = 3,
1095 };
1096 enum
1097 {
1098 PS_REPL_NONE = 0,
1099 PS_REPL_S = 1,
1100 PS_REPL_T = 2,
1101 PS_REPL_ONE_MINUS_T = 3,
1102 };
1103
1104 const uint32_t compmask = fs->inputs[index].compmask;
1105
1106 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1107 * fourth component occupy three consecutive varying slots
1108 */
1109 int shift = 0;
1110 *interp_mode = 0;
1111 *ps_repl_mode = 0;
1112 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1113 if (compmask & 0x1) {
1114 *ps_repl_mode |= PS_REPL_S << shift;
1115 shift += 2;
1116 }
1117 if (compmask & 0x2) {
1118 *ps_repl_mode |= PS_REPL_T << shift;
1119 shift += 2;
1120 }
1121 if (compmask & 0x4) {
1122 *interp_mode |= INTERP_ZERO << shift;
1123 shift += 2;
1124 }
1125 if (compmask & 0x8) {
1126 *interp_mode |= INTERP_ONE << 6;
1127 shift += 2;
1128 }
1129 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1130 fs->inputs[index].rasterflat) {
1131 for (int i = 0; i < 4; i++) {
1132 if (compmask & (1 << i)) {
1133 *interp_mode |= INTERP_FLAT << shift;
1134 shift += 2;
1135 }
1136 }
1137 }
1138
1139 return shift;
1140 }
1141
1142 static void
1143 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1144 const struct ir3_shader_variant *fs,
1145 bool binning_pass)
1146 {
1147 uint32_t interp_modes[8] = { 0 };
1148 uint32_t ps_repl_modes[8] = { 0 };
1149
1150 if (!binning_pass) {
1151 for (int i = -1;
1152 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1153
1154 /* get the mode for input i */
1155 uint8_t interp_mode;
1156 uint8_t ps_repl_mode;
1157 const int bits =
1158 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1159
1160 /* OR the mode into the array */
1161 const uint32_t inloc = fs->inputs[i].inloc * 2;
1162 uint32_t n = inloc / 32;
1163 uint32_t shift = inloc % 32;
1164 interp_modes[n] |= interp_mode << shift;
1165 ps_repl_modes[n] |= ps_repl_mode << shift;
1166 if (shift + bits > 32) {
1167 n++;
1168 shift = 32 - shift;
1169
1170 interp_modes[n] |= interp_mode >> shift;
1171 ps_repl_modes[n] |= ps_repl_mode >> shift;
1172 }
1173 }
1174 }
1175
1176 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1177 tu_cs_emit_array(cs, interp_modes, 8);
1178
1179 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1180 tu_cs_emit_array(cs, ps_repl_modes, 8);
1181 }
1182
1183 static void
1184 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1185 {
1186 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1187 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
1188 uint32_t smask_in_regid;
1189
1190 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
1191 bool enable_varyings = fs->total_in > 0;
1192
1193 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1194 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1195 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1196 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1197 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1198 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1199 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1200 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1201 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1202
1203 if (fs->num_sampler_prefetch > 0) {
1204 assert(VALIDREG(ij_pix_regid));
1205 /* also, it seems like ij_pix is *required* to be r0.x */
1206 assert(ij_pix_regid == regid(0, 0));
1207 }
1208
1209 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1210 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1211 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1212 0x7000); // XXX);
1213 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1214 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1215 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1216 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1217 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1218 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1219 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1220 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1221 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1222 }
1223
1224 if (fs->num_sampler_prefetch > 0) {
1225 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1226 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1227 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1228 tu_cs_emit(cs,
1229 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1230 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1231 }
1232 }
1233
1234 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1235 tu_cs_emit(cs, 0x7);
1236 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1237 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1238 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1239 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1240 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1241 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1242 0xfc00fc00);
1243 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1244 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1245 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1246 0x0000fc00);
1247 tu_cs_emit(cs, 0xfc);
1248
1249 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1250 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1251
1252 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1253 tu_cs_emit(cs, 0xff); /* XXX */
1254
1255 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1256 tu_cs_emit(cs,
1257 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1258 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1259 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1260 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1261 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1262 COND(fs->frag_coord,
1263 A6XX_GRAS_CNTL_SIZE |
1264 A6XX_GRAS_CNTL_XCOORD |
1265 A6XX_GRAS_CNTL_YCOORD |
1266 A6XX_GRAS_CNTL_ZCOORD |
1267 A6XX_GRAS_CNTL_WCOORD) |
1268 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1269
1270 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1271 tu_cs_emit(cs,
1272 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1273 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1274 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1275 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1276 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1277 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1278 COND(fs->frag_coord,
1279 A6XX_RB_RENDER_CONTROL0_SIZE |
1280 A6XX_RB_RENDER_CONTROL0_XCOORD |
1281 A6XX_RB_RENDER_CONTROL0_YCOORD |
1282 A6XX_RB_RENDER_CONTROL0_ZCOORD |
1283 A6XX_RB_RENDER_CONTROL0_WCOORD) |
1284 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1285 tu_cs_emit(cs,
1286 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1287 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1288 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1289 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1290
1291 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1292 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1293
1294 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1295 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1296
1297 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1298 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1299 }
1300
1301 static void
1302 tu6_emit_fs_outputs(struct tu_cs *cs,
1303 const struct ir3_shader_variant *fs,
1304 uint32_t mrt_count)
1305 {
1306 uint32_t smask_regid, posz_regid;
1307
1308 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1309 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1310
1311 uint32_t fragdata_regid[8];
1312 if (fs->color0_mrt) {
1313 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1314 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1315 fragdata_regid[i] = fragdata_regid[0];
1316 } else {
1317 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1318 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1319 }
1320
1321 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1322 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1323 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1324 0xfc000000);
1325 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1326
1327 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1328 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1329 // TODO we could have a mix of half and full precision outputs,
1330 // we really need to figure out half-precision from IR3_REG_HALF
1331 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1332 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1333 }
1334
1335 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1336 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1337 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
1338 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1339
1340 uint32_t gras_su_depth_plane_cntl = 0;
1341 uint32_t rb_depth_plane_cntl = 0;
1342 if (fs->no_earlyz || fs->writes_pos) {
1343 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1344 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1345 }
1346
1347 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1348 tu_cs_emit(cs, gras_su_depth_plane_cntl);
1349
1350 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1351 tu_cs_emit(cs, rb_depth_plane_cntl);
1352 }
1353
1354 static void
1355 tu6_emit_shader_object(struct tu_cs *cs,
1356 gl_shader_stage stage,
1357 const struct ir3_shader_variant *variant,
1358 const struct tu_bo *binary_bo,
1359 uint32_t binary_offset)
1360 {
1361 uint16_t reg;
1362 uint8_t opcode;
1363 enum a6xx_state_block sb;
1364 switch (stage) {
1365 case MESA_SHADER_VERTEX:
1366 reg = REG_A6XX_SP_VS_OBJ_START_LO;
1367 opcode = CP_LOAD_STATE6_GEOM;
1368 sb = SB6_VS_SHADER;
1369 break;
1370 case MESA_SHADER_TESS_CTRL:
1371 reg = REG_A6XX_SP_HS_OBJ_START_LO;
1372 opcode = CP_LOAD_STATE6_GEOM;
1373 sb = SB6_HS_SHADER;
1374 break;
1375 case MESA_SHADER_TESS_EVAL:
1376 reg = REG_A6XX_SP_DS_OBJ_START_LO;
1377 opcode = CP_LOAD_STATE6_GEOM;
1378 sb = SB6_DS_SHADER;
1379 break;
1380 case MESA_SHADER_GEOMETRY:
1381 reg = REG_A6XX_SP_GS_OBJ_START_LO;
1382 opcode = CP_LOAD_STATE6_GEOM;
1383 sb = SB6_GS_SHADER;
1384 break;
1385 case MESA_SHADER_FRAGMENT:
1386 reg = REG_A6XX_SP_FS_OBJ_START_LO;
1387 opcode = CP_LOAD_STATE6_FRAG;
1388 sb = SB6_FS_SHADER;
1389 break;
1390 case MESA_SHADER_COMPUTE:
1391 reg = REG_A6XX_SP_CS_OBJ_START_LO;
1392 opcode = CP_LOAD_STATE6_FRAG;
1393 sb = SB6_CS_SHADER;
1394 break;
1395 default:
1396 unreachable("invalid gl_shader_stage");
1397 opcode = CP_LOAD_STATE6_GEOM;
1398 sb = SB6_VS_SHADER;
1399 break;
1400 }
1401
1402 if (!variant->instrlen) {
1403 tu_cs_emit_pkt4(cs, reg, 2);
1404 tu_cs_emit_qw(cs, 0);
1405 return;
1406 }
1407
1408 assert(variant->type == stage);
1409
1410 const uint64_t binary_iova = binary_bo->iova + binary_offset;
1411 assert((binary_iova & 0xf) == 0);
1412 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1413 * of the shader. this could be a potential source of problems at some point
1414 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1415 */
1416
1417 tu_cs_emit_pkt4(cs, reg, 2);
1418 tu_cs_emit_qw(cs, binary_iova);
1419
1420 /* always indirect */
1421 const bool indirect = true;
1422 if (indirect) {
1423 tu_cs_emit_pkt7(cs, opcode, 3);
1424 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1425 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1426 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1427 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1428 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1429 tu_cs_emit_qw(cs, binary_iova);
1430 } else {
1431 const void *binary = binary_bo->map + binary_offset;
1432
1433 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
1434 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1435 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1436 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1437 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1438 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1439 tu_cs_emit_qw(cs, 0);
1440 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
1441 }
1442 }
1443
1444 static void
1445 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
1446 uint32_t opcode, enum a6xx_state_block block)
1447 {
1448 /* dummy variant */
1449 if (!v->shader)
1450 return;
1451
1452 const struct ir3_const_state *const_state = &v->shader->const_state;
1453 uint32_t base = const_state->offsets.immediate;
1454 int size = const_state->immediates_count;
1455
1456 /* truncate size to avoid writing constants that shader
1457 * does not use:
1458 */
1459 size = MIN2(size + base, v->constlen) - base;
1460
1461 if (size <= 0)
1462 return;
1463
1464 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1465 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1466 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1467 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1468 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1469 CP_LOAD_STATE6_0_NUM_UNIT(size));
1470 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1471 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1472
1473 for (unsigned i = 0; i < size; i++) {
1474 tu_cs_emit(cs, const_state->immediates[i].val[0]);
1475 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1476 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1477 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1478 }
1479 }
1480
1481 static void
1482 tu6_emit_geometry_consts(struct tu_cs *cs,
1483 const struct ir3_shader_variant *vs,
1484 const struct ir3_shader_variant *gs) {
1485 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1486
1487 uint32_t params[4] = {
1488 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1489 vs->shader->output_size * 4, /* vertex stride */
1490 0,
1491 0,
1492 };
1493 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1494 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1495 ARRAY_SIZE(params), params);
1496
1497 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1498 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1499 ARRAY_SIZE(params), params);
1500 }
1501
1502 static void
1503 tu6_emit_program(struct tu_cs *cs,
1504 const struct tu_pipeline_builder *builder,
1505 const struct tu_bo *binary_bo,
1506 bool binning_pass,
1507 struct tu_streamout_state *tf)
1508 {
1509 static const struct ir3_shader_variant dummy_variant = {
1510 .type = MESA_SHADER_NONE
1511 };
1512 assert(builder->shaders[MESA_SHADER_VERTEX]);
1513 const struct ir3_shader_variant *vs =
1514 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1515 const struct ir3_shader_variant *hs =
1516 builder->shaders[MESA_SHADER_TESS_CTRL]
1517 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1518 : &dummy_variant;
1519 const struct ir3_shader_variant *ds =
1520 builder->shaders[MESA_SHADER_TESS_EVAL]
1521 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1522 : &dummy_variant;
1523 const struct ir3_shader_variant *gs =
1524 builder->shaders[MESA_SHADER_GEOMETRY]
1525 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1526 : &dummy_variant;
1527 const struct ir3_shader_variant *fs =
1528 builder->shaders[MESA_SHADER_FRAGMENT]
1529 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1530 : &dummy_variant;
1531 bool has_gs = gs->type != MESA_SHADER_NONE;
1532
1533 if (binning_pass) {
1534 /* if we have streamout, use full VS in binning pass, as the
1535 * binning pass VS will have outputs on other than position/psize
1536 * stripped out:
1537 */
1538 if (vs->shader->stream_output.num_outputs == 0)
1539 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1540 fs = &dummy_variant;
1541 }
1542
1543 tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1544 tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1545 tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1546 tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1547 tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1548
1549 tu6_emit_vs_system_values(cs, vs, gs);
1550 tu6_emit_vpc(cs, vs, gs, fs, binning_pass, tf);
1551 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1552 tu6_emit_fs_inputs(cs, fs);
1553 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1554
1555 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1556 binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1557 if (has_gs)
1558 tu6_emit_shader_object(cs, MESA_SHADER_GEOMETRY, gs, binary_bo,
1559 builder->shader_offsets[MESA_SHADER_GEOMETRY]);
1560 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1561 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1562
1563 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1564 if (has_gs) {
1565 tu6_emit_immediates(cs, gs, CP_LOAD_STATE6_GEOM, SB6_GS_SHADER);
1566 tu6_emit_geometry_consts(cs, vs, gs);
1567 }
1568 if (!binning_pass)
1569 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1570 }
1571
1572 static void
1573 tu6_emit_vertex_input(struct tu_cs *cs,
1574 const struct ir3_shader_variant *vs,
1575 const VkPipelineVertexInputStateCreateInfo *info,
1576 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1577 uint32_t *count)
1578 {
1579 uint32_t vfd_fetch_idx = 0;
1580 uint32_t vfd_decode_idx = 0;
1581 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1582
1583 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1584 const VkVertexInputBindingDescription *binding =
1585 &info->pVertexBindingDescriptions[i];
1586
1587 tu_cs_emit_regs(cs,
1588 A6XX_VFD_FETCH_STRIDE(vfd_fetch_idx, binding->stride));
1589
1590 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1591 binding_instanced |= 1 << binding->binding;
1592
1593 bindings[vfd_fetch_idx] = binding->binding;
1594 vfd_fetch_idx++;
1595 }
1596
1597 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1598
1599 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1600 const VkVertexInputAttributeDescription *attr =
1601 &info->pVertexAttributeDescriptions[i];
1602 uint32_t binding_idx, input_idx;
1603
1604 for (binding_idx = 0; binding_idx < vfd_fetch_idx; binding_idx++) {
1605 if (bindings[binding_idx] == attr->binding)
1606 break;
1607 }
1608 assert(binding_idx < vfd_fetch_idx);
1609
1610 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1611 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1612 break;
1613 }
1614
1615 /* attribute not used, skip it */
1616 if (input_idx == vs->inputs_count)
1617 continue;
1618
1619 const struct tu_native_format format = tu6_format_vtx(attr->format);
1620 tu_cs_emit_regs(cs,
1621 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1622 .idx = binding_idx,
1623 .offset = attr->offset,
1624 .instanced = binding_instanced & (1 << attr->binding),
1625 .format = format.fmt,
1626 .swap = format.swap,
1627 .unk30 = 1,
1628 ._float = !vk_format_is_int(attr->format)),
1629 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1630
1631 tu_cs_emit_regs(cs,
1632 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1633 .writemask = vs->inputs[input_idx].compmask,
1634 .regid = vs->inputs[input_idx].regid));
1635
1636 vfd_decode_idx++;
1637 }
1638
1639 tu_cs_emit_regs(cs,
1640 A6XX_VFD_CONTROL_0(
1641 .fetch_cnt = vfd_fetch_idx,
1642 .decode_cnt = vfd_decode_idx));
1643
1644 *count = vfd_fetch_idx;
1645 }
1646
1647 static uint32_t
1648 tu6_guardband_adj(uint32_t v)
1649 {
1650 if (v > 256)
1651 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1652 else
1653 return 511;
1654 }
1655
1656 void
1657 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1658 {
1659 float offsets[3];
1660 float scales[3];
1661 scales[0] = viewport->width / 2.0f;
1662 scales[1] = viewport->height / 2.0f;
1663 scales[2] = viewport->maxDepth - viewport->minDepth;
1664 offsets[0] = viewport->x + scales[0];
1665 offsets[1] = viewport->y + scales[1];
1666 offsets[2] = viewport->minDepth;
1667
1668 VkOffset2D min;
1669 VkOffset2D max;
1670 min.x = (int32_t) viewport->x;
1671 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1672 if (viewport->height >= 0.0f) {
1673 min.y = (int32_t) viewport->y;
1674 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1675 } else {
1676 min.y = (int32_t)(viewport->y + viewport->height);
1677 max.y = (int32_t) ceilf(viewport->y);
1678 }
1679 /* the spec allows viewport->height to be 0.0f */
1680 if (min.y == max.y)
1681 max.y++;
1682 assert(min.x >= 0 && min.x < max.x);
1683 assert(min.y >= 0 && min.y < max.y);
1684
1685 VkExtent2D guardband_adj;
1686 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1687 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1688
1689 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1690 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1691 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1692 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1693 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1694 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1695 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1696
1697 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1698 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1699 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1700 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1701 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1702
1703 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1704 tu_cs_emit(cs,
1705 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1706 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1707
1708 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1709 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1710
1711 tu_cs_emit_regs(cs,
1712 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1713 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1714
1715 tu_cs_emit_regs(cs,
1716 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1717 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1718 }
1719
1720 void
1721 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1722 {
1723 const VkOffset2D min = scissor->offset;
1724 const VkOffset2D max = {
1725 scissor->offset.x + scissor->extent.width,
1726 scissor->offset.y + scissor->extent.height,
1727 };
1728
1729 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1730 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1731 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1732 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1733 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1734 }
1735
1736 static void
1737 tu6_emit_gras_unknowns(struct tu_cs *cs)
1738 {
1739 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1740 tu_cs_emit(cs, 0x0);
1741 }
1742
1743 static void
1744 tu6_emit_point_size(struct tu_cs *cs)
1745 {
1746 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1747 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1748 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1749 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1750 }
1751
1752 static uint32_t
1753 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1754 VkSampleCountFlagBits samples)
1755 {
1756 uint32_t gras_su_cntl = 0;
1757
1758 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1759 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1760 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1761 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1762
1763 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1764 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1765
1766 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1767
1768 if (rast_info->depthBiasEnable)
1769 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1770
1771 if (samples > VK_SAMPLE_COUNT_1_BIT)
1772 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1773
1774 return gras_su_cntl;
1775 }
1776
1777 void
1778 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1779 uint32_t gras_su_cntl,
1780 float line_width)
1781 {
1782 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1783 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1784
1785 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1786 tu_cs_emit(cs, gras_su_cntl);
1787 }
1788
1789 void
1790 tu6_emit_depth_bias(struct tu_cs *cs,
1791 float constant_factor,
1792 float clamp,
1793 float slope_factor)
1794 {
1795 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1796 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1797 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1798 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1799 }
1800
1801 static void
1802 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1803 {
1804 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1805 tu_cs_emit(cs, 0);
1806 }
1807
1808 static void
1809 tu6_emit_depth_control(struct tu_cs *cs,
1810 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1811 const VkPipelineRasterizationStateCreateInfo *rast_info)
1812 {
1813 assert(!ds_info->depthBoundsTestEnable);
1814
1815 uint32_t rb_depth_cntl = 0;
1816 if (ds_info->depthTestEnable) {
1817 rb_depth_cntl |=
1818 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1819 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1820 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1821
1822 if (rast_info->depthClampEnable)
1823 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1824
1825 if (ds_info->depthWriteEnable)
1826 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1827 }
1828
1829 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1830 tu_cs_emit(cs, rb_depth_cntl);
1831 }
1832
1833 static void
1834 tu6_emit_stencil_control(struct tu_cs *cs,
1835 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1836 {
1837 uint32_t rb_stencil_control = 0;
1838 if (ds_info->stencilTestEnable) {
1839 const VkStencilOpState *front = &ds_info->front;
1840 const VkStencilOpState *back = &ds_info->back;
1841 rb_stencil_control |=
1842 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1843 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1844 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1845 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1846 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1847 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1848 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1849 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1850 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1851 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1852 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1853 }
1854
1855 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1856 tu_cs_emit(cs, rb_stencil_control);
1857 }
1858
1859 void
1860 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1861 {
1862 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1863 tu_cs_emit(
1864 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1865 }
1866
1867 void
1868 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1869 {
1870 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1871 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1872 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1873 }
1874
1875 void
1876 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1877 {
1878 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1879 tu_cs_emit(cs,
1880 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1881 }
1882
1883 static uint32_t
1884 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1885 bool has_alpha)
1886 {
1887 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1888 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1889 has_alpha ? att->srcColorBlendFactor
1890 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1891 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1892 has_alpha ? att->dstColorBlendFactor
1893 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1894 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1895 const enum adreno_rb_blend_factor src_alpha_factor =
1896 tu6_blend_factor(att->srcAlphaBlendFactor);
1897 const enum adreno_rb_blend_factor dst_alpha_factor =
1898 tu6_blend_factor(att->dstAlphaBlendFactor);
1899
1900 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1901 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1902 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1903 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1904 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1905 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1906 }
1907
1908 static uint32_t
1909 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1910 uint32_t rb_mrt_control_rop,
1911 bool is_int,
1912 bool has_alpha)
1913 {
1914 uint32_t rb_mrt_control =
1915 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1916
1917 /* ignore blending and logic op for integer attachments */
1918 if (is_int) {
1919 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1920 return rb_mrt_control;
1921 }
1922
1923 rb_mrt_control |= rb_mrt_control_rop;
1924
1925 if (att->blendEnable) {
1926 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1927
1928 if (has_alpha)
1929 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1930 }
1931
1932 return rb_mrt_control;
1933 }
1934
1935 static void
1936 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1937 const VkPipelineColorBlendStateCreateInfo *blend_info,
1938 const VkFormat attachment_formats[MAX_RTS],
1939 uint32_t *blend_enable_mask)
1940 {
1941 *blend_enable_mask = 0;
1942
1943 bool rop_reads_dst = false;
1944 uint32_t rb_mrt_control_rop = 0;
1945 if (blend_info->logicOpEnable) {
1946 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1947 rb_mrt_control_rop =
1948 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1949 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1950 }
1951
1952 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1953 const VkPipelineColorBlendAttachmentState *att =
1954 &blend_info->pAttachments[i];
1955 const VkFormat format = attachment_formats[i];
1956
1957 uint32_t rb_mrt_control = 0;
1958 uint32_t rb_mrt_blend_control = 0;
1959 if (format != VK_FORMAT_UNDEFINED) {
1960 const bool is_int = vk_format_is_int(format);
1961 const bool has_alpha = vk_format_has_alpha(format);
1962
1963 rb_mrt_control =
1964 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1965 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1966
1967 if (att->blendEnable || rop_reads_dst)
1968 *blend_enable_mask |= 1 << i;
1969 }
1970
1971 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1972 tu_cs_emit(cs, rb_mrt_control);
1973 tu_cs_emit(cs, rb_mrt_blend_control);
1974 }
1975 }
1976
1977 static void
1978 tu6_emit_blend_control(struct tu_cs *cs,
1979 uint32_t blend_enable_mask,
1980 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1981 {
1982 assert(!msaa_info->alphaToOneEnable);
1983
1984 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1985 if (blend_enable_mask)
1986 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1987 if (msaa_info->alphaToCoverageEnable)
1988 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1989
1990 const uint32_t sample_mask =
1991 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1992 : ((1 << msaa_info->rasterizationSamples) - 1);
1993
1994 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1995 uint32_t rb_blend_cntl =
1996 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1997 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1998 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1999 if (msaa_info->alphaToCoverageEnable)
2000 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
2001
2002 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
2003 tu_cs_emit(cs, sp_blend_cntl);
2004
2005 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
2006 tu_cs_emit(cs, rb_blend_cntl);
2007 }
2008
2009 void
2010 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
2011 {
2012 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2013 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
2014 }
2015
2016 static VkResult
2017 tu_pipeline_create(struct tu_device *dev,
2018 struct tu_pipeline_layout *layout,
2019 bool compute,
2020 const VkAllocationCallbacks *pAllocator,
2021 struct tu_pipeline **out_pipeline)
2022 {
2023 struct tu_pipeline *pipeline =
2024 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
2025 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2026 if (!pipeline)
2027 return VK_ERROR_OUT_OF_HOST_MEMORY;
2028
2029 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
2030
2031 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
2032 * that LOAD_STATE can potentially take up a large amount of space so we
2033 * calculate its size explicitly.
2034 */
2035 unsigned load_state_size = tu6_load_state_size(layout, compute);
2036 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size);
2037 if (result != VK_SUCCESS) {
2038 vk_free2(&dev->alloc, pAllocator, pipeline);
2039 return result;
2040 }
2041
2042 *out_pipeline = pipeline;
2043
2044 return VK_SUCCESS;
2045 }
2046
2047 static VkResult
2048 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
2049 {
2050 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
2051 NULL
2052 };
2053 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
2054 gl_shader_stage stage =
2055 tu_shader_stage(builder->create_info->pStages[i].stage);
2056 stage_infos[stage] = &builder->create_info->pStages[i];
2057 }
2058
2059 struct tu_shader_compile_options options;
2060 tu_shader_compile_options_init(&options, builder->create_info);
2061
2062 /* compile shaders in reverse order */
2063 struct tu_shader *next_stage_shader = NULL;
2064 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
2065 stage > MESA_SHADER_NONE; stage--) {
2066 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
2067 if (!stage_info)
2068 continue;
2069
2070 struct tu_shader *shader =
2071 tu_shader_create(builder->device, stage, stage_info, builder->layout,
2072 builder->alloc);
2073 if (!shader)
2074 return VK_ERROR_OUT_OF_HOST_MEMORY;
2075
2076 VkResult result =
2077 tu_shader_compile(builder->device, shader, next_stage_shader,
2078 &options, builder->alloc);
2079 if (result != VK_SUCCESS)
2080 return result;
2081
2082 builder->shaders[stage] = shader;
2083 builder->shader_offsets[stage] = builder->shader_total_size;
2084 builder->shader_total_size +=
2085 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
2086
2087 next_stage_shader = shader;
2088 }
2089
2090 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2091 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2092 const struct ir3_shader_variant *variant;
2093
2094 if (vs->ir3_shader.stream_output.num_outputs)
2095 variant = &vs->variants[0];
2096 else
2097 variant = &vs->variants[1];
2098
2099 builder->binning_vs_offset = builder->shader_total_size;
2100 builder->shader_total_size +=
2101 sizeof(uint32_t) * variant->info.sizedwords;
2102 }
2103
2104 return VK_SUCCESS;
2105 }
2106
2107 static VkResult
2108 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
2109 struct tu_pipeline *pipeline)
2110 {
2111 struct tu_bo *bo = &pipeline->program.binary_bo;
2112
2113 VkResult result =
2114 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
2115 if (result != VK_SUCCESS)
2116 return result;
2117
2118 result = tu_bo_map(builder->device, bo);
2119 if (result != VK_SUCCESS)
2120 return result;
2121
2122 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2123 const struct tu_shader *shader = builder->shaders[i];
2124 if (!shader)
2125 continue;
2126
2127 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
2128 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
2129 }
2130
2131 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2132 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2133 const struct ir3_shader_variant *variant;
2134 void *bin;
2135
2136 if (vs->ir3_shader.stream_output.num_outputs) {
2137 variant = &vs->variants[0];
2138 bin = vs->binary;
2139 } else {
2140 variant = &vs->variants[1];
2141 bin = vs->binning_binary;
2142 }
2143
2144 memcpy(bo->map + builder->binning_vs_offset, bin,
2145 sizeof(uint32_t) * variant->info.sizedwords);
2146 }
2147
2148 return VK_SUCCESS;
2149 }
2150
2151 static void
2152 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2153 struct tu_pipeline *pipeline)
2154 {
2155 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2156 builder->create_info->pDynamicState;
2157
2158 if (!dynamic_info)
2159 return;
2160
2161 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2162 pipeline->dynamic_state.mask |=
2163 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
2164 }
2165 }
2166
2167 static void
2168 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2169 struct tu_shader *shader,
2170 struct ir3_shader_variant *v)
2171 {
2172 link->ubo_state = v->shader->ubo_state;
2173 link->const_state = v->shader->const_state;
2174 link->constlen = v->constlen;
2175 link->push_consts = shader->push_consts;
2176 }
2177
2178 static void
2179 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2180 struct tu_pipeline *pipeline)
2181 {
2182 struct tu_cs prog_cs;
2183 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2184 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
2185 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2186
2187 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2188 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
2189 pipeline->program.binning_state_ib =
2190 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2191
2192 VkShaderStageFlags stages = 0;
2193 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2194 stages |= builder->create_info->pStages[i].stage;
2195 }
2196 pipeline->active_stages = stages;
2197
2198 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2199 if (!builder->shaders[i])
2200 continue;
2201
2202 tu_pipeline_set_linkage(&pipeline->program.link[i],
2203 builder->shaders[i],
2204 &builder->shaders[i]->variants[0]);
2205 }
2206
2207 if (builder->shaders[MESA_SHADER_FRAGMENT]) {
2208 memcpy(pipeline->program.input_attachment_idx,
2209 builder->shaders[MESA_SHADER_FRAGMENT]->attachment_idx,
2210 sizeof(pipeline->program.input_attachment_idx));
2211 }
2212 }
2213
2214 static void
2215 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2216 struct tu_pipeline *pipeline)
2217 {
2218 const VkPipelineVertexInputStateCreateInfo *vi_info =
2219 builder->create_info->pVertexInputState;
2220 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2221
2222 struct tu_cs vi_cs;
2223 tu_cs_begin_sub_stream(&pipeline->cs,
2224 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2225 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
2226 pipeline->vi.bindings, &pipeline->vi.count);
2227 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2228
2229 if (vs->has_binning_pass) {
2230 tu_cs_begin_sub_stream(&pipeline->cs,
2231 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2232 tu6_emit_vertex_input(
2233 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
2234 &pipeline->vi.binning_count);
2235 pipeline->vi.binning_state_ib =
2236 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2237 }
2238 }
2239
2240 static void
2241 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2242 struct tu_pipeline *pipeline)
2243 {
2244 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2245 builder->create_info->pInputAssemblyState;
2246
2247 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2248 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2249 }
2250
2251 static void
2252 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2253 struct tu_pipeline *pipeline)
2254 {
2255 /* The spec says:
2256 *
2257 * pViewportState is a pointer to an instance of the
2258 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2259 * pipeline has rasterization disabled."
2260 *
2261 * We leave the relevant registers stale in that case.
2262 */
2263 if (builder->rasterizer_discard)
2264 return;
2265
2266 const VkPipelineViewportStateCreateInfo *vp_info =
2267 builder->create_info->pViewportState;
2268
2269 struct tu_cs vp_cs;
2270 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
2271
2272 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2273 assert(vp_info->viewportCount == 1);
2274 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
2275 }
2276
2277 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2278 assert(vp_info->scissorCount == 1);
2279 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
2280 }
2281
2282 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
2283 }
2284
2285 static void
2286 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2287 struct tu_pipeline *pipeline)
2288 {
2289 const VkPipelineRasterizationStateCreateInfo *rast_info =
2290 builder->create_info->pRasterizationState;
2291
2292 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2293
2294 struct tu_cs rast_cs;
2295 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
2296
2297
2298 tu_cs_emit_regs(&rast_cs,
2299 A6XX_GRAS_CL_CNTL(
2300 .znear_clip_disable = rast_info->depthClampEnable,
2301 .zfar_clip_disable = rast_info->depthClampEnable,
2302 .unk5 = rast_info->depthClampEnable,
2303 .zero_gb_scale_z = 1,
2304 .vp_clip_code_ignore = 1));
2305 /* move to hw ctx init? */
2306 tu6_emit_gras_unknowns(&rast_cs);
2307 tu6_emit_point_size(&rast_cs);
2308
2309 const uint32_t gras_su_cntl =
2310 tu6_gras_su_cntl(rast_info, builder->samples);
2311
2312 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
2313 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
2314
2315 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
2316 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
2317 rast_info->depthBiasClamp,
2318 rast_info->depthBiasSlopeFactor);
2319 }
2320
2321 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
2322
2323 pipeline->rast.gras_su_cntl = gras_su_cntl;
2324 }
2325
2326 static void
2327 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2328 struct tu_pipeline *pipeline)
2329 {
2330 /* The spec says:
2331 *
2332 * pDepthStencilState is a pointer to an instance of the
2333 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2334 * the pipeline has rasterization disabled or if the subpass of the
2335 * render pass the pipeline is created against does not use a
2336 * depth/stencil attachment.
2337 *
2338 * We disable both depth and stenil tests in those cases.
2339 */
2340 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2341 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2342 builder->use_depth_stencil_attachment
2343 ? builder->create_info->pDepthStencilState
2344 : &dummy_ds_info;
2345
2346 struct tu_cs ds_cs;
2347 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2348
2349 /* move to hw ctx init? */
2350 tu6_emit_alpha_control_disable(&ds_cs);
2351
2352 tu6_emit_depth_control(&ds_cs, ds_info, builder->create_info->pRasterizationState);
2353 tu6_emit_stencil_control(&ds_cs, ds_info);
2354
2355 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2356 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2357 ds_info->back.compareMask);
2358 }
2359 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2360 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2361 ds_info->back.writeMask);
2362 }
2363 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2364 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2365 ds_info->back.reference);
2366 }
2367
2368 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2369 }
2370
2371 static void
2372 tu_pipeline_builder_parse_multisample_and_color_blend(
2373 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2374 {
2375 /* The spec says:
2376 *
2377 * pMultisampleState is a pointer to an instance of the
2378 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2379 * has rasterization disabled.
2380 *
2381 * Also,
2382 *
2383 * pColorBlendState is a pointer to an instance of the
2384 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2385 * pipeline has rasterization disabled or if the subpass of the render
2386 * pass the pipeline is created against does not use any color
2387 * attachments.
2388 *
2389 * We leave the relevant registers stale when rasterization is disabled.
2390 */
2391 if (builder->rasterizer_discard)
2392 return;
2393
2394 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2395 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2396 builder->create_info->pMultisampleState;
2397 const VkPipelineColorBlendStateCreateInfo *blend_info =
2398 builder->use_color_attachments ? builder->create_info->pColorBlendState
2399 : &dummy_blend_info;
2400
2401 struct tu_cs blend_cs;
2402 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 9, &blend_cs);
2403
2404 uint32_t blend_enable_mask;
2405 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2406 builder->color_attachment_formats,
2407 &blend_enable_mask);
2408
2409 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2410 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2411
2412 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
2413
2414 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2415 }
2416
2417 static void
2418 tu_pipeline_finish(struct tu_pipeline *pipeline,
2419 struct tu_device *dev,
2420 const VkAllocationCallbacks *alloc)
2421 {
2422 tu_cs_finish(&pipeline->cs);
2423
2424 if (pipeline->program.binary_bo.gem_handle)
2425 tu_bo_finish(dev, &pipeline->program.binary_bo);
2426 }
2427
2428 static VkResult
2429 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2430 struct tu_pipeline **pipeline)
2431 {
2432 VkResult result = tu_pipeline_create(builder->device, builder->layout,
2433 false, builder->alloc, pipeline);
2434 if (result != VK_SUCCESS)
2435 return result;
2436
2437 (*pipeline)->layout = builder->layout;
2438
2439 /* compile and upload shaders */
2440 result = tu_pipeline_builder_compile_shaders(builder);
2441 if (result == VK_SUCCESS)
2442 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2443 if (result != VK_SUCCESS) {
2444 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2445 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2446 *pipeline = VK_NULL_HANDLE;
2447
2448 return result;
2449 }
2450
2451 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2452 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2453 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2454 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2455 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2456 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2457 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2458 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2459 tu6_emit_load_state(*pipeline, false);
2460
2461 /* we should have reserved enough space upfront such that the CS never
2462 * grows
2463 */
2464 assert((*pipeline)->cs.bo_count == 1);
2465
2466 return VK_SUCCESS;
2467 }
2468
2469 static void
2470 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2471 {
2472 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2473 if (!builder->shaders[i])
2474 continue;
2475 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2476 }
2477 }
2478
2479 static void
2480 tu_pipeline_builder_init_graphics(
2481 struct tu_pipeline_builder *builder,
2482 struct tu_device *dev,
2483 struct tu_pipeline_cache *cache,
2484 const VkGraphicsPipelineCreateInfo *create_info,
2485 const VkAllocationCallbacks *alloc)
2486 {
2487 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2488
2489 *builder = (struct tu_pipeline_builder) {
2490 .device = dev,
2491 .cache = cache,
2492 .create_info = create_info,
2493 .alloc = alloc,
2494 .layout = layout,
2495 };
2496
2497 builder->rasterizer_discard =
2498 create_info->pRasterizationState->rasterizerDiscardEnable;
2499
2500 if (builder->rasterizer_discard) {
2501 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2502 } else {
2503 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2504
2505 const struct tu_render_pass *pass =
2506 tu_render_pass_from_handle(create_info->renderPass);
2507 const struct tu_subpass *subpass =
2508 &pass->subpasses[create_info->subpass];
2509
2510 builder->use_depth_stencil_attachment =
2511 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
2512
2513 assert(subpass->color_count == 0 ||
2514 !create_info->pColorBlendState ||
2515 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2516 builder->color_attachment_count = subpass->color_count;
2517 for (uint32_t i = 0; i < subpass->color_count; i++) {
2518 const uint32_t a = subpass->color_attachments[i].attachment;
2519 if (a == VK_ATTACHMENT_UNUSED)
2520 continue;
2521
2522 builder->color_attachment_formats[i] = pass->attachments[a].format;
2523 builder->use_color_attachments = true;
2524 }
2525 }
2526 }
2527
2528 static VkResult
2529 tu_graphics_pipeline_create(VkDevice device,
2530 VkPipelineCache pipelineCache,
2531 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2532 const VkAllocationCallbacks *pAllocator,
2533 VkPipeline *pPipeline)
2534 {
2535 TU_FROM_HANDLE(tu_device, dev, device);
2536 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2537
2538 struct tu_pipeline_builder builder;
2539 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2540 pCreateInfo, pAllocator);
2541
2542 struct tu_pipeline *pipeline = NULL;
2543 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2544 tu_pipeline_builder_finish(&builder);
2545
2546 if (result == VK_SUCCESS)
2547 *pPipeline = tu_pipeline_to_handle(pipeline);
2548 else
2549 *pPipeline = VK_NULL_HANDLE;
2550
2551 return result;
2552 }
2553
2554 VkResult
2555 tu_CreateGraphicsPipelines(VkDevice device,
2556 VkPipelineCache pipelineCache,
2557 uint32_t count,
2558 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2559 const VkAllocationCallbacks *pAllocator,
2560 VkPipeline *pPipelines)
2561 {
2562 VkResult final_result = VK_SUCCESS;
2563
2564 for (uint32_t i = 0; i < count; i++) {
2565 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2566 &pCreateInfos[i], pAllocator,
2567 &pPipelines[i]);
2568
2569 if (result != VK_SUCCESS)
2570 final_result = result;
2571 }
2572
2573 return final_result;
2574 }
2575
2576 static void
2577 tu6_emit_compute_program(struct tu_cs *cs,
2578 struct tu_shader *shader,
2579 const struct tu_bo *binary_bo)
2580 {
2581 const struct ir3_shader_variant *v = &shader->variants[0];
2582
2583 tu6_emit_cs_config(cs, shader, v);
2584
2585 /* The compute program is the only one in the pipeline, so 0 offset. */
2586 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2587
2588 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2589 }
2590
2591 static VkResult
2592 tu_compute_upload_shader(VkDevice device,
2593 struct tu_pipeline *pipeline,
2594 struct tu_shader *shader)
2595 {
2596 TU_FROM_HANDLE(tu_device, dev, device);
2597 struct tu_bo *bo = &pipeline->program.binary_bo;
2598 struct ir3_shader_variant *v = &shader->variants[0];
2599
2600 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2601 VkResult result =
2602 tu_bo_init_new(dev, bo, shader_size);
2603 if (result != VK_SUCCESS)
2604 return result;
2605
2606 result = tu_bo_map(dev, bo);
2607 if (result != VK_SUCCESS)
2608 return result;
2609
2610 memcpy(bo->map, shader->binary, shader_size);
2611
2612 return VK_SUCCESS;
2613 }
2614
2615
2616 static VkResult
2617 tu_compute_pipeline_create(VkDevice device,
2618 VkPipelineCache _cache,
2619 const VkComputePipelineCreateInfo *pCreateInfo,
2620 const VkAllocationCallbacks *pAllocator,
2621 VkPipeline *pPipeline)
2622 {
2623 TU_FROM_HANDLE(tu_device, dev, device);
2624 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2625 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2626 VkResult result;
2627
2628 struct tu_pipeline *pipeline;
2629
2630 *pPipeline = VK_NULL_HANDLE;
2631
2632 result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline);
2633 if (result != VK_SUCCESS)
2634 return result;
2635
2636 pipeline->layout = layout;
2637
2638 struct tu_shader_compile_options options;
2639 tu_shader_compile_options_init(&options, NULL);
2640
2641 struct tu_shader *shader =
2642 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2643 if (!shader) {
2644 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2645 goto fail;
2646 }
2647
2648 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2649 if (result != VK_SUCCESS)
2650 goto fail;
2651
2652 struct ir3_shader_variant *v = &shader->variants[0];
2653
2654 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2655 shader, v);
2656
2657 result = tu_compute_upload_shader(device, pipeline, shader);
2658 if (result != VK_SUCCESS)
2659 goto fail;
2660
2661 for (int i = 0; i < 3; i++)
2662 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2663
2664 struct tu_cs prog_cs;
2665 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2666 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2667 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2668
2669 tu6_emit_load_state(pipeline, true);
2670
2671 *pPipeline = tu_pipeline_to_handle(pipeline);
2672 return VK_SUCCESS;
2673
2674 fail:
2675 if (shader)
2676 tu_shader_destroy(dev, shader, pAllocator);
2677
2678 tu_pipeline_finish(pipeline, dev, pAllocator);
2679 vk_free2(&dev->alloc, pAllocator, pipeline);
2680
2681 return result;
2682 }
2683
2684 VkResult
2685 tu_CreateComputePipelines(VkDevice device,
2686 VkPipelineCache pipelineCache,
2687 uint32_t count,
2688 const VkComputePipelineCreateInfo *pCreateInfos,
2689 const VkAllocationCallbacks *pAllocator,
2690 VkPipeline *pPipelines)
2691 {
2692 VkResult final_result = VK_SUCCESS;
2693
2694 for (uint32_t i = 0; i < count; i++) {
2695 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2696 &pCreateInfos[i],
2697 pAllocator, &pPipelines[i]);
2698 if (result != VK_SUCCESS)
2699 final_result = result;
2700 }
2701
2702 return final_result;
2703 }
2704
2705 void
2706 tu_DestroyPipeline(VkDevice _device,
2707 VkPipeline _pipeline,
2708 const VkAllocationCallbacks *pAllocator)
2709 {
2710 TU_FROM_HANDLE(tu_device, dev, _device);
2711 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2712
2713 if (!_pipeline)
2714 return;
2715
2716 tu_pipeline_finish(pipeline, dev, pAllocator);
2717 vk_free2(&dev->alloc, pAllocator, pipeline);
2718 }