2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
43 /* Emit IB that preloads the descriptors that the shader uses */
46 emit_load_state(struct tu_cs
*cs
, unsigned opcode
, enum a6xx_state_type st
,
47 enum a6xx_state_block sb
, unsigned base
, unsigned offset
,
50 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
51 * clear if emitting more packets will even help anything. Presumably the
52 * descriptor cache is relatively small, and these packets stop doing
53 * anything when there are too many descriptors.
55 tu_cs_emit_pkt7(cs
, opcode
, 3);
57 CP_LOAD_STATE6_0_STATE_TYPE(st
) |
58 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS
) |
59 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
60 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count
, 1024-1)));
61 tu_cs_emit_qw(cs
, offset
| (base
<< 28));
65 tu6_load_state_size(struct tu_pipeline
*pipeline
, bool compute
)
67 const unsigned load_state_size
= 4;
69 for (unsigned i
= 0; i
< pipeline
->layout
->num_sets
; i
++) {
70 if (pipeline
&& !(pipeline
->active_desc_sets
& (1u << i
)))
73 struct tu_descriptor_set_layout
*set_layout
= pipeline
->layout
->set
[i
].layout
;
74 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
75 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
77 /* Note: some users, like amber for example, pass in
78 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
79 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
81 VkShaderStageFlags stages
= compute
?
82 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
83 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
84 unsigned stage_count
= util_bitcount(stages
);
86 if (!binding
->array_size
)
89 switch (binding
->type
) {
90 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
91 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
92 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
93 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
94 /* IBO-backed resources only need one packet for all graphics stages */
95 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
)
97 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)
100 case VK_DESCRIPTOR_TYPE_SAMPLER
:
101 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
102 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
103 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
104 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
105 /* Textures and UBO's needs a packet for each stage */
108 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
109 /* Because of how we pack combined images and samplers, we
110 * currently can't use one packet for the whole array.
112 count
= stage_count
* binding
->array_size
* 2;
114 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
117 unreachable("bad descriptor type");
119 size
+= count
* load_state_size
;
126 tu6_emit_load_state(struct tu_pipeline
*pipeline
, bool compute
)
128 unsigned size
= tu6_load_state_size(pipeline
, compute
);
133 tu_cs_begin_sub_stream(&pipeline
->cs
, size
, &cs
);
135 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
136 for (unsigned i
= 0; i
< layout
->num_sets
; i
++) {
137 /* From 13.2.7. Descriptor Set Binding:
139 * A compatible descriptor set must be bound for all set numbers that
140 * any shaders in a pipeline access, at the time that a draw or
141 * dispatch command is recorded to execute using that pipeline.
142 * However, if none of the shaders in a pipeline statically use any
143 * bindings with a particular set number, then no descriptor set need
144 * be bound for that set number, even if the pipeline layout includes
145 * a non-trivial descriptor set layout for that set number.
147 * This means that descriptor sets unused by the pipeline may have a
148 * garbage or 0 BINDLESS_BASE register, which will cause context faults
149 * when prefetching descriptors from these sets. Skip prefetching for
150 * descriptors from them to avoid this. This is also an optimization,
151 * since these prefetches would be useless.
153 if (!(pipeline
->active_desc_sets
& (1u << i
)))
156 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[i
].layout
;
157 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
158 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
160 unsigned offset
= binding
->offset
/ 4;
161 /* Note: some users, like amber for example, pass in
162 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
163 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
165 VkShaderStageFlags stages
= compute
?
166 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
167 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
168 unsigned count
= binding
->array_size
;
169 if (count
== 0 || stages
== 0)
171 switch (binding
->type
) {
172 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
174 offset
= (layout
->set
[i
].dynamic_offset_start
+
175 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
177 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
178 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
179 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
180 /* IBO-backed resources only need one packet for all graphics stages */
181 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
) {
182 emit_load_state(&cs
, CP_LOAD_STATE6
, ST6_SHADER
, SB6_IBO
,
183 base
, offset
, count
);
185 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
) {
186 emit_load_state(&cs
, CP_LOAD_STATE6_FRAG
, ST6_IBO
, SB6_CS_SHADER
,
187 base
, offset
, count
);
190 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
191 /* nothing - input attachment doesn't use bindless */
193 case VK_DESCRIPTOR_TYPE_SAMPLER
:
194 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
195 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
: {
196 tu_foreach_stage(stage
, stages
) {
197 emit_load_state(&cs
, tu6_stage2opcode(stage
),
198 binding
->type
== VK_DESCRIPTOR_TYPE_SAMPLER
?
199 ST6_SHADER
: ST6_CONSTANTS
,
200 tu6_stage2texsb(stage
), base
, offset
, count
);
204 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
206 offset
= (layout
->set
[i
].dynamic_offset_start
+
207 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
209 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
: {
210 tu_foreach_stage(stage
, stages
) {
211 emit_load_state(&cs
, tu6_stage2opcode(stage
), ST6_UBO
,
212 tu6_stage2shadersb(stage
), base
, offset
, count
);
216 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
: {
217 tu_foreach_stage(stage
, stages
) {
218 /* TODO: We could emit less CP_LOAD_STATE6 if we used
219 * struct-of-arrays instead of array-of-structs.
221 for (unsigned i
= 0; i
< count
; i
++) {
222 unsigned tex_offset
= offset
+ 2 * i
* A6XX_TEX_CONST_DWORDS
;
223 unsigned sam_offset
= offset
+ (2 * i
+ 1) * A6XX_TEX_CONST_DWORDS
;
224 emit_load_state(&cs
, tu6_stage2opcode(stage
),
225 ST6_CONSTANTS
, tu6_stage2texsb(stage
),
226 base
, tex_offset
, 1);
227 emit_load_state(&cs
, tu6_stage2opcode(stage
),
228 ST6_SHADER
, tu6_stage2texsb(stage
),
229 base
, sam_offset
, 1);
235 unreachable("bad descriptor type");
240 pipeline
->load_state
= tu_cs_end_draw_state(&pipeline
->cs
, &cs
);
243 struct tu_pipeline_builder
245 struct tu_device
*device
;
246 struct tu_pipeline_cache
*cache
;
247 struct tu_pipeline_layout
*layout
;
248 const VkAllocationCallbacks
*alloc
;
249 const VkGraphicsPipelineCreateInfo
*create_info
;
251 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
252 struct ir3_shader_variant
*variants
[MESA_SHADER_STAGES
];
253 struct ir3_shader_variant
*binning_variant
;
254 uint64_t shader_iova
[MESA_SHADER_STAGES
];
255 uint64_t binning_vs_iova
;
257 bool rasterizer_discard
;
258 /* these states are affectd by rasterizer_discard */
259 VkSampleCountFlagBits samples
;
260 bool use_color_attachments
;
261 bool use_dual_src_blend
;
262 uint32_t color_attachment_count
;
263 VkFormat color_attachment_formats
[MAX_RTS
];
264 VkFormat depth_attachment_format
;
265 uint32_t render_components
;
269 tu_logic_op_reads_dst(VkLogicOp op
)
272 case VK_LOGIC_OP_CLEAR
:
273 case VK_LOGIC_OP_COPY
:
274 case VK_LOGIC_OP_COPY_INVERTED
:
275 case VK_LOGIC_OP_SET
:
283 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
285 /* treat dst alpha as 1.0 and avoid reading it */
287 case VK_BLEND_FACTOR_DST_ALPHA
:
288 return VK_BLEND_FACTOR_ONE
;
289 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
290 return VK_BLEND_FACTOR_ZERO
;
296 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor
)
299 case VK_BLEND_FACTOR_SRC1_COLOR
:
300 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
301 case VK_BLEND_FACTOR_SRC1_ALPHA
:
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
310 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo
*info
)
315 for (unsigned i
= 0; i
< info
->attachmentCount
; i
++) {
316 const VkPipelineColorBlendAttachmentState
*blend
= &info
->pAttachments
[i
];
317 if (tu_blend_factor_is_dual_src(blend
->srcColorBlendFactor
) ||
318 tu_blend_factor_is_dual_src(blend
->dstColorBlendFactor
) ||
319 tu_blend_factor_is_dual_src(blend
->srcAlphaBlendFactor
) ||
320 tu_blend_factor_is_dual_src(blend
->dstAlphaBlendFactor
))
328 tu6_emit_xs_config(struct tu_cs
*cs
,
329 gl_shader_stage stage
, /* xs->type, but xs may be NULL */
330 const struct ir3_shader_variant
*xs
,
331 uint64_t binary_iova
)
333 static const struct xs_config
{
334 uint16_t reg_sp_xs_ctrl
;
335 uint16_t reg_sp_xs_config
;
336 uint16_t reg_hlsq_xs_ctrl
;
337 uint16_t reg_sp_vs_obj_start
;
339 [MESA_SHADER_VERTEX
] = {
340 REG_A6XX_SP_VS_CTRL_REG0
,
341 REG_A6XX_SP_VS_CONFIG
,
342 REG_A6XX_HLSQ_VS_CNTL
,
343 REG_A6XX_SP_VS_OBJ_START_LO
,
345 [MESA_SHADER_TESS_CTRL
] = {
346 REG_A6XX_SP_HS_CTRL_REG0
,
347 REG_A6XX_SP_HS_CONFIG
,
348 REG_A6XX_HLSQ_HS_CNTL
,
349 REG_A6XX_SP_HS_OBJ_START_LO
,
351 [MESA_SHADER_TESS_EVAL
] = {
352 REG_A6XX_SP_DS_CTRL_REG0
,
353 REG_A6XX_SP_DS_CONFIG
,
354 REG_A6XX_HLSQ_DS_CNTL
,
355 REG_A6XX_SP_DS_OBJ_START_LO
,
357 [MESA_SHADER_GEOMETRY
] = {
358 REG_A6XX_SP_GS_CTRL_REG0
,
359 REG_A6XX_SP_GS_CONFIG
,
360 REG_A6XX_HLSQ_GS_CNTL
,
361 REG_A6XX_SP_GS_OBJ_START_LO
,
363 [MESA_SHADER_FRAGMENT
] = {
364 REG_A6XX_SP_FS_CTRL_REG0
,
365 REG_A6XX_SP_FS_CONFIG
,
366 REG_A6XX_HLSQ_FS_CNTL
,
367 REG_A6XX_SP_FS_OBJ_START_LO
,
369 [MESA_SHADER_COMPUTE
] = {
370 REG_A6XX_SP_CS_CTRL_REG0
,
371 REG_A6XX_SP_CS_CONFIG
,
372 REG_A6XX_HLSQ_CS_CNTL
,
373 REG_A6XX_SP_CS_OBJ_START_LO
,
376 const struct xs_config
*cfg
= &xs_config
[stage
];
379 /* shader stage disabled */
380 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_config
, 1);
383 tu_cs_emit_pkt4(cs
, cfg
->reg_hlsq_xs_ctrl
, 1);
388 bool is_fs
= xs
->type
== MESA_SHADER_FRAGMENT
;
389 enum a3xx_threadsize threadsize
= FOUR_QUADS
;
392 * the "threadsize" field may have nothing to do with threadsize,
393 * use a value that matches the blob until it is figured out
395 if (xs
->type
== MESA_SHADER_GEOMETRY
)
396 threadsize
= TWO_QUADS
;
398 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_ctrl
, 1);
400 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize
) |
401 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs
->info
.max_reg
+ 1) |
402 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs
->info
.max_half_reg
+ 1) |
403 COND(xs
->mergedregs
, A6XX_SP_VS_CTRL_REG0_MERGEDREGS
) |
404 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs
->branchstack
) |
405 COND(xs
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
) |
406 COND(xs
->need_fine_derivatives
, A6XX_SP_VS_CTRL_REG0_DIFF_FINE
) |
407 /* only fragment shader sets VARYING bit */
408 COND(xs
->total_in
&& is_fs
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
409 /* unknown bit, seems unnecessary */
410 COND(is_fs
, 0x1000000));
412 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_config
, 2);
413 tu_cs_emit(cs
, A6XX_SP_VS_CONFIG_ENABLED
|
414 COND(xs
->bindless_tex
, A6XX_SP_VS_CONFIG_BINDLESS_TEX
) |
415 COND(xs
->bindless_samp
, A6XX_SP_VS_CONFIG_BINDLESS_SAMP
) |
416 COND(xs
->bindless_ibo
, A6XX_SP_VS_CONFIG_BINDLESS_IBO
) |
417 COND(xs
->bindless_ubo
, A6XX_SP_VS_CONFIG_BINDLESS_UBO
) |
418 A6XX_SP_VS_CONFIG_NTEX(xs
->num_samp
) |
419 A6XX_SP_VS_CONFIG_NSAMP(xs
->num_samp
));
420 tu_cs_emit(cs
, xs
->instrlen
);
422 tu_cs_emit_pkt4(cs
, cfg
->reg_hlsq_xs_ctrl
, 1);
423 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs
->constlen
) |
424 A6XX_HLSQ_VS_CNTL_ENABLED
);
426 /* emit program binary
427 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
430 assert((binary_iova
& 0x7f) == 0);
432 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_vs_obj_start
, 2);
433 tu_cs_emit_qw(cs
, binary_iova
);
435 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(stage
), 3);
436 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
437 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
438 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
439 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage
)) |
440 CP_LOAD_STATE6_0_NUM_UNIT(xs
->instrlen
));
441 tu_cs_emit_qw(cs
, binary_iova
);
443 /* emit immediates */
445 const struct ir3_const_state
*const_state
= ir3_const_state(xs
);
446 uint32_t base
= const_state
->offsets
.immediate
;
447 int size
= const_state
->immediates_count
;
449 /* truncate size to avoid writing constants that shader
452 size
= MIN2(size
+ base
, xs
->constlen
) - base
;
457 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(stage
), 3 + size
* 4);
458 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
459 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
460 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
461 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage
)) |
462 CP_LOAD_STATE6_0_NUM_UNIT(size
));
463 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
464 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
466 for (unsigned i
= 0; i
< size
; i
++) {
467 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
468 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
469 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
470 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
475 tu6_emit_cs_config(struct tu_cs
*cs
, const struct tu_shader
*shader
,
476 const struct ir3_shader_variant
*v
,
477 uint32_t binary_iova
)
479 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(
483 tu6_emit_xs_config(cs
, MESA_SHADER_COMPUTE
, v
, binary_iova
);
485 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
486 tu_cs_emit(cs
, 0x41);
488 uint32_t local_invocation_id
=
489 ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
490 uint32_t work_group_id
=
491 ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
493 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
495 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
496 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
497 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
498 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
499 tu_cs_emit(cs
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
503 tu6_emit_vs_system_values(struct tu_cs
*cs
,
504 const struct ir3_shader_variant
*vs
,
505 const struct ir3_shader_variant
*hs
,
506 const struct ir3_shader_variant
*ds
,
507 const struct ir3_shader_variant
*gs
,
508 bool primid_passthru
)
510 const uint32_t vertexid_regid
=
511 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
512 const uint32_t instanceid_regid
=
513 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
514 const uint32_t tess_coord_x_regid
= hs
?
515 ir3_find_sysval_regid(ds
, SYSTEM_VALUE_TESS_COORD
) :
517 const uint32_t tess_coord_y_regid
= VALIDREG(tess_coord_x_regid
) ?
518 tess_coord_x_regid
+ 1 :
520 const uint32_t hs_patch_regid
= hs
?
521 ir3_find_sysval_regid(hs
, SYSTEM_VALUE_PRIMITIVE_ID
) :
523 const uint32_t ds_patch_regid
= hs
?
524 ir3_find_sysval_regid(ds
, SYSTEM_VALUE_PRIMITIVE_ID
) :
526 const uint32_t hs_invocation_regid
= hs
?
527 ir3_find_sysval_regid(hs
, SYSTEM_VALUE_TCS_HEADER_IR3
) :
529 const uint32_t primitiveid_regid
= gs
?
530 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
) :
532 const uint32_t gsheader_regid
= gs
?
533 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_GS_HEADER_IR3
) :
536 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
537 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
538 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
539 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid
) |
541 tu_cs_emit(cs
, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid
) |
542 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid
));
543 tu_cs_emit(cs
, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid
) |
544 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid
) |
545 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid
) |
547 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
548 tu_cs_emit(cs
, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid
) |
549 0xfc00); /* VFD_CONTROL_5 */
550 tu_cs_emit(cs
, COND(primid_passthru
, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU
)); /* VFD_CONTROL_6 */
553 /* Add any missing varyings needed for stream-out. Otherwise varyings not
554 * used by fragment shader will be stripped out.
557 tu6_link_streamout(struct ir3_shader_linkage
*l
,
558 const struct ir3_shader_variant
*v
)
560 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
563 * First, any stream-out varyings not already in linkage map (ie. also
564 * consumed by frag shader) need to be added:
566 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
567 const struct ir3_stream_output
*out
= &info
->output
[i
];
569 (1 << (out
->num_components
+ out
->start_component
)) - 1;
570 unsigned k
= out
->register_index
;
571 unsigned idx
, nextloc
= 0;
573 /* psize/pos need to be the last entries in linkage map, and will
574 * get added link_stream_out, so skip over them:
576 if (v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
||
577 v
->outputs
[k
].slot
== VARYING_SLOT_POS
)
580 for (idx
= 0; idx
< l
->cnt
; idx
++) {
581 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
583 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
586 /* add if not already in linkage map: */
588 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
590 /* expand component-mask if needed, ie streaming out all components
591 * but frag shader doesn't consume all components:
593 if (compmask
& ~l
->var
[idx
].compmask
) {
594 l
->var
[idx
].compmask
|= compmask
;
595 l
->max_loc
= MAX2(l
->max_loc
, l
->var
[idx
].loc
+
596 util_last_bit(l
->var
[idx
].compmask
));
602 tu6_setup_streamout(struct tu_cs
*cs
,
603 const struct ir3_shader_variant
*v
,
604 struct ir3_shader_linkage
*l
)
606 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
607 uint32_t prog
[IR3_MAX_SO_OUTPUTS
* 2] = {};
608 uint32_t ncomp
[IR3_MAX_SO_BUFFERS
] = {};
609 uint32_t prog_count
= align(l
->max_loc
, 2) / 2;
611 /* TODO: streamout state should be in a non-GMEM draw state */
614 if (info
->num_outputs
== 0) {
615 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
616 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
618 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
623 /* is there something to do with info->stride[i]? */
625 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
626 const struct ir3_stream_output
*out
= &info
->output
[i
];
627 unsigned k
= out
->register_index
;
630 /* Skip it, if there's an unused reg in the middle of outputs. */
631 if (v
->outputs
[k
].regid
== INVALID_REG
)
634 ncomp
[out
->output_buffer
] += out
->num_components
;
636 /* linkage map sorted by order frag shader wants things, so
637 * a bit less ideal here..
639 for (idx
= 0; idx
< l
->cnt
; idx
++)
640 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
643 debug_assert(idx
< l
->cnt
);
645 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
646 unsigned c
= j
+ out
->start_component
;
647 unsigned loc
= l
->var
[idx
].loc
+ c
;
648 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
651 prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
652 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
653 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
655 prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
656 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
657 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
662 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + 2 * prog_count
);
663 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
664 tu_cs_emit(cs
, A6XX_VPC_SO_BUF_CNTL_ENABLE
|
665 COND(ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
666 COND(ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
667 COND(ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
668 COND(ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
));
669 for (uint32_t i
= 0; i
< 4; i
++) {
670 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(i
));
671 tu_cs_emit(cs
, ncomp
[i
]);
673 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
674 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
675 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
676 for (uint32_t i
= 0; i
< prog_count
; i
++) {
677 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
678 tu_cs_emit(cs
, prog
[i
]);
683 tu6_emit_const(struct tu_cs
*cs
, uint32_t opcode
, uint32_t base
,
684 enum a6xx_state_block block
, uint32_t offset
,
685 uint32_t size
, uint32_t *dwords
) {
686 assert(size
% 4 == 0);
688 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
);
689 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
690 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
691 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
692 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
693 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 4));
695 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
696 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
697 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
699 tu_cs_emit_array(cs
, dwords
, size
);
703 tu6_emit_link_map(struct tu_cs
*cs
,
704 const struct ir3_shader_variant
*producer
,
705 const struct ir3_shader_variant
*consumer
,
706 enum a6xx_state_block sb
)
708 const struct ir3_const_state
*const_state
= ir3_const_state(consumer
);
709 uint32_t base
= const_state
->offsets
.primitive_map
;
710 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
711 num_loc
= ir3_link_geometry_stages(producer
, consumer
, patch_locs
);
712 int size
= DIV_ROUND_UP(num_loc
, 4);
714 size
= (MIN2(size
+ base
, consumer
->constlen
) - base
) * 4;
718 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, base
, sb
, 0, size
,
723 gl_primitive_to_tess(uint16_t primitive
) {
729 case GL_TRIANGLE_STRIP
:
737 tu6_emit_vpc(struct tu_cs
*cs
,
738 const struct ir3_shader_variant
*vs
,
739 const struct ir3_shader_variant
*hs
,
740 const struct ir3_shader_variant
*ds
,
741 const struct ir3_shader_variant
*gs
,
742 const struct ir3_shader_variant
*fs
)
744 /* note: doesn't compile as static because of the array regs.. */
745 const struct reg_config
{
746 uint16_t reg_sp_xs_out_reg
;
747 uint16_t reg_sp_xs_vpc_dst_reg
;
748 uint16_t reg_vpc_xs_pack
;
749 uint16_t reg_vpc_xs_clip_cntl
;
750 uint16_t reg_gras_xs_cl_cntl
;
751 uint16_t reg_pc_xs_out_cntl
;
752 uint16_t reg_sp_xs_primitive_cntl
;
753 uint16_t reg_vpc_xs_layer_cntl
;
754 uint16_t reg_gras_xs_layer_cntl
;
756 [MESA_SHADER_VERTEX
] = {
757 REG_A6XX_SP_VS_OUT_REG(0),
758 REG_A6XX_SP_VS_VPC_DST_REG(0),
759 REG_A6XX_VPC_VS_PACK
,
760 REG_A6XX_VPC_VS_CLIP_CNTL
,
761 REG_A6XX_GRAS_VS_CL_CNTL
,
762 REG_A6XX_PC_VS_OUT_CNTL
,
763 REG_A6XX_SP_VS_PRIMITIVE_CNTL
,
764 REG_A6XX_VPC_VS_LAYER_CNTL
,
765 REG_A6XX_GRAS_VS_LAYER_CNTL
767 [MESA_SHADER_TESS_EVAL
] = {
768 REG_A6XX_SP_DS_OUT_REG(0),
769 REG_A6XX_SP_DS_VPC_DST_REG(0),
770 REG_A6XX_VPC_DS_PACK
,
771 REG_A6XX_VPC_DS_CLIP_CNTL
,
772 REG_A6XX_GRAS_DS_CL_CNTL
,
773 REG_A6XX_PC_DS_OUT_CNTL
,
774 REG_A6XX_SP_DS_PRIMITIVE_CNTL
,
775 REG_A6XX_VPC_DS_LAYER_CNTL
,
776 REG_A6XX_GRAS_DS_LAYER_CNTL
778 [MESA_SHADER_GEOMETRY
] = {
779 REG_A6XX_SP_GS_OUT_REG(0),
780 REG_A6XX_SP_GS_VPC_DST_REG(0),
781 REG_A6XX_VPC_GS_PACK
,
782 REG_A6XX_VPC_GS_CLIP_CNTL
,
783 REG_A6XX_GRAS_GS_CL_CNTL
,
784 REG_A6XX_PC_GS_OUT_CNTL
,
785 REG_A6XX_SP_GS_PRIMITIVE_CNTL
,
786 REG_A6XX_VPC_GS_LAYER_CNTL
,
787 REG_A6XX_GRAS_GS_LAYER_CNTL
791 const struct ir3_shader_variant
*last_shader
;
800 const struct reg_config
*cfg
= ®_config
[last_shader
->type
];
802 struct ir3_shader_linkage linkage
= { .primid_loc
= 0xff };
804 ir3_link_shaders(&linkage
, last_shader
, fs
, true);
806 if (last_shader
->shader
->stream_output
.num_outputs
)
807 tu6_link_streamout(&linkage
, last_shader
);
809 /* We do this after linking shaders in order to know whether PrimID
810 * passthrough needs to be enabled.
812 bool primid_passthru
= linkage
.primid_loc
!= 0xff;
813 tu6_emit_vs_system_values(cs
, vs
, hs
, ds
, gs
, primid_passthru
);
815 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
816 tu_cs_emit(cs
, ~linkage
.varmask
[0]);
817 tu_cs_emit(cs
, ~linkage
.varmask
[1]);
818 tu_cs_emit(cs
, ~linkage
.varmask
[2]);
819 tu_cs_emit(cs
, ~linkage
.varmask
[3]);
821 /* a6xx finds position/pointsize at the end */
822 const uint32_t position_regid
=
823 ir3_find_output_regid(last_shader
, VARYING_SLOT_POS
);
824 const uint32_t pointsize_regid
=
825 ir3_find_output_regid(last_shader
, VARYING_SLOT_PSIZ
);
826 const uint32_t layer_regid
=
827 ir3_find_output_regid(last_shader
, VARYING_SLOT_LAYER
);
828 uint32_t primitive_regid
= gs
?
829 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
) : regid(63, 0);
830 uint32_t flags_regid
= gs
?
831 ir3_find_output_regid(gs
, VARYING_SLOT_GS_VERTEX_FLAGS_IR3
) : 0;
833 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff, layer_loc
= 0xff;
834 if (layer_regid
!= regid(63, 0)) {
835 layer_loc
= linkage
.max_loc
;
836 ir3_link_add(&linkage
, layer_regid
, 0x1, linkage
.max_loc
);
838 if (position_regid
!= regid(63, 0)) {
839 position_loc
= linkage
.max_loc
;
840 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
842 if (pointsize_regid
!= regid(63, 0)) {
843 pointsize_loc
= linkage
.max_loc
;
844 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
847 tu6_setup_streamout(cs
, last_shader
, &linkage
);
849 /* map outputs of the last shader to VPC */
850 assert(linkage
.cnt
<= 32);
851 const uint32_t sp_out_count
= DIV_ROUND_UP(linkage
.cnt
, 2);
852 const uint32_t sp_vpc_dst_count
= DIV_ROUND_UP(linkage
.cnt
, 4);
854 uint32_t sp_vpc_dst
[8];
855 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
856 ((uint16_t *) sp_out
)[i
] =
857 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
858 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
859 ((uint8_t *) sp_vpc_dst
)[i
] =
860 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
863 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_out_reg
, sp_out_count
);
864 tu_cs_emit_array(cs
, sp_out
, sp_out_count
);
866 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_vpc_dst_reg
, sp_vpc_dst_count
);
867 tu_cs_emit_array(cs
, sp_vpc_dst
, sp_vpc_dst_count
);
869 tu_cs_emit_pkt4(cs
, cfg
->reg_vpc_xs_pack
, 1);
870 tu_cs_emit(cs
, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc
) |
871 A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc
) |
872 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
874 tu_cs_emit_pkt4(cs
, cfg
->reg_vpc_xs_clip_cntl
, 1);
875 tu_cs_emit(cs
, 0xffff00);
877 tu_cs_emit_pkt4(cs
, cfg
->reg_gras_xs_cl_cntl
, 1);
880 tu_cs_emit_pkt4(cs
, cfg
->reg_pc_xs_out_cntl
, 1);
881 tu_cs_emit(cs
, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage
.max_loc
) |
882 CONDREG(pointsize_regid
, A6XX_PC_VS_OUT_CNTL_PSIZE
) |
883 CONDREG(layer_regid
, A6XX_PC_VS_OUT_CNTL_LAYER
) |
884 CONDREG(primitive_regid
, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID
));
886 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_primitive_cntl
, 1);
887 tu_cs_emit(cs
, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage
.cnt
) |
888 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid
));
890 tu_cs_emit_pkt4(cs
, cfg
->reg_vpc_xs_layer_cntl
, 1);
891 tu_cs_emit(cs
, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc
) | 0xff00);
893 tu_cs_emit_pkt4(cs
, cfg
->reg_gras_xs_layer_cntl
, 1);
894 tu_cs_emit(cs
, CONDREG(layer_regid
, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER
));
896 tu_cs_emit_regs(cs
, A6XX_PC_PRIMID_PASSTHRU(primid_passthru
));
898 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
899 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
? fs
->total_in
: 0) |
900 COND(fs
&& fs
->total_in
, A6XX_VPC_CNTL_0_VARYING
) |
901 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage
.primid_loc
) |
902 A6XX_VPC_CNTL_0_UNKLOC(0xff));
905 shader_info
*hs_info
= &hs
->shader
->nir
->info
;
906 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_TESS_NUM_VERTEX
, 1);
907 tu_cs_emit(cs
, hs_info
->tess
.tcs_vertices_out
);
909 /* Total attribute slots in HS incoming patch. */
910 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9801
, 1);
912 hs_info
->tess
.tcs_vertices_out
* vs
->output_size
/ 4);
914 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
915 tu_cs_emit(cs
, vs
->output_size
);
916 /* In SPIR-V generated from GLSL, the tessellation primitive params are
917 * are specified in the tess eval shader, but in SPIR-V generated from
918 * HLSL, they are specified in the tess control shader. */
919 shader_info
*tess_info
=
920 ds
->shader
->nir
->info
.tess
.spacing
== TESS_SPACING_UNSPECIFIED
?
921 &hs
->shader
->nir
->info
: &ds
->shader
->nir
->info
;
922 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_TESS_CNTL
, 1);
924 if (tess_info
->tess
.point_mode
)
925 output
= TESS_POINTS
;
926 else if (tess_info
->tess
.primitive_mode
== GL_ISOLINES
)
928 else if (tess_info
->tess
.ccw
)
929 output
= TESS_CCW_TRIS
;
931 output
= TESS_CW_TRIS
;
933 enum a6xx_tess_spacing spacing
;
934 switch (tess_info
->tess
.spacing
) {
935 case TESS_SPACING_EQUAL
:
936 spacing
= TESS_EQUAL
;
938 case TESS_SPACING_FRACTIONAL_ODD
:
939 spacing
= TESS_FRACTIONAL_ODD
;
941 case TESS_SPACING_FRACTIONAL_EVEN
:
942 spacing
= TESS_FRACTIONAL_EVEN
;
944 case TESS_SPACING_UNSPECIFIED
:
946 unreachable("invalid tess spacing");
948 tu_cs_emit(cs
, A6XX_PC_TESS_CNTL_SPACING(spacing
) |
949 A6XX_PC_TESS_CNTL_OUTPUT(output
));
951 tu6_emit_link_map(cs
, vs
, hs
, SB6_HS_SHADER
);
952 tu6_emit_link_map(cs
, hs
, ds
, SB6_DS_SHADER
);
957 uint32_t vertices_out
, invocations
, output
, vec4_size
;
958 /* this detects the tu_clear_blit path, which doesn't set ->nir */
959 if (gs
->shader
->nir
) {
961 tu6_emit_link_map(cs
, ds
, gs
, SB6_GS_SHADER
);
963 tu6_emit_link_map(cs
, vs
, gs
, SB6_GS_SHADER
);
965 vertices_out
= gs
->shader
->nir
->info
.gs
.vertices_out
- 1;
966 output
= gl_primitive_to_tess(gs
->shader
->nir
->info
.gs
.output_primitive
);
967 invocations
= gs
->shader
->nir
->info
.gs
.invocations
- 1;
968 /* Size of per-primitive alloction in ldlw memory in vec4s. */
969 vec4_size
= gs
->shader
->nir
->info
.gs
.vertices_in
*
970 DIV_ROUND_UP(vs
->output_size
, 4);
973 output
= TESS_CW_TRIS
;
978 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_5
, 1);
980 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out
) |
981 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output
) |
982 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations
));
984 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_3
, 1);
987 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9100
, 1);
988 tu_cs_emit(cs
, 0xff);
990 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
991 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size
));
993 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 1);
996 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_PRIM_SIZE
, 1);
997 tu_cs_emit(cs
, vs
->output_size
);
1002 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
1004 uint8_t *interp_mode
,
1005 uint8_t *ps_repl_mode
)
1019 PS_REPL_ONE_MINUS_T
= 3,
1022 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
1024 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1025 * fourth component occupy three consecutive varying slots
1030 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
1031 if (compmask
& 0x1) {
1032 *ps_repl_mode
|= PS_REPL_S
<< shift
;
1035 if (compmask
& 0x2) {
1036 *ps_repl_mode
|= PS_REPL_T
<< shift
;
1039 if (compmask
& 0x4) {
1040 *interp_mode
|= INTERP_ZERO
<< shift
;
1043 if (compmask
& 0x8) {
1044 *interp_mode
|= INTERP_ONE
<< 6;
1047 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
1048 fs
->inputs
[index
].rasterflat
) {
1049 for (int i
= 0; i
< 4; i
++) {
1050 if (compmask
& (1 << i
)) {
1051 *interp_mode
|= INTERP_FLAT
<< shift
;
1061 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
1062 const struct ir3_shader_variant
*fs
)
1064 uint32_t interp_modes
[8] = { 0 };
1065 uint32_t ps_repl_modes
[8] = { 0 };
1069 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
1071 /* get the mode for input i */
1072 uint8_t interp_mode
;
1073 uint8_t ps_repl_mode
;
1075 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
1077 /* OR the mode into the array */
1078 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
1079 uint32_t n
= inloc
/ 32;
1080 uint32_t shift
= inloc
% 32;
1081 interp_modes
[n
] |= interp_mode
<< shift
;
1082 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
1083 if (shift
+ bits
> 32) {
1087 interp_modes
[n
] |= interp_mode
>> shift
;
1088 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
1093 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1094 tu_cs_emit_array(cs
, interp_modes
, 8);
1096 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1097 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
1101 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
1103 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
1104 uint32_t ij_regid
[IJ_COUNT
];
1105 uint32_t smask_in_regid
;
1107 bool sample_shading
= fs
->per_samp
| fs
->key
.sample_shading
;
1108 bool enable_varyings
= fs
->total_in
> 0;
1110 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
1111 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
1112 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
1113 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
1114 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
1115 for (unsigned i
= 0; i
< ARRAY_SIZE(ij_regid
); i
++)
1116 ij_regid
[i
] = ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
+ i
);
1118 if (VALIDREG(ij_regid
[IJ_LINEAR_SAMPLE
]))
1119 tu_finishme("linear sample varying");
1121 if (VALIDREG(ij_regid
[IJ_LINEAR_CENTROID
]))
1122 tu_finishme("linear centroid varying");
1124 if (fs
->num_sampler_prefetch
> 0) {
1125 assert(VALIDREG(ij_regid
[IJ_PERSP_PIXEL
]));
1126 /* also, it seems like ij_pix is *required* to be r0.x */
1127 assert(ij_regid
[IJ_PERSP_PIXEL
] == regid(0, 0));
1130 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
1131 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
1132 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1134 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1135 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1136 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
1137 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
1138 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
1139 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
1140 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
1141 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
1142 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
1145 if (fs
->num_sampler_prefetch
> 0) {
1146 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs
->num_sampler_prefetch
);
1147 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1148 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1150 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_bindless_id
) |
1151 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch
->tex_bindless_id
));
1155 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
1156 tu_cs_emit(cs
, 0x7);
1157 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
1158 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
1159 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
1160 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid
[IJ_PERSP_SIZE
]));
1161 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid
[IJ_PERSP_PIXEL
]) |
1162 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid
[IJ_LINEAR_PIXEL
]) |
1163 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid
[IJ_PERSP_CENTROID
]) |
1164 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid
[IJ_LINEAR_CENTROID
]));
1165 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
1166 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
1167 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid
[IJ_PERSP_SAMPLE
]) |
1168 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid
[IJ_LINEAR_SAMPLE
]));
1169 tu_cs_emit(cs
, 0xfc);
1171 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
1172 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
1174 bool need_size
= fs
->frag_face
|| fs
->fragcoord_compmask
!= 0;
1175 bool need_size_persamp
= false;
1176 if (VALIDREG(ij_regid
[IJ_PERSP_SIZE
])) {
1178 need_size_persamp
= true;
1182 if (VALIDREG(ij_regid
[IJ_LINEAR_PIXEL
]))
1185 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
1187 CONDREG(ij_regid
[IJ_PERSP_PIXEL
], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL
) |
1188 CONDREG(ij_regid
[IJ_PERSP_CENTROID
], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID
) |
1189 CONDREG(ij_regid
[IJ_PERSP_SAMPLE
], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE
) |
1190 COND(need_size
, A6XX_GRAS_CNTL_SIZE
) |
1191 COND(need_size_persamp
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
1192 COND(fs
->fragcoord_compmask
!= 0, A6XX_GRAS_CNTL_COORD_MASK(fs
->fragcoord_compmask
)));
1194 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
1196 CONDREG(ij_regid
[IJ_PERSP_PIXEL
], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL
) |
1197 CONDREG(ij_regid
[IJ_PERSP_CENTROID
], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID
) |
1198 CONDREG(ij_regid
[IJ_PERSP_SAMPLE
], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE
) |
1199 COND(need_size
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
1200 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
1201 COND(need_size_persamp
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
1202 COND(fs
->fragcoord_compmask
!= 0,
1203 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs
->fragcoord_compmask
)));
1205 /* these two bits (UNK4/UNK5) relate to fragcoord
1206 * without them, fragcoord is the same for all samples
1208 COND(sample_shading
, A6XX_RB_RENDER_CONTROL1_UNK4
) |
1209 COND(sample_shading
, A6XX_RB_RENDER_CONTROL1_UNK5
) |
1210 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
1211 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
1212 CONDREG(ij_regid
[IJ_PERSP_SIZE
], A6XX_RB_RENDER_CONTROL1_SIZE
) |
1213 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
1215 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
1216 tu_cs_emit(cs
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
1218 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
1219 tu_cs_emit(cs
, COND(sample_shading
, 0x6)); // XXX
1221 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
1222 tu_cs_emit(cs
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
1226 tu6_emit_fs_outputs(struct tu_cs
*cs
,
1227 const struct ir3_shader_variant
*fs
,
1228 uint32_t mrt_count
, bool dual_src_blend
,
1229 uint32_t render_components
,
1232 uint32_t smask_regid
, posz_regid
, stencilref_regid
;
1234 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
1235 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
1236 stencilref_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_STENCIL
);
1238 uint32_t fragdata_regid
[8];
1239 if (fs
->color0_mrt
) {
1240 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
1241 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1242 fragdata_regid
[i
] = fragdata_regid
[0];
1244 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1245 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
1248 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
1249 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
1250 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
1251 A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid
) |
1252 COND(dual_src_blend
, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE
));
1253 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1255 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1256 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
1257 // TODO we could have a mix of half and full precision outputs,
1258 // we really need to figure out half-precision from IR3_REG_HALF
1259 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
1260 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
1264 A6XX_SP_FS_RENDER_COMPONENTS(.dword
= render_components
));
1266 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
1267 tu_cs_emit(cs
, COND(fs
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
) |
1268 COND(fs
->writes_smask
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK
) |
1269 COND(fs
->writes_stencilref
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF
) |
1270 COND(dual_src_blend
, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE
));
1271 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1274 A6XX_RB_RENDER_COMPONENTS(.dword
= render_components
));
1276 enum a6xx_ztest_mode zmode
;
1278 if (fs
->no_earlyz
|| fs
->has_kill
|| fs
->writes_pos
|| fs
->writes_stencilref
|| is_s8_uint
) {
1279 zmode
= A6XX_LATE_Z
;
1281 zmode
= A6XX_EARLY_Z
;
1284 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
1285 tu_cs_emit(cs
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode
));
1287 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
1288 tu_cs_emit(cs
, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode
));
1292 tu6_emit_geom_tess_consts(struct tu_cs
*cs
,
1293 const struct ir3_shader_variant
*vs
,
1294 const struct ir3_shader_variant
*hs
,
1295 const struct ir3_shader_variant
*ds
,
1296 const struct ir3_shader_variant
*gs
,
1297 uint32_t cps_per_patch
)
1299 uint32_t num_vertices
=
1300 hs
? cps_per_patch
: gs
->shader
->nir
->info
.gs
.vertices_in
;
1302 uint32_t vs_params
[4] = {
1303 vs
->output_size
* num_vertices
* 4, /* vs primitive stride */
1304 vs
->output_size
* 4, /* vs vertex stride */
1308 uint32_t vs_base
= ir3_const_state(vs
)->offsets
.primitive_param
;
1309 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, vs_base
, SB6_VS_SHADER
, 0,
1310 ARRAY_SIZE(vs_params
), vs_params
);
1313 assert(ds
->type
!= MESA_SHADER_NONE
);
1314 uint32_t hs_params
[4] = {
1315 vs
->output_size
* num_vertices
* 4, /* hs primitive stride */
1316 vs
->output_size
* 4, /* hs vertex stride */
1321 uint32_t hs_base
= hs
->const_state
->offsets
.primitive_param
;
1322 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, hs_base
, SB6_HS_SHADER
, 0,
1323 ARRAY_SIZE(hs_params
), hs_params
);
1325 num_vertices
= gs
->shader
->nir
->info
.gs
.vertices_in
;
1327 uint32_t ds_params
[4] = {
1328 ds
->output_size
* num_vertices
* 4, /* ds primitive stride */
1329 ds
->output_size
* 4, /* ds vertex stride */
1330 hs
->output_size
, /* hs vertex stride (dwords) */
1331 hs
->shader
->nir
->info
.tess
.tcs_vertices_out
1334 uint32_t ds_base
= ds
->const_state
->offsets
.primitive_param
;
1335 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, ds_base
, SB6_DS_SHADER
, 0,
1336 ARRAY_SIZE(ds_params
), ds_params
);
1340 const struct ir3_shader_variant
*prev
= ds
? ds
: vs
;
1341 uint32_t gs_params
[4] = {
1342 prev
->output_size
* num_vertices
* 4, /* gs primitive stride */
1343 prev
->output_size
* 4, /* gs vertex stride */
1347 uint32_t gs_base
= gs
->const_state
->offsets
.primitive_param
;
1348 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, gs_base
, SB6_GS_SHADER
, 0,
1349 ARRAY_SIZE(gs_params
), gs_params
);
1354 tu6_emit_program(struct tu_cs
*cs
,
1355 struct tu_pipeline_builder
*builder
,
1358 const struct ir3_shader_variant
*vs
= builder
->variants
[MESA_SHADER_VERTEX
];
1359 const struct ir3_shader_variant
*bs
= builder
->binning_variant
;
1360 const struct ir3_shader_variant
*hs
= builder
->variants
[MESA_SHADER_TESS_CTRL
];
1361 const struct ir3_shader_variant
*ds
= builder
->variants
[MESA_SHADER_TESS_EVAL
];
1362 const struct ir3_shader_variant
*gs
= builder
->variants
[MESA_SHADER_GEOMETRY
];
1363 const struct ir3_shader_variant
*fs
= builder
->variants
[MESA_SHADER_FRAGMENT
];
1364 gl_shader_stage stage
= MESA_SHADER_VERTEX
;
1366 STATIC_ASSERT(MESA_SHADER_VERTEX
== 0);
1368 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(
1376 /* Don't use the binning pass variant when GS is present because we don't
1377 * support compiling correct binning pass variants with GS.
1379 if (binning_pass
&& !gs
) {
1381 tu6_emit_xs_config(cs
, stage
, bs
, builder
->binning_vs_iova
);
1385 for (; stage
< ARRAY_SIZE(builder
->shaders
); stage
++) {
1386 const struct ir3_shader_variant
*xs
= builder
->variants
[stage
];
1388 if (stage
== MESA_SHADER_FRAGMENT
&& binning_pass
)
1391 tu6_emit_xs_config(cs
, stage
, xs
, builder
->shader_iova
[stage
]);
1394 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
1397 tu6_emit_vpc(cs
, vs
, hs
, ds
, gs
, fs
);
1398 tu6_emit_vpc_varying_modes(cs
, fs
);
1401 tu6_emit_fs_inputs(cs
, fs
);
1402 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
,
1403 builder
->use_dual_src_blend
,
1404 builder
->render_components
,
1405 builder
->depth_attachment_format
== VK_FORMAT_S8_UINT
);
1407 /* TODO: check if these can be skipped if fs is disabled */
1408 struct ir3_shader_variant dummy_variant
= {};
1409 tu6_emit_fs_inputs(cs
, &dummy_variant
);
1410 tu6_emit_fs_outputs(cs
, &dummy_variant
, builder
->color_attachment_count
,
1411 builder
->use_dual_src_blend
,
1412 builder
->render_components
,
1413 builder
->depth_attachment_format
== VK_FORMAT_S8_UINT
);
1417 uint32_t cps_per_patch
= builder
->create_info
->pTessellationState
?
1418 builder
->create_info
->pTessellationState
->patchControlPoints
: 0;
1419 tu6_emit_geom_tess_consts(cs
, vs
, hs
, ds
, gs
, cps_per_patch
);
1424 tu6_emit_vertex_input(struct tu_cs
*cs
,
1425 const struct ir3_shader_variant
*vs
,
1426 const VkPipelineVertexInputStateCreateInfo
*info
,
1427 uint32_t *bindings_used
)
1429 uint32_t vfd_decode_idx
= 0;
1430 uint32_t binding_instanced
= 0; /* bitmask of instanced bindings */
1431 uint32_t step_rate
[MAX_VBS
];
1433 for (uint32_t i
= 0; i
< info
->vertexBindingDescriptionCount
; i
++) {
1434 const VkVertexInputBindingDescription
*binding
=
1435 &info
->pVertexBindingDescriptions
[i
];
1438 A6XX_VFD_FETCH_STRIDE(binding
->binding
, binding
->stride
));
1440 if (binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1441 binding_instanced
|= 1 << binding
->binding
;
1443 *bindings_used
|= 1 << binding
->binding
;
1444 step_rate
[binding
->binding
] = 1;
1447 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*div_state
=
1448 vk_find_struct_const(info
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1450 for (uint32_t i
= 0; i
< div_state
->vertexBindingDivisorCount
; i
++) {
1451 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1452 &div_state
->pVertexBindingDivisors
[i
];
1453 step_rate
[desc
->binding
] = desc
->divisor
;
1457 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1459 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
1460 const VkVertexInputAttributeDescription
*attr
=
1461 &info
->pVertexAttributeDescriptions
[i
];
1464 assert(*bindings_used
& BIT(attr
->binding
));
1466 for (input_idx
= 0; input_idx
< vs
->inputs_count
; input_idx
++) {
1467 if ((vs
->inputs
[input_idx
].slot
- VERT_ATTRIB_GENERIC0
) == attr
->location
)
1471 /* attribute not used, skip it */
1472 if (input_idx
== vs
->inputs_count
)
1475 const struct tu_native_format format
= tu6_format_vtx(attr
->format
);
1477 A6XX_VFD_DECODE_INSTR(vfd_decode_idx
,
1478 .idx
= attr
->binding
,
1479 .offset
= attr
->offset
,
1480 .instanced
= binding_instanced
& (1 << attr
->binding
),
1481 .format
= format
.fmt
,
1482 .swap
= format
.swap
,
1484 ._float
= !vk_format_is_int(attr
->format
)),
1485 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx
, step_rate
[attr
->binding
]));
1488 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx
,
1489 .writemask
= vs
->inputs
[input_idx
].compmask
,
1490 .regid
= vs
->inputs
[input_idx
].regid
));
1497 .fetch_cnt
= vfd_decode_idx
, /* decode_cnt for binning pass ? */
1498 .decode_cnt
= vfd_decode_idx
));
1502 tu6_guardband_adj(uint32_t v
)
1505 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1511 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1515 scales
[0] = viewport
->width
/ 2.0f
;
1516 scales
[1] = viewport
->height
/ 2.0f
;
1517 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1518 offsets
[0] = viewport
->x
+ scales
[0];
1519 offsets
[1] = viewport
->y
+ scales
[1];
1520 offsets
[2] = viewport
->minDepth
;
1524 min
.x
= (int32_t) viewport
->x
;
1525 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1526 if (viewport
->height
>= 0.0f
) {
1527 min
.y
= (int32_t) viewport
->y
;
1528 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1530 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1531 max
.y
= (int32_t) ceilf(viewport
->y
);
1533 /* the spec allows viewport->height to be 0.0f */
1536 assert(min
.x
>= 0 && min
.x
< max
.x
);
1537 assert(min
.y
>= 0 && min
.y
< max
.y
);
1539 VkExtent2D guardband_adj
;
1540 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1541 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1544 A6XX_GRAS_CL_VPORT_XOFFSET(0, offsets
[0]),
1545 A6XX_GRAS_CL_VPORT_XSCALE(0, scales
[0]),
1546 A6XX_GRAS_CL_VPORT_YOFFSET(0, offsets
[1]),
1547 A6XX_GRAS_CL_VPORT_YSCALE(0, scales
[1]),
1548 A6XX_GRAS_CL_VPORT_ZOFFSET(0, offsets
[2]),
1549 A6XX_GRAS_CL_VPORT_ZSCALE(0, scales
[2]));
1551 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(0), 2);
1552 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(min
.x
) |
1553 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(min
.y
));
1554 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(max
.x
- 1) |
1555 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(max
.y
- 1));
1557 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1559 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1560 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1562 float z_clamp_min
= MIN2(viewport
->minDepth
, viewport
->maxDepth
);
1563 float z_clamp_max
= MAX2(viewport
->minDepth
, viewport
->maxDepth
);
1566 A6XX_GRAS_CL_Z_CLAMP_MIN(0, z_clamp_min
),
1567 A6XX_GRAS_CL_Z_CLAMP_MAX(0, z_clamp_max
));
1570 A6XX_RB_Z_CLAMP_MIN(z_clamp_min
),
1571 A6XX_RB_Z_CLAMP_MAX(z_clamp_max
));
1575 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1577 VkOffset2D min
= scissor
->offset
;
1579 scissor
->offset
.x
+ scissor
->extent
.width
,
1580 scissor
->offset
.y
+ scissor
->extent
.height
,
1583 /* special case for empty scissor with max == 0 to avoid overflow */
1589 /* avoid overflow with large scissor
1590 * note the max will be limited to min - 1, so that empty scissor works
1592 uint32_t scissor_max
= BITFIELD_MASK(15);
1593 min
.x
= MIN2(scissor_max
, min
.x
);
1594 min
.y
= MIN2(scissor_max
, min
.y
);
1595 max
.x
= MIN2(scissor_max
, max
.x
);
1596 max
.y
= MIN2(scissor_max
, max
.y
);
1599 A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0, .x
= min
.x
, .y
= min
.y
),
1600 A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0, .x
= max
.x
- 1, .y
= max
.y
- 1));
1604 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
)
1607 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 1);
1610 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 1);
1613 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 1);
1618 assert(samp_loc
->sampleLocationsPerPixel
== samp_loc
->sampleLocationsCount
);
1619 assert(samp_loc
->sampleLocationGridSize
.width
== 1);
1620 assert(samp_loc
->sampleLocationGridSize
.height
== 1);
1622 uint32_t sample_config
=
1623 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE
;
1624 uint32_t sample_locations
= 0;
1625 for (uint32_t i
= 0; i
< samp_loc
->sampleLocationsCount
; i
++) {
1627 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc
->pSampleLocations
[i
].x
) |
1628 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc
->pSampleLocations
[i
].y
)) << i
*8;
1631 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 2);
1632 tu_cs_emit(cs
, sample_config
);
1633 tu_cs_emit(cs
, sample_locations
);
1635 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 2);
1636 tu_cs_emit(cs
, sample_config
);
1637 tu_cs_emit(cs
, sample_locations
);
1639 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 2);
1640 tu_cs_emit(cs
, sample_config
);
1641 tu_cs_emit(cs
, sample_locations
);
1645 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1646 VkSampleCountFlagBits samples
)
1648 uint32_t gras_su_cntl
= 0;
1650 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1651 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1652 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1653 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1655 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1656 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1658 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1660 if (rast_info
->depthBiasEnable
)
1661 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1663 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1664 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1666 return gras_su_cntl
;
1670 tu6_emit_depth_bias(struct tu_cs
*cs
,
1671 float constant_factor
,
1675 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1676 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
).value
);
1677 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
).value
);
1678 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
).value
);
1682 tu6_emit_depth_control(struct tu_cs
*cs
,
1683 const VkPipelineDepthStencilStateCreateInfo
*ds_info
,
1684 const VkPipelineRasterizationStateCreateInfo
*rast_info
)
1686 uint32_t rb_depth_cntl
= 0;
1687 if (ds_info
->depthTestEnable
) {
1689 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1690 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1691 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
; /* TODO: don't set for ALWAYS/NEVER */
1693 if (rast_info
->depthClampEnable
)
1694 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE
;
1696 if (ds_info
->depthWriteEnable
)
1697 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1700 if (ds_info
->depthBoundsTestEnable
)
1701 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE
| A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1703 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1704 tu_cs_emit(cs
, rb_depth_cntl
);
1708 tu6_emit_stencil_control(struct tu_cs
*cs
,
1709 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1711 uint32_t rb_stencil_control
= 0;
1712 if (ds_info
->stencilTestEnable
) {
1713 const VkStencilOpState
*front
= &ds_info
->front
;
1714 const VkStencilOpState
*back
= &ds_info
->back
;
1715 rb_stencil_control
|=
1716 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1717 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1718 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1719 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1720 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1721 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1722 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1723 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1724 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1725 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1726 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1729 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1730 tu_cs_emit(cs
, rb_stencil_control
);
1734 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1737 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1738 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1739 has_alpha
? att
->srcColorBlendFactor
1740 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1741 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1742 has_alpha
? att
->dstColorBlendFactor
1743 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1744 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1745 const enum adreno_rb_blend_factor src_alpha_factor
=
1746 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1747 const enum adreno_rb_blend_factor dst_alpha_factor
=
1748 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1750 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1751 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1752 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1753 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1754 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1755 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1759 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1760 uint32_t rb_mrt_control_rop
,
1764 uint32_t rb_mrt_control
=
1765 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1767 /* ignore blending and logic op for integer attachments */
1769 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1770 return rb_mrt_control
;
1773 rb_mrt_control
|= rb_mrt_control_rop
;
1775 if (att
->blendEnable
) {
1776 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1779 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1782 return rb_mrt_control
;
1786 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1787 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1788 const VkFormat attachment_formats
[MAX_RTS
],
1789 uint32_t *blend_enable_mask
)
1791 *blend_enable_mask
= 0;
1793 bool rop_reads_dst
= false;
1794 uint32_t rb_mrt_control_rop
= 0;
1795 if (blend_info
->logicOpEnable
) {
1796 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1797 rb_mrt_control_rop
=
1798 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1799 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1802 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
1803 const VkPipelineColorBlendAttachmentState
*att
=
1804 &blend_info
->pAttachments
[i
];
1805 const VkFormat format
= attachment_formats
[i
];
1807 uint32_t rb_mrt_control
= 0;
1808 uint32_t rb_mrt_blend_control
= 0;
1809 if (format
!= VK_FORMAT_UNDEFINED
) {
1810 const bool is_int
= vk_format_is_int(format
);
1811 const bool has_alpha
= vk_format_has_alpha(format
);
1814 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
1815 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
1817 if (att
->blendEnable
|| rop_reads_dst
)
1818 *blend_enable_mask
|= 1 << i
;
1821 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1822 tu_cs_emit(cs
, rb_mrt_control
);
1823 tu_cs_emit(cs
, rb_mrt_blend_control
);
1828 tu6_emit_blend_control(struct tu_cs
*cs
,
1829 uint32_t blend_enable_mask
,
1830 bool dual_src_blend
,
1831 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
1833 const uint32_t sample_mask
=
1834 msaa_info
->pSampleMask
? (*msaa_info
->pSampleMask
& 0xffff)
1835 : ((1 << msaa_info
->rasterizationSamples
) - 1);
1838 A6XX_SP_BLEND_CNTL(.enabled
= blend_enable_mask
,
1839 .dual_color_in_enable
= dual_src_blend
,
1840 .alpha_to_coverage
= msaa_info
->alphaToCoverageEnable
,
1843 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1845 A6XX_RB_BLEND_CNTL(.enable_blend
= blend_enable_mask
,
1846 .independent_blend
= true,
1847 .sample_mask
= sample_mask
,
1848 .dual_color_in_enable
= dual_src_blend
,
1849 .alpha_to_coverage
= msaa_info
->alphaToCoverageEnable
,
1850 .alpha_to_one
= msaa_info
->alphaToOneEnable
));
1854 tu_pipeline_allocate_cs(struct tu_device
*dev
,
1855 struct tu_pipeline
*pipeline
,
1856 struct tu_pipeline_builder
*builder
,
1857 struct ir3_shader_variant
*compute
)
1859 uint32_t size
= 2048 + tu6_load_state_size(pipeline
, compute
);
1861 /* graphics case: */
1863 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1864 if (builder
->variants
[i
])
1865 size
+= builder
->variants
[i
]->info
.sizedwords
;
1868 size
+= builder
->binning_variant
->info
.sizedwords
;
1870 size
+= compute
->info
.sizedwords
;
1873 tu_cs_init(&pipeline
->cs
, dev
, TU_CS_MODE_SUB_STREAM
, size
);
1875 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1876 * that LOAD_STATE can potentially take up a large amount of space so we
1877 * calculate its size explicitly.
1879 return tu_cs_reserve_space(&pipeline
->cs
, size
);
1883 tu_pipeline_shader_key_init(struct ir3_shader_key
*key
,
1884 const VkGraphicsPipelineCreateInfo
*pipeline_info
)
1886 for (uint32_t i
= 0; i
< pipeline_info
->stageCount
; i
++) {
1887 if (pipeline_info
->pStages
[i
].stage
== VK_SHADER_STAGE_GEOMETRY_BIT
) {
1893 if (pipeline_info
->pRasterizationState
->rasterizerDiscardEnable
)
1896 const VkPipelineMultisampleStateCreateInfo
*msaa_info
= pipeline_info
->pMultisampleState
;
1897 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
1898 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1899 if (msaa_info
->rasterizationSamples
> 1 ||
1900 /* also set msaa key when sample location is not the default
1901 * since this affects varying interpolation */
1902 (sample_locations
&& sample_locations
->sampleLocationsEnable
)) {
1906 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1907 if (msaa_info
->sampleShadingEnable
)
1908 key
->sample_shading
= true;
1910 /* We set this after we compile to NIR because we need the prim mode */
1911 key
->tessellation
= IR3_TESS_NONE
;
1915 tu6_get_tessmode(struct tu_shader
* shader
)
1917 uint32_t primitive_mode
= shader
->ir3_shader
->nir
->info
.tess
.primitive_mode
;
1918 switch (primitive_mode
) {
1920 return IR3_TESS_ISOLINES
;
1922 return IR3_TESS_TRIANGLES
;
1924 return IR3_TESS_QUADS
;
1926 return IR3_TESS_NONE
;
1928 unreachable("bad tessmode");
1933 tu_upload_variant(struct tu_pipeline
*pipeline
,
1934 const struct ir3_shader_variant
*variant
)
1936 struct tu_cs_memory memory
;
1941 /* this expects to get enough alignment because shaders are allocated first
1942 * and sizedwords is always aligned correctly
1943 * note: an assert in tu6_emit_xs_config validates the alignment
1945 tu_cs_alloc(&pipeline
->cs
, variant
->info
.sizedwords
, 1, &memory
);
1947 memcpy(memory
.map
, variant
->bin
, sizeof(uint32_t) * variant
->info
.sizedwords
);
1952 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
,
1953 struct tu_pipeline
*pipeline
)
1955 const struct ir3_compiler
*compiler
= builder
->device
->compiler
;
1956 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
1959 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1960 gl_shader_stage stage
=
1961 vk_to_mesa_shader_stage(builder
->create_info
->pStages
[i
].stage
);
1962 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
1965 struct ir3_shader_key key
= {};
1966 tu_pipeline_shader_key_init(&key
, builder
->create_info
);
1968 for (gl_shader_stage stage
= MESA_SHADER_VERTEX
;
1969 stage
< MESA_SHADER_STAGES
; stage
++) {
1970 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
1971 if (!stage_info
&& stage
!= MESA_SHADER_FRAGMENT
)
1974 struct tu_shader
*shader
=
1975 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->layout
,
1978 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1980 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
1981 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
1982 * the mode is specified in the tessellation control shader. */
1983 if ((stage
== MESA_SHADER_TESS_EVAL
|| stage
== MESA_SHADER_TESS_CTRL
) &&
1984 key
.tessellation
== IR3_TESS_NONE
) {
1985 key
.tessellation
= tu6_get_tessmode(shader
);
1988 builder
->shaders
[stage
] = shader
;
1991 struct tu_shader
*gs
= builder
->shaders
[MESA_SHADER_GEOMETRY
];
1993 !gs
|| !(gs
->ir3_shader
->nir
->info
.outputs_written
& VARYING_SLOT_LAYER
);
1995 pipeline
->tess
.patch_type
= key
.tessellation
;
1997 for (gl_shader_stage stage
= MESA_SHADER_VERTEX
;
1998 stage
< MESA_SHADER_STAGES
; stage
++) {
1999 if (!builder
->shaders
[stage
])
2003 builder
->variants
[stage
] =
2004 ir3_shader_get_variant(builder
->shaders
[stage
]->ir3_shader
,
2005 &key
, false, &created
);
2006 if (!builder
->variants
[stage
])
2007 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2010 uint32_t safe_constlens
= ir3_trim_constlen(builder
->variants
, compiler
);
2012 key
.safe_constlen
= true;
2014 for (gl_shader_stage stage
= MESA_SHADER_VERTEX
;
2015 stage
< MESA_SHADER_STAGES
; stage
++) {
2016 if (!builder
->shaders
[stage
])
2019 if (safe_constlens
& (1 << stage
)) {
2021 builder
->variants
[stage
] =
2022 ir3_shader_get_variant(builder
->shaders
[stage
]->ir3_shader
,
2023 &key
, false, &created
);
2024 if (!builder
->variants
[stage
])
2025 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2029 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
2030 struct ir3_shader_variant
*variant
;
2032 if (vs
->ir3_shader
->stream_output
.num_outputs
||
2033 !ir3_has_binning_vs(&key
)) {
2034 variant
= builder
->variants
[MESA_SHADER_VERTEX
];
2037 key
.safe_constlen
= !!(safe_constlens
& (1 << MESA_SHADER_VERTEX
));
2038 variant
= ir3_shader_get_variant(vs
->ir3_shader
, &key
,
2041 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2044 builder
->binning_variant
= variant
;
2050 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
2051 struct tu_pipeline
*pipeline
)
2053 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
2054 builder
->create_info
->pDynamicState
;
2059 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
2060 VkDynamicState state
= dynamic_info
->pDynamicStates
[i
];
2062 case VK_DYNAMIC_STATE_VIEWPORT
... VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2063 pipeline
->dynamic_state_mask
|= BIT(state
);
2065 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
2066 pipeline
->dynamic_state_mask
|= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
);
2069 assert(!"unsupported dynamic state");
2076 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage
*link
,
2077 struct tu_shader
*shader
,
2078 struct ir3_shader_variant
*v
)
2080 link
->const_state
= *ir3_const_state(v
);
2081 link
->constlen
= v
->constlen
;
2082 link
->push_consts
= shader
->push_consts
;
2086 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
2087 struct tu_pipeline
*pipeline
)
2089 struct tu_cs prog_cs
;
2090 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2091 tu6_emit_program(&prog_cs
, builder
, false);
2092 pipeline
->program
.state
= tu_cs_end_draw_state(&pipeline
->cs
, &prog_cs
);
2094 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2095 tu6_emit_program(&prog_cs
, builder
, true);
2096 pipeline
->program
.binning_state
= tu_cs_end_draw_state(&pipeline
->cs
, &prog_cs
);
2098 VkShaderStageFlags stages
= 0;
2099 for (unsigned i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
2100 stages
|= builder
->create_info
->pStages
[i
].stage
;
2102 pipeline
->active_stages
= stages
;
2104 uint32_t desc_sets
= 0;
2105 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2106 if (!builder
->shaders
[i
])
2109 tu_pipeline_set_linkage(&pipeline
->program
.link
[i
],
2110 builder
->shaders
[i
],
2111 builder
->variants
[i
]);
2112 desc_sets
|= builder
->shaders
[i
]->active_desc_sets
;
2114 pipeline
->active_desc_sets
= desc_sets
;
2118 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
2119 struct tu_pipeline
*pipeline
)
2121 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
2122 builder
->create_info
->pVertexInputState
;
2123 const struct ir3_shader_variant
*vs
= builder
->variants
[MESA_SHADER_VERTEX
];
2124 const struct ir3_shader_variant
*bs
= builder
->binning_variant
;
2127 tu_cs_begin_sub_stream(&pipeline
->cs
,
2128 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2129 tu6_emit_vertex_input(&vi_cs
, vs
, vi_info
,
2130 &pipeline
->vi
.bindings_used
);
2131 pipeline
->vi
.state
= tu_cs_end_draw_state(&pipeline
->cs
, &vi_cs
);
2134 tu_cs_begin_sub_stream(&pipeline
->cs
,
2135 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2136 tu6_emit_vertex_input(
2137 &vi_cs
, bs
, vi_info
, &pipeline
->vi
.bindings_used
);
2138 pipeline
->vi
.binning_state
=
2139 tu_cs_end_draw_state(&pipeline
->cs
, &vi_cs
);
2144 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
2145 struct tu_pipeline
*pipeline
)
2147 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
2148 builder
->create_info
->pInputAssemblyState
;
2150 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
2151 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
2155 tu_pipeline_static_state(struct tu_pipeline
*pipeline
, struct tu_cs
*cs
,
2156 uint32_t id
, uint32_t size
)
2158 assert(id
< ARRAY_SIZE(pipeline
->dynamic_state
));
2160 if (pipeline
->dynamic_state_mask
& BIT(id
))
2163 pipeline
->dynamic_state
[id
] = tu_cs_draw_state(&pipeline
->cs
, cs
, size
);
2168 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder
*builder
,
2169 struct tu_pipeline
*pipeline
)
2171 const VkPipelineTessellationStateCreateInfo
*tess_info
=
2172 builder
->create_info
->pTessellationState
;
2177 assert(pipeline
->ia
.primtype
== DI_PT_PATCHES0
);
2178 assert(tess_info
->patchControlPoints
<= 32);
2179 pipeline
->ia
.primtype
+= tess_info
->patchControlPoints
;
2180 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_info
=
2181 vk_find_struct_const(tess_info
->pNext
, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2182 pipeline
->tess
.upper_left_domain_origin
= !domain_info
||
2183 domain_info
->domainOrigin
== VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
;
2184 const struct ir3_shader_variant
*hs
= builder
->variants
[MESA_SHADER_TESS_CTRL
];
2185 const struct ir3_shader_variant
*ds
= builder
->variants
[MESA_SHADER_TESS_EVAL
];
2186 pipeline
->tess
.param_stride
= hs
->output_size
* 4;
2187 pipeline
->tess
.hs_bo_regid
= hs
->const_state
->offsets
.primitive_param
+ 1;
2188 pipeline
->tess
.ds_bo_regid
= ds
->const_state
->offsets
.primitive_param
+ 1;
2192 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
2193 struct tu_pipeline
*pipeline
)
2197 * pViewportState is a pointer to an instance of the
2198 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2199 * pipeline has rasterization disabled."
2201 * We leave the relevant registers stale in that case.
2203 if (builder
->rasterizer_discard
)
2206 const VkPipelineViewportStateCreateInfo
*vp_info
=
2207 builder
->create_info
->pViewportState
;
2211 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_VIEWPORT
, 18))
2212 tu6_emit_viewport(&cs
, vp_info
->pViewports
);
2214 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_SCISSOR
, 3))
2215 tu6_emit_scissor(&cs
, vp_info
->pScissors
);
2219 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
2220 struct tu_pipeline
*pipeline
)
2222 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
2223 builder
->create_info
->pRasterizationState
;
2225 enum a6xx_polygon_mode mode
= tu6_polygon_mode(rast_info
->polygonMode
);
2228 pipeline
->rast_state
= tu_cs_draw_state(&pipeline
->cs
, &cs
, 9);
2230 tu_cs_emit_regs(&cs
,
2232 .znear_clip_disable
= rast_info
->depthClampEnable
,
2233 .zfar_clip_disable
= rast_info
->depthClampEnable
,
2234 .unk5
= rast_info
->depthClampEnable
,
2235 .zero_gb_scale_z
= 1,
2236 .vp_clip_code_ignore
= 1));
2238 tu_cs_emit_regs(&cs
,
2239 A6XX_VPC_POLYGON_MODE(mode
));
2241 tu_cs_emit_regs(&cs
,
2242 A6XX_PC_POLYGON_MODE(mode
));
2244 /* move to hw ctx init? */
2245 tu_cs_emit_regs(&cs
,
2246 A6XX_GRAS_SU_POINT_MINMAX(.min
= 1.0f
/ 16.0f
, .max
= 4092.0f
),
2247 A6XX_GRAS_SU_POINT_SIZE(1.0f
));
2249 pipeline
->gras_su_cntl
=
2250 tu6_gras_su_cntl(rast_info
, builder
->samples
);
2252 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2)) {
2253 pipeline
->gras_su_cntl
|=
2254 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info
->lineWidth
/ 2.0f
);
2255 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= pipeline
->gras_su_cntl
));
2258 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4)) {
2259 tu6_emit_depth_bias(&cs
, rast_info
->depthBiasConstantFactor
,
2260 rast_info
->depthBiasClamp
,
2261 rast_info
->depthBiasSlopeFactor
);
2267 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
2268 struct tu_pipeline
*pipeline
)
2272 * pDepthStencilState is a pointer to an instance of the
2273 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2274 * the pipeline has rasterization disabled or if the subpass of the
2275 * render pass the pipeline is created against does not use a
2276 * depth/stencil attachment.
2278 * Disable both depth and stencil tests if there is no ds attachment,
2279 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2280 * only the separate stencil attachment
2282 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
2283 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
2284 builder
->depth_attachment_format
!= VK_FORMAT_UNDEFINED
2285 ? builder
->create_info
->pDepthStencilState
2287 const VkPipelineDepthStencilStateCreateInfo
*ds_info_depth
=
2288 builder
->depth_attachment_format
!= VK_FORMAT_S8_UINT
2289 ? ds_info
: &dummy_ds_info
;
2292 pipeline
->ds_state
= tu_cs_draw_state(&pipeline
->cs
, &cs
, 6);
2294 /* move to hw ctx init? */
2295 tu_cs_emit_regs(&cs
, A6XX_RB_ALPHA_CONTROL());
2296 tu6_emit_depth_control(&cs
, ds_info_depth
,
2297 builder
->create_info
->pRasterizationState
);
2298 tu6_emit_stencil_control(&cs
, ds_info
);
2300 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_DEPTH_BOUNDS
, 3)) {
2301 tu_cs_emit_regs(&cs
,
2302 A6XX_RB_Z_BOUNDS_MIN(ds_info
->minDepthBounds
),
2303 A6XX_RB_Z_BOUNDS_MAX(ds_info
->maxDepthBounds
));
2306 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2)) {
2307 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.mask
= ds_info
->front
.compareMask
& 0xff,
2308 .bfmask
= ds_info
->back
.compareMask
& 0xff));
2311 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2)) {
2312 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.wrmask
= ds_info
->front
.writeMask
& 0xff,
2313 .bfwrmask
= ds_info
->back
.writeMask
& 0xff));
2316 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2)) {
2317 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.ref
= ds_info
->front
.reference
& 0xff,
2318 .bfref
= ds_info
->back
.reference
& 0xff));
2323 tu_pipeline_builder_parse_multisample_and_color_blend(
2324 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
2328 * pMultisampleState is a pointer to an instance of the
2329 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2330 * has rasterization disabled.
2334 * pColorBlendState is a pointer to an instance of the
2335 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2336 * pipeline has rasterization disabled or if the subpass of the render
2337 * pass the pipeline is created against does not use any color
2340 * We leave the relevant registers stale when rasterization is disabled.
2342 if (builder
->rasterizer_discard
)
2345 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
2346 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
2347 builder
->create_info
->pMultisampleState
;
2348 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
2349 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
2350 : &dummy_blend_info
;
2353 pipeline
->blend_state
=
2354 tu_cs_draw_state(&pipeline
->cs
, &cs
, blend_info
->attachmentCount
* 3 + 4);
2356 uint32_t blend_enable_mask
;
2357 tu6_emit_rb_mrt_controls(&cs
, blend_info
,
2358 builder
->color_attachment_formats
,
2359 &blend_enable_mask
);
2361 tu6_emit_blend_control(&cs
, blend_enable_mask
,
2362 builder
->use_dual_src_blend
, msaa_info
);
2364 assert(cs
.cur
== cs
.end
); /* validate draw state size */
2366 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5)) {
2367 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2368 tu_cs_emit_array(&cs
, (const uint32_t *) blend_info
->blendConstants
, 4);
2371 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
2372 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
2373 const VkSampleLocationsInfoEXT
*samp_loc
= NULL
;
2375 if (sample_locations
&& sample_locations
->sampleLocationsEnable
)
2376 samp_loc
= &sample_locations
->sampleLocationsInfo
;
2378 if (tu_pipeline_static_state(pipeline
, &cs
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
,
2379 samp_loc
? 9 : 6)) {
2380 tu6_emit_sample_locations(&cs
, samp_loc
);
2385 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
2386 struct tu_device
*dev
,
2387 const VkAllocationCallbacks
*alloc
)
2389 tu_cs_finish(&pipeline
->cs
);
2393 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
2394 struct tu_pipeline
**pipeline
)
2398 *pipeline
= vk_object_zalloc(&builder
->device
->vk
, builder
->alloc
,
2399 sizeof(**pipeline
), VK_OBJECT_TYPE_PIPELINE
);
2401 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2403 (*pipeline
)->layout
= builder
->layout
;
2405 /* compile and upload shaders */
2406 result
= tu_pipeline_builder_compile_shaders(builder
, *pipeline
);
2407 if (result
!= VK_SUCCESS
) {
2408 vk_object_free(&builder
->device
->vk
, builder
->alloc
, *pipeline
);
2412 result
= tu_pipeline_allocate_cs(builder
->device
, *pipeline
, builder
, NULL
);
2413 if (result
!= VK_SUCCESS
) {
2414 vk_object_free(&builder
->device
->vk
, builder
->alloc
, *pipeline
);
2418 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
2419 builder
->shader_iova
[i
] = tu_upload_variant(*pipeline
, builder
->variants
[i
]);
2421 builder
->binning_vs_iova
=
2422 tu_upload_variant(*pipeline
, builder
->binning_variant
);
2424 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
2425 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
2426 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
2427 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
2428 tu_pipeline_builder_parse_tessellation(builder
, *pipeline
);
2429 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
2430 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
2431 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
2432 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
2433 tu6_emit_load_state(*pipeline
, false);
2435 /* we should have reserved enough space upfront such that the CS never
2438 assert((*pipeline
)->cs
.bo_count
== 1);
2444 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
2446 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2447 if (!builder
->shaders
[i
])
2449 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
2454 tu_pipeline_builder_init_graphics(
2455 struct tu_pipeline_builder
*builder
,
2456 struct tu_device
*dev
,
2457 struct tu_pipeline_cache
*cache
,
2458 const VkGraphicsPipelineCreateInfo
*create_info
,
2459 const VkAllocationCallbacks
*alloc
)
2461 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, create_info
->layout
);
2463 *builder
= (struct tu_pipeline_builder
) {
2466 .create_info
= create_info
,
2471 builder
->rasterizer_discard
=
2472 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
2474 if (builder
->rasterizer_discard
) {
2475 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
2477 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
2479 const struct tu_render_pass
*pass
=
2480 tu_render_pass_from_handle(create_info
->renderPass
);
2481 const struct tu_subpass
*subpass
=
2482 &pass
->subpasses
[create_info
->subpass
];
2484 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
2485 builder
->depth_attachment_format
= (a
!= VK_ATTACHMENT_UNUSED
) ?
2486 pass
->attachments
[a
].format
: VK_FORMAT_UNDEFINED
;
2488 assert(subpass
->color_count
== 0 ||
2489 !create_info
->pColorBlendState
||
2490 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
2491 builder
->color_attachment_count
= subpass
->color_count
;
2492 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
2493 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
2494 if (a
== VK_ATTACHMENT_UNUSED
)
2497 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
2498 builder
->use_color_attachments
= true;
2499 builder
->render_components
|= 0xf << (i
* 4);
2502 if (tu_blend_state_is_dual_src(create_info
->pColorBlendState
)) {
2503 builder
->color_attachment_count
++;
2504 builder
->use_dual_src_blend
= true;
2505 /* dual source blending has an extra fs output in the 2nd slot */
2506 if (subpass
->color_attachments
[0].attachment
!= VK_ATTACHMENT_UNUSED
)
2507 builder
->render_components
|= 0xf << 4;
2513 tu_graphics_pipeline_create(VkDevice device
,
2514 VkPipelineCache pipelineCache
,
2515 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2516 const VkAllocationCallbacks
*pAllocator
,
2517 VkPipeline
*pPipeline
)
2519 TU_FROM_HANDLE(tu_device
, dev
, device
);
2520 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
2522 struct tu_pipeline_builder builder
;
2523 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
2524 pCreateInfo
, pAllocator
);
2526 struct tu_pipeline
*pipeline
= NULL
;
2527 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
2528 tu_pipeline_builder_finish(&builder
);
2530 if (result
== VK_SUCCESS
)
2531 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2533 *pPipeline
= VK_NULL_HANDLE
;
2539 tu_CreateGraphicsPipelines(VkDevice device
,
2540 VkPipelineCache pipelineCache
,
2542 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
2543 const VkAllocationCallbacks
*pAllocator
,
2544 VkPipeline
*pPipelines
)
2546 VkResult final_result
= VK_SUCCESS
;
2548 for (uint32_t i
= 0; i
< count
; i
++) {
2549 VkResult result
= tu_graphics_pipeline_create(device
, pipelineCache
,
2550 &pCreateInfos
[i
], pAllocator
,
2553 if (result
!= VK_SUCCESS
)
2554 final_result
= result
;
2557 return final_result
;
2561 tu_compute_pipeline_create(VkDevice device
,
2562 VkPipelineCache _cache
,
2563 const VkComputePipelineCreateInfo
*pCreateInfo
,
2564 const VkAllocationCallbacks
*pAllocator
,
2565 VkPipeline
*pPipeline
)
2567 TU_FROM_HANDLE(tu_device
, dev
, device
);
2568 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, pCreateInfo
->layout
);
2569 const VkPipelineShaderStageCreateInfo
*stage_info
= &pCreateInfo
->stage
;
2572 struct tu_pipeline
*pipeline
;
2574 *pPipeline
= VK_NULL_HANDLE
;
2576 pipeline
= vk_object_zalloc(&dev
->vk
, pAllocator
, sizeof(*pipeline
),
2577 VK_OBJECT_TYPE_PIPELINE
);
2579 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2581 pipeline
->layout
= layout
;
2583 struct ir3_shader_key key
= {};
2585 struct tu_shader
*shader
=
2586 tu_shader_create(dev
, MESA_SHADER_COMPUTE
, stage_info
, layout
, pAllocator
);
2588 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2592 pipeline
->active_desc_sets
= shader
->active_desc_sets
;
2595 struct ir3_shader_variant
*v
=
2596 ir3_shader_get_variant(shader
->ir3_shader
, &key
, false, &created
);
2598 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2602 tu_pipeline_set_linkage(&pipeline
->program
.link
[MESA_SHADER_COMPUTE
],
2605 result
= tu_pipeline_allocate_cs(dev
, pipeline
, NULL
, v
);
2606 if (result
!= VK_SUCCESS
)
2609 uint64_t shader_iova
= tu_upload_variant(pipeline
, v
);
2611 for (int i
= 0; i
< 3; i
++)
2612 pipeline
->compute
.local_size
[i
] = v
->shader
->nir
->info
.cs
.local_size
[i
];
2614 struct tu_cs prog_cs
;
2615 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2616 tu6_emit_cs_config(&prog_cs
, shader
, v
, shader_iova
);
2617 pipeline
->program
.state
= tu_cs_end_draw_state(&pipeline
->cs
, &prog_cs
);
2619 tu6_emit_load_state(pipeline
, true);
2621 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2626 tu_shader_destroy(dev
, shader
, pAllocator
);
2628 vk_object_free(&dev
->vk
, pAllocator
, pipeline
);
2634 tu_CreateComputePipelines(VkDevice device
,
2635 VkPipelineCache pipelineCache
,
2637 const VkComputePipelineCreateInfo
*pCreateInfos
,
2638 const VkAllocationCallbacks
*pAllocator
,
2639 VkPipeline
*pPipelines
)
2641 VkResult final_result
= VK_SUCCESS
;
2643 for (uint32_t i
= 0; i
< count
; i
++) {
2644 VkResult result
= tu_compute_pipeline_create(device
, pipelineCache
,
2646 pAllocator
, &pPipelines
[i
]);
2647 if (result
!= VK_SUCCESS
)
2648 final_result
= result
;
2651 return final_result
;
2655 tu_DestroyPipeline(VkDevice _device
,
2656 VkPipeline _pipeline
,
2657 const VkAllocationCallbacks
*pAllocator
)
2659 TU_FROM_HANDLE(tu_device
, dev
, _device
);
2660 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2665 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2666 vk_object_free(&dev
->vk
, pAllocator
, pipeline
);