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radv: do not use VK_TRUE/VK_FALSE
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "main/menums.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
38 #include "vk_util.h"
39
40 #include "tu_cs.h"
41
42 struct tu_pipeline_builder
43 {
44 struct tu_device *device;
45 struct tu_pipeline_cache *cache;
46 const VkAllocationCallbacks *alloc;
47 const VkGraphicsPipelineCreateInfo *create_info;
48
49 struct tu_shader *shaders[MESA_SHADER_STAGES];
50 uint32_t shader_offsets[MESA_SHADER_STAGES];
51 uint32_t binning_vs_offset;
52 uint32_t shader_total_size;
53
54 bool rasterizer_discard;
55 /* these states are affectd by rasterizer_discard */
56 VkSampleCountFlagBits samples;
57 bool use_depth_stencil_attachment;
58 bool use_color_attachments;
59 uint32_t color_attachment_count;
60 VkFormat color_attachment_formats[MAX_RTS];
61 };
62
63 static enum tu_dynamic_state_bits
64 tu_dynamic_state_bit(VkDynamicState state)
65 {
66 switch (state) {
67 case VK_DYNAMIC_STATE_VIEWPORT:
68 return TU_DYNAMIC_VIEWPORT;
69 case VK_DYNAMIC_STATE_SCISSOR:
70 return TU_DYNAMIC_SCISSOR;
71 case VK_DYNAMIC_STATE_LINE_WIDTH:
72 return TU_DYNAMIC_LINE_WIDTH;
73 case VK_DYNAMIC_STATE_DEPTH_BIAS:
74 return TU_DYNAMIC_DEPTH_BIAS;
75 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
76 return TU_DYNAMIC_BLEND_CONSTANTS;
77 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
78 return TU_DYNAMIC_DEPTH_BOUNDS;
79 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
80 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
81 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
82 return TU_DYNAMIC_STENCIL_WRITE_MASK;
83 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
84 return TU_DYNAMIC_STENCIL_REFERENCE;
85 default:
86 unreachable("invalid dynamic state");
87 return 0;
88 }
89 }
90
91 static gl_shader_stage
92 tu_shader_stage(VkShaderStageFlagBits stage)
93 {
94 switch (stage) {
95 case VK_SHADER_STAGE_VERTEX_BIT:
96 return MESA_SHADER_VERTEX;
97 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
98 return MESA_SHADER_TESS_CTRL;
99 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
100 return MESA_SHADER_TESS_EVAL;
101 case VK_SHADER_STAGE_GEOMETRY_BIT:
102 return MESA_SHADER_GEOMETRY;
103 case VK_SHADER_STAGE_FRAGMENT_BIT:
104 return MESA_SHADER_FRAGMENT;
105 case VK_SHADER_STAGE_COMPUTE_BIT:
106 return MESA_SHADER_COMPUTE;
107 default:
108 unreachable("invalid VkShaderStageFlagBits");
109 return MESA_SHADER_NONE;
110 }
111 }
112
113 static const VkVertexInputAttributeDescription *
114 tu_find_vertex_input_attribute(
115 const VkPipelineVertexInputStateCreateInfo *vi_info, uint32_t slot)
116 {
117 assert(slot >= VERT_ATTRIB_GENERIC0);
118 slot -= VERT_ATTRIB_GENERIC0;
119 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
120 if (vi_info->pVertexAttributeDescriptions[i].location == slot)
121 return &vi_info->pVertexAttributeDescriptions[i];
122 }
123 return NULL;
124 }
125
126 static const VkVertexInputBindingDescription *
127 tu_find_vertex_input_binding(
128 const VkPipelineVertexInputStateCreateInfo *vi_info,
129 const VkVertexInputAttributeDescription *vi_attr)
130 {
131 assert(vi_attr);
132 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
133 if (vi_info->pVertexBindingDescriptions[i].binding == vi_attr->binding)
134 return &vi_info->pVertexBindingDescriptions[i];
135 }
136 return NULL;
137 }
138
139 static bool
140 tu_logic_op_reads_dst(VkLogicOp op)
141 {
142 switch (op) {
143 case VK_LOGIC_OP_CLEAR:
144 case VK_LOGIC_OP_COPY:
145 case VK_LOGIC_OP_COPY_INVERTED:
146 case VK_LOGIC_OP_SET:
147 return false;
148 default:
149 return true;
150 }
151 }
152
153 static VkBlendFactor
154 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
155 {
156 /* treat dst alpha as 1.0 and avoid reading it */
157 switch (factor) {
158 case VK_BLEND_FACTOR_DST_ALPHA:
159 return VK_BLEND_FACTOR_ONE;
160 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
161 return VK_BLEND_FACTOR_ZERO;
162 default:
163 return factor;
164 }
165 }
166
167 static enum pc_di_primtype
168 tu6_primtype(VkPrimitiveTopology topology)
169 {
170 switch (topology) {
171 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
172 return DI_PT_POINTLIST;
173 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
174 return DI_PT_LINELIST;
175 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
176 return DI_PT_LINESTRIP;
177 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
178 return DI_PT_TRILIST;
179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
180 return DI_PT_TRISTRIP;
181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
182 return DI_PT_TRIFAN;
183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
184 return DI_PT_LINE_ADJ;
185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
186 return DI_PT_LINESTRIP_ADJ;
187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
188 return DI_PT_TRI_ADJ;
189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
190 return DI_PT_TRISTRIP_ADJ;
191 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
192 default:
193 unreachable("invalid primitive topology");
194 return DI_PT_NONE;
195 }
196 }
197
198 static enum adreno_compare_func
199 tu6_compare_func(VkCompareOp op)
200 {
201 switch (op) {
202 case VK_COMPARE_OP_NEVER:
203 return FUNC_NEVER;
204 case VK_COMPARE_OP_LESS:
205 return FUNC_LESS;
206 case VK_COMPARE_OP_EQUAL:
207 return FUNC_EQUAL;
208 case VK_COMPARE_OP_LESS_OR_EQUAL:
209 return FUNC_LEQUAL;
210 case VK_COMPARE_OP_GREATER:
211 return FUNC_GREATER;
212 case VK_COMPARE_OP_NOT_EQUAL:
213 return FUNC_NOTEQUAL;
214 case VK_COMPARE_OP_GREATER_OR_EQUAL:
215 return FUNC_GEQUAL;
216 case VK_COMPARE_OP_ALWAYS:
217 return FUNC_ALWAYS;
218 default:
219 unreachable("invalid VkCompareOp");
220 return FUNC_NEVER;
221 }
222 }
223
224 static enum adreno_stencil_op
225 tu6_stencil_op(VkStencilOp op)
226 {
227 switch (op) {
228 case VK_STENCIL_OP_KEEP:
229 return STENCIL_KEEP;
230 case VK_STENCIL_OP_ZERO:
231 return STENCIL_ZERO;
232 case VK_STENCIL_OP_REPLACE:
233 return STENCIL_REPLACE;
234 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
235 return STENCIL_INCR_CLAMP;
236 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
237 return STENCIL_DECR_CLAMP;
238 case VK_STENCIL_OP_INVERT:
239 return STENCIL_INVERT;
240 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
241 return STENCIL_INCR_WRAP;
242 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
243 return STENCIL_DECR_WRAP;
244 default:
245 unreachable("invalid VkStencilOp");
246 return STENCIL_KEEP;
247 }
248 }
249
250 static enum a3xx_rop_code
251 tu6_rop(VkLogicOp op)
252 {
253 switch (op) {
254 case VK_LOGIC_OP_CLEAR:
255 return ROP_CLEAR;
256 case VK_LOGIC_OP_AND:
257 return ROP_AND;
258 case VK_LOGIC_OP_AND_REVERSE:
259 return ROP_AND_REVERSE;
260 case VK_LOGIC_OP_COPY:
261 return ROP_COPY;
262 case VK_LOGIC_OP_AND_INVERTED:
263 return ROP_AND_INVERTED;
264 case VK_LOGIC_OP_NO_OP:
265 return ROP_NOOP;
266 case VK_LOGIC_OP_XOR:
267 return ROP_XOR;
268 case VK_LOGIC_OP_OR:
269 return ROP_OR;
270 case VK_LOGIC_OP_NOR:
271 return ROP_NOR;
272 case VK_LOGIC_OP_EQUIVALENT:
273 return ROP_EQUIV;
274 case VK_LOGIC_OP_INVERT:
275 return ROP_INVERT;
276 case VK_LOGIC_OP_OR_REVERSE:
277 return ROP_OR_REVERSE;
278 case VK_LOGIC_OP_COPY_INVERTED:
279 return ROP_COPY_INVERTED;
280 case VK_LOGIC_OP_OR_INVERTED:
281 return ROP_OR_INVERTED;
282 case VK_LOGIC_OP_NAND:
283 return ROP_NAND;
284 case VK_LOGIC_OP_SET:
285 return ROP_SET;
286 default:
287 unreachable("invalid VkLogicOp");
288 return ROP_NOOP;
289 }
290 }
291
292 static enum adreno_rb_blend_factor
293 tu6_blend_factor(VkBlendFactor factor)
294 {
295 switch (factor) {
296 case VK_BLEND_FACTOR_ZERO:
297 return FACTOR_ZERO;
298 case VK_BLEND_FACTOR_ONE:
299 return FACTOR_ONE;
300 case VK_BLEND_FACTOR_SRC_COLOR:
301 return FACTOR_SRC_COLOR;
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
303 return FACTOR_ONE_MINUS_SRC_COLOR;
304 case VK_BLEND_FACTOR_DST_COLOR:
305 return FACTOR_DST_COLOR;
306 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
307 return FACTOR_ONE_MINUS_DST_COLOR;
308 case VK_BLEND_FACTOR_SRC_ALPHA:
309 return FACTOR_SRC_ALPHA;
310 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
311 return FACTOR_ONE_MINUS_SRC_ALPHA;
312 case VK_BLEND_FACTOR_DST_ALPHA:
313 return FACTOR_DST_ALPHA;
314 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
315 return FACTOR_ONE_MINUS_DST_ALPHA;
316 case VK_BLEND_FACTOR_CONSTANT_COLOR:
317 return FACTOR_CONSTANT_COLOR;
318 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
319 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
320 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
321 return FACTOR_CONSTANT_ALPHA;
322 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
323 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
325 return FACTOR_SRC_ALPHA_SATURATE;
326 case VK_BLEND_FACTOR_SRC1_COLOR:
327 return FACTOR_SRC1_COLOR;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
329 return FACTOR_ONE_MINUS_SRC1_COLOR;
330 case VK_BLEND_FACTOR_SRC1_ALPHA:
331 return FACTOR_SRC1_ALPHA;
332 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
333 return FACTOR_ONE_MINUS_SRC1_ALPHA;
334 default:
335 unreachable("invalid VkBlendFactor");
336 return FACTOR_ZERO;
337 }
338 }
339
340 static enum a3xx_rb_blend_opcode
341 tu6_blend_op(VkBlendOp op)
342 {
343 switch (op) {
344 case VK_BLEND_OP_ADD:
345 return BLEND_DST_PLUS_SRC;
346 case VK_BLEND_OP_SUBTRACT:
347 return BLEND_SRC_MINUS_DST;
348 case VK_BLEND_OP_REVERSE_SUBTRACT:
349 return BLEND_DST_MINUS_SRC;
350 case VK_BLEND_OP_MIN:
351 return BLEND_MIN_DST_SRC;
352 case VK_BLEND_OP_MAX:
353 return BLEND_MAX_DST_SRC;
354 default:
355 unreachable("invalid VkBlendOp");
356 return BLEND_DST_PLUS_SRC;
357 }
358 }
359
360 static void
361 tu6_emit_vs_config(struct tu_cs *cs, const struct ir3_shader_variant *vs)
362 {
363 uint32_t sp_vs_ctrl =
364 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
365 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
366 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
367 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
368 if (vs->need_pixlod)
369 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
370
371 uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(vs->num_samp) |
372 A6XX_SP_VS_CONFIG_NSAMP(vs->num_samp);
373 if (vs->instrlen)
374 sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
375
376 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
377 tu_cs_emit(cs, sp_vs_ctrl);
378
379 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
380 tu_cs_emit(cs, sp_vs_config);
381 tu_cs_emit(cs, vs->instrlen);
382
383 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
384 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
385 A6XX_HLSQ_VS_CNTL_ENABLED);
386 }
387
388 static void
389 tu6_emit_hs_config(struct tu_cs *cs, const struct ir3_shader_variant *hs)
390 {
391 uint32_t sp_hs_config = 0;
392 if (hs->instrlen)
393 sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
394
395 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
396 tu_cs_emit(cs, 0);
397
398 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
399 tu_cs_emit(cs, sp_hs_config);
400 tu_cs_emit(cs, hs->instrlen);
401
402 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
403 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
404 }
405
406 static void
407 tu6_emit_ds_config(struct tu_cs *cs, const struct ir3_shader_variant *ds)
408 {
409 uint32_t sp_ds_config = 0;
410 if (ds->instrlen)
411 sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
412
413 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
414 tu_cs_emit(cs, sp_ds_config);
415 tu_cs_emit(cs, ds->instrlen);
416
417 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
418 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
419 }
420
421 static void
422 tu6_emit_gs_config(struct tu_cs *cs, const struct ir3_shader_variant *gs)
423 {
424 uint32_t sp_gs_config = 0;
425 if (gs->instrlen)
426 sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED;
427
428 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
429 tu_cs_emit(cs, 0);
430
431 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
432 tu_cs_emit(cs, sp_gs_config);
433 tu_cs_emit(cs, gs->instrlen);
434
435 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
436 tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
437 }
438
439 static void
440 tu6_emit_fs_config(struct tu_cs *cs, const struct ir3_shader_variant *fs)
441 {
442 uint32_t sp_fs_ctrl =
443 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
444 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
445 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
446 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
447 if (fs->total_in > 0 || fs->frag_coord)
448 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
449 if (fs->need_pixlod)
450 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
451
452 uint32_t sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(fs->num_samp) |
453 A6XX_SP_FS_CONFIG_NSAMP(fs->num_samp) |
454 A6XX_SP_FS_CONFIG_NIBO(fs->image_mapping.num_ibo);
455 if (fs->instrlen)
456 sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
457
458 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
459 tu_cs_emit(cs, 0);
460
461 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_AB00, 1);
462 tu_cs_emit(cs, 0x5);
463
464 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
465 tu_cs_emit(cs, sp_fs_ctrl);
466
467 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
468 tu_cs_emit(cs, sp_fs_config);
469 tu_cs_emit(cs, fs->instrlen);
470
471 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
472 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
473 A6XX_HLSQ_FS_CNTL_ENABLED);
474
475 tu_cs_emit_pkt4(cs, REG_A6XX_SP_IBO_COUNT, 1);
476 tu_cs_emit(cs, fs->image_mapping.num_ibo);
477 }
478
479 static void
480 tu6_emit_cs_config(struct tu_cs *cs, const struct ir3_shader_variant *v)
481 {
482 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
483 tu_cs_emit(cs, 0xff);
484
485 unsigned constlen = align(v->constlen, 4);
486 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
487 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
488 A6XX_HLSQ_CS_CNTL_ENABLED);
489
490 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
491 tu_cs_emit(cs, A6XX_SP_CS_CONFIG_ENABLED |
492 A6XX_SP_CS_CONFIG_NIBO(v->image_mapping.num_ibo) |
493 A6XX_SP_CS_CONFIG_NTEX(v->num_samp) |
494 A6XX_SP_CS_CONFIG_NSAMP(v->num_samp) |
495 A6XX_SP_CS_CONFIG_NIBO(v->image_mapping.num_ibo));
496 tu_cs_emit(cs, v->instrlen);
497
498 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
499 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
500 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
501 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
502 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
503 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE));
504
505 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
506 tu_cs_emit(cs, 0x41);
507
508 uint32_t local_invocation_id =
509 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
510 uint32_t work_group_id =
511 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
512
513 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
514 tu_cs_emit(cs,
515 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
516 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
517 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
518 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
519 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
520
521 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_IBO_COUNT, 1);
522 tu_cs_emit(cs, v->image_mapping.num_ibo);
523 }
524
525 static void
526 tu6_emit_vs_system_values(struct tu_cs *cs,
527 const struct ir3_shader_variant *vs)
528 {
529 const uint32_t vertexid_regid =
530 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
531 const uint32_t instanceid_regid =
532 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
533
534 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
535 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
536 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
537 0xfcfc0000);
538 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
539 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
540 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
541 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_5 */
542 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
543 }
544
545 static void
546 tu6_emit_vpc(struct tu_cs *cs,
547 const struct ir3_shader_variant *vs,
548 const struct ir3_shader_variant *fs,
549 bool binning_pass)
550 {
551 struct ir3_shader_linkage linkage = { 0 };
552 ir3_link_shaders(&linkage, vs, fs);
553
554 if (vs->shader->stream_output.num_outputs && !binning_pass)
555 tu_finishme("stream output");
556
557 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
558 for (uint32_t i = 0; i < linkage.cnt; i++) {
559 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
560 for (uint32_t j = 0; j < comp_count; j++)
561 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
562 }
563
564 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
565 tu_cs_emit(cs, ~vpc_var_enables[0]);
566 tu_cs_emit(cs, ~vpc_var_enables[1]);
567 tu_cs_emit(cs, ~vpc_var_enables[2]);
568 tu_cs_emit(cs, ~vpc_var_enables[3]);
569
570 /* a6xx finds position/pointsize at the end */
571 const uint32_t position_regid =
572 ir3_find_output_regid(vs, VARYING_SLOT_POS);
573 const uint32_t pointsize_regid =
574 ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
575 uint32_t pointsize_loc = 0xff, position_loc = 0xff;
576 if (position_regid != regid(63, 0)) {
577 position_loc = linkage.max_loc;
578 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
579 }
580 if (pointsize_regid != regid(63, 0)) {
581 pointsize_loc = linkage.max_loc;
582 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
583 }
584
585 /* map vs outputs to VPC */
586 assert(linkage.cnt <= 32);
587 const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
588 const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
589 uint32_t sp_vs_out[16];
590 uint32_t sp_vs_vpc_dst[8];
591 sp_vs_out[sp_vs_out_count - 1] = 0;
592 sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
593 for (uint32_t i = 0; i < linkage.cnt; i++) {
594 ((uint16_t *) sp_vs_out)[i] =
595 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
596 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
597 ((uint8_t *) sp_vs_vpc_dst)[i] =
598 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
599 }
600
601 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
602 tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
603
604 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
605 tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
606
607 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
608 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
609 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
610 0xff00ff00);
611
612 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
613 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
614 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
615 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
616
617 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_SIV_CNTL, 1);
618 tu_cs_emit(cs, 0x0000ffff); /* XXX */
619
620 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
621 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
622
623 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
624 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
625 (vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
626 }
627
628 static int
629 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
630 uint32_t index,
631 uint8_t *interp_mode,
632 uint8_t *ps_repl_mode)
633 {
634 enum
635 {
636 INTERP_SMOOTH = 0,
637 INTERP_FLAT = 1,
638 INTERP_ZERO = 2,
639 INTERP_ONE = 3,
640 };
641 enum
642 {
643 PS_REPL_NONE = 0,
644 PS_REPL_S = 1,
645 PS_REPL_T = 2,
646 PS_REPL_ONE_MINUS_T = 3,
647 };
648
649 const uint32_t compmask = fs->inputs[index].compmask;
650
651 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
652 * fourth component occupy three consecutive varying slots
653 */
654 int shift = 0;
655 *interp_mode = 0;
656 *ps_repl_mode = 0;
657 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
658 if (compmask & 0x1) {
659 *ps_repl_mode |= PS_REPL_S << shift;
660 shift += 2;
661 }
662 if (compmask & 0x2) {
663 *ps_repl_mode |= PS_REPL_T << shift;
664 shift += 2;
665 }
666 if (compmask & 0x4) {
667 *interp_mode |= INTERP_ZERO << shift;
668 shift += 2;
669 }
670 if (compmask & 0x8) {
671 *interp_mode |= INTERP_ONE << 6;
672 shift += 2;
673 }
674 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
675 fs->inputs[index].rasterflat) {
676 for (int i = 0; i < 4; i++) {
677 if (compmask & (1 << i)) {
678 *interp_mode |= INTERP_FLAT << shift;
679 shift += 2;
680 }
681 }
682 }
683
684 return shift;
685 }
686
687 static void
688 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
689 const struct ir3_shader_variant *fs,
690 bool binning_pass)
691 {
692 uint32_t interp_modes[8] = { 0 };
693 uint32_t ps_repl_modes[8] = { 0 };
694
695 if (!binning_pass) {
696 for (int i = -1;
697 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
698
699 /* get the mode for input i */
700 uint8_t interp_mode;
701 uint8_t ps_repl_mode;
702 const int bits =
703 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
704
705 /* OR the mode into the array */
706 const uint32_t inloc = fs->inputs[i].inloc * 2;
707 uint32_t n = inloc / 32;
708 uint32_t shift = inloc % 32;
709 interp_modes[n] |= interp_mode << shift;
710 ps_repl_modes[n] |= ps_repl_mode << shift;
711 if (shift + bits > 32) {
712 n++;
713 shift = 32 - shift;
714
715 interp_modes[n] |= interp_mode >> shift;
716 ps_repl_modes[n] |= ps_repl_mode >> shift;
717 }
718 }
719 }
720
721 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
722 tu_cs_emit_array(cs, interp_modes, 8);
723
724 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
725 tu_cs_emit_array(cs, ps_repl_modes, 8);
726 }
727
728 static void
729 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
730 {
731 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
732 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
733 uint32_t smask_in_regid;
734
735 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
736 bool enable_varyings = fs->total_in > 0;
737
738 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
739 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
740 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
741 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
742 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
743 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
744 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
745 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
746 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
747
748 if (fs->num_sampler_prefetch > 0) {
749 assert(VALIDREG(ij_pix_regid));
750 /* also, it seems like ij_pix is *required* to be r0.x */
751 assert(ij_pix_regid == regid(0, 0));
752 }
753
754 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
755 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
756 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
757 0x7000); // XXX);
758 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
759 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
760 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
761 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
762 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
763 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
764 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
765 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
766 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
767 }
768
769 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
770 tu_cs_emit(cs, 0x7);
771 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
772 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
773 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
774 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
775 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
776 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
777 0xfc00fc00);
778 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
779 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
780 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
781 0x0000fc00);
782 tu_cs_emit(cs, 0xfc);
783
784 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
785 tu_cs_emit(cs, enable_varyings ? 3 : 1);
786
787 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A982, 1);
788 tu_cs_emit(cs, 0); /* XXX */
789
790 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
791 tu_cs_emit(cs, 0xff); /* XXX */
792
793 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
794 tu_cs_emit(cs,
795 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
796 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
797 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
798 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
799 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
800 COND(fs->frag_coord,
801 A6XX_GRAS_CNTL_SIZE |
802 A6XX_GRAS_CNTL_XCOORD |
803 A6XX_GRAS_CNTL_YCOORD |
804 A6XX_GRAS_CNTL_ZCOORD |
805 A6XX_GRAS_CNTL_WCOORD) |
806 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
807
808 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
809 tu_cs_emit(cs,
810 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
811 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
812 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
813 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
814 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
815 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
816 COND(fs->frag_coord,
817 A6XX_RB_RENDER_CONTROL0_SIZE |
818 A6XX_RB_RENDER_CONTROL0_XCOORD |
819 A6XX_RB_RENDER_CONTROL0_YCOORD |
820 A6XX_RB_RENDER_CONTROL0_ZCOORD |
821 A6XX_RB_RENDER_CONTROL0_WCOORD) |
822 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
823 tu_cs_emit(cs,
824 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
825 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
826 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
827 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
828 }
829
830 static void
831 tu6_emit_fs_outputs(struct tu_cs *cs,
832 const struct ir3_shader_variant *fs,
833 uint32_t mrt_count)
834 {
835 uint32_t smask_regid, posz_regid;
836
837 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
838 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
839
840 uint32_t fragdata_regid[8];
841 if (fs->color0_mrt) {
842 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
843 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
844 fragdata_regid[i] = fragdata_regid[0];
845 } else {
846 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
847 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
848 }
849
850 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
851 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
852 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
853 0xfc000000);
854 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
855
856 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
857 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
858 // TODO we could have a mix of half and full precision outputs,
859 // we really need to figure out half-precision from IR3_REG_HALF
860 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
861 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
862 }
863
864 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
865 tu_cs_emit(cs, fs->writes_pos ? A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z : 0);
866 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
867
868 uint32_t gras_su_depth_plane_cntl = 0;
869 uint32_t rb_depth_plane_cntl = 0;
870 if (fs->no_earlyz | fs->writes_pos) {
871 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
872 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
873 }
874
875 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
876 tu_cs_emit(cs, gras_su_depth_plane_cntl);
877
878 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
879 tu_cs_emit(cs, rb_depth_plane_cntl);
880 }
881
882 static void
883 tu6_emit_shader_object(struct tu_cs *cs,
884 gl_shader_stage stage,
885 const struct ir3_shader_variant *variant,
886 const struct tu_bo *binary_bo,
887 uint32_t binary_offset)
888 {
889 uint16_t reg;
890 uint8_t opcode;
891 enum a6xx_state_block sb;
892 switch (stage) {
893 case MESA_SHADER_VERTEX:
894 reg = REG_A6XX_SP_VS_OBJ_START_LO;
895 opcode = CP_LOAD_STATE6_GEOM;
896 sb = SB6_VS_SHADER;
897 break;
898 case MESA_SHADER_TESS_CTRL:
899 reg = REG_A6XX_SP_HS_OBJ_START_LO;
900 opcode = CP_LOAD_STATE6_GEOM;
901 sb = SB6_HS_SHADER;
902 break;
903 case MESA_SHADER_TESS_EVAL:
904 reg = REG_A6XX_SP_DS_OBJ_START_LO;
905 opcode = CP_LOAD_STATE6_GEOM;
906 sb = SB6_DS_SHADER;
907 break;
908 case MESA_SHADER_GEOMETRY:
909 reg = REG_A6XX_SP_GS_OBJ_START_LO;
910 opcode = CP_LOAD_STATE6_GEOM;
911 sb = SB6_GS_SHADER;
912 break;
913 case MESA_SHADER_FRAGMENT:
914 reg = REG_A6XX_SP_FS_OBJ_START_LO;
915 opcode = CP_LOAD_STATE6_FRAG;
916 sb = SB6_FS_SHADER;
917 break;
918 case MESA_SHADER_COMPUTE:
919 reg = REG_A6XX_SP_CS_OBJ_START_LO;
920 opcode = CP_LOAD_STATE6_FRAG;
921 sb = SB6_CS_SHADER;
922 break;
923 default:
924 unreachable("invalid gl_shader_stage");
925 opcode = CP_LOAD_STATE6_GEOM;
926 sb = SB6_VS_SHADER;
927 break;
928 }
929
930 if (!variant->instrlen) {
931 tu_cs_emit_pkt4(cs, reg, 2);
932 tu_cs_emit_qw(cs, 0);
933 return;
934 }
935
936 assert(variant->type == stage);
937
938 const uint64_t binary_iova = binary_bo->iova + binary_offset;
939 assert((binary_iova & 0x3) == 0);
940
941 tu_cs_emit_pkt4(cs, reg, 2);
942 tu_cs_emit_qw(cs, binary_iova);
943
944 /* always indirect */
945 const bool indirect = true;
946 if (indirect) {
947 tu_cs_emit_pkt7(cs, opcode, 3);
948 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
949 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
950 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
951 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
952 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
953 tu_cs_emit_qw(cs, binary_iova);
954 } else {
955 const void *binary = binary_bo->map + binary_offset;
956
957 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
958 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
959 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
960 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
961 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
962 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
963 tu_cs_emit_qw(cs, 0);
964 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
965 }
966 }
967
968 static void
969 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
970 uint32_t opcode, enum a6xx_state_block block)
971 {
972 /* dummy variant */
973 if (!v->shader)
974 return;
975
976 const struct ir3_const_state *const_state = &v->shader->const_state;
977 uint32_t base = const_state->offsets.immediate;
978 int size = const_state->immediates_count;
979
980 /* truncate size to avoid writing constants that shader
981 * does not use:
982 */
983 size = MIN2(size + base, v->constlen) - base;
984
985 if (size <= 0)
986 return;
987
988 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
989 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
990 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
991 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
992 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
993 CP_LOAD_STATE6_0_NUM_UNIT(size));
994 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
995 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
996
997 for (unsigned i = 0; i < size; i++) {
998 tu_cs_emit(cs, const_state->immediates[i].val[0]);
999 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1000 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1001 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1002 }
1003 }
1004
1005 static void
1006 tu6_emit_program(struct tu_cs *cs,
1007 const struct tu_pipeline_builder *builder,
1008 const struct tu_bo *binary_bo,
1009 bool binning_pass)
1010 {
1011 static const struct ir3_shader_variant dummy_variant = {
1012 .type = MESA_SHADER_NONE
1013 };
1014 assert(builder->shaders[MESA_SHADER_VERTEX]);
1015 const struct ir3_shader_variant *vs =
1016 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1017 const struct ir3_shader_variant *hs =
1018 builder->shaders[MESA_SHADER_TESS_CTRL]
1019 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1020 : &dummy_variant;
1021 const struct ir3_shader_variant *ds =
1022 builder->shaders[MESA_SHADER_TESS_EVAL]
1023 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1024 : &dummy_variant;
1025 const struct ir3_shader_variant *gs =
1026 builder->shaders[MESA_SHADER_GEOMETRY]
1027 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1028 : &dummy_variant;
1029 const struct ir3_shader_variant *fs =
1030 builder->shaders[MESA_SHADER_FRAGMENT]
1031 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1032 : &dummy_variant;
1033
1034 if (binning_pass) {
1035 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1036 fs = &dummy_variant;
1037 }
1038
1039 tu6_emit_vs_config(cs, vs);
1040 tu6_emit_hs_config(cs, hs);
1041 tu6_emit_ds_config(cs, ds);
1042 tu6_emit_gs_config(cs, gs);
1043 tu6_emit_fs_config(cs, fs);
1044
1045 tu6_emit_vs_system_values(cs, vs);
1046 tu6_emit_vpc(cs, vs, fs, binning_pass);
1047 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1048 tu6_emit_fs_inputs(cs, fs);
1049 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1050
1051 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1052 builder->shader_offsets[MESA_SHADER_VERTEX]);
1053
1054 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1055 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1056
1057 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1058 if (!binning_pass)
1059 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1060 }
1061
1062 static void
1063 tu6_emit_vertex_input(struct tu_cs *cs,
1064 const struct ir3_shader_variant *vs,
1065 const VkPipelineVertexInputStateCreateInfo *vi_info,
1066 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1067 uint16_t strides[MAX_VERTEX_ATTRIBS],
1068 uint16_t offsets[MAX_VERTEX_ATTRIBS],
1069 uint32_t *count)
1070 {
1071 uint32_t vfd_decode_idx = 0;
1072
1073 for (uint32_t i = 0; i < vs->inputs_count; i++) {
1074 if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
1075 continue;
1076
1077 const VkVertexInputAttributeDescription *vi_attr =
1078 tu_find_vertex_input_attribute(vi_info, vs->inputs[i].slot);
1079 const VkVertexInputBindingDescription *vi_binding =
1080 tu_find_vertex_input_binding(vi_info, vi_attr);
1081 assert(vi_attr && vi_binding);
1082
1083 const struct tu_native_format *format =
1084 tu6_get_native_format(vi_attr->format);
1085 assert(format && format->vtx >= 0);
1086
1087 uint32_t vfd_decode = A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx) |
1088 A6XX_VFD_DECODE_INSTR_FORMAT(format->vtx) |
1089 A6XX_VFD_DECODE_INSTR_SWAP(format->swap) |
1090 A6XX_VFD_DECODE_INSTR_UNK30;
1091 if (vi_binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1092 vfd_decode |= A6XX_VFD_DECODE_INSTR_INSTANCED;
1093 if (!vk_format_is_int(vi_attr->format))
1094 vfd_decode |= A6XX_VFD_DECODE_INSTR_FLOAT;
1095
1096 const uint32_t vfd_decode_step_rate = 1;
1097
1098 const uint32_t vfd_dest_cntl =
1099 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
1100 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid);
1101
1102 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE(vfd_decode_idx), 2);
1103 tu_cs_emit(cs, vfd_decode);
1104 tu_cs_emit(cs, vfd_decode_step_rate);
1105
1106 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx), 1);
1107 tu_cs_emit(cs, vfd_dest_cntl);
1108
1109 bindings[vfd_decode_idx] = vi_binding->binding;
1110 strides[vfd_decode_idx] = vi_binding->stride;
1111 offsets[vfd_decode_idx] = vi_attr->offset;
1112
1113 vfd_decode_idx++;
1114 assert(vfd_decode_idx <= MAX_VERTEX_ATTRIBS);
1115 }
1116
1117 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
1118 tu_cs_emit(
1119 cs, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx) | (vfd_decode_idx << 8));
1120
1121 *count = vfd_decode_idx;
1122 }
1123
1124 static uint32_t
1125 tu6_guardband_adj(uint32_t v)
1126 {
1127 if (v > 256)
1128 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1129 else
1130 return 511;
1131 }
1132
1133 void
1134 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1135 {
1136 float offsets[3];
1137 float scales[3];
1138 scales[0] = viewport->width / 2.0f;
1139 scales[1] = viewport->height / 2.0f;
1140 scales[2] = viewport->maxDepth - viewport->minDepth;
1141 offsets[0] = viewport->x + scales[0];
1142 offsets[1] = viewport->y + scales[1];
1143 offsets[2] = viewport->minDepth;
1144
1145 VkOffset2D min;
1146 VkOffset2D max;
1147 min.x = (int32_t) viewport->x;
1148 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1149 if (viewport->height >= 0.0f) {
1150 min.y = (int32_t) viewport->y;
1151 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1152 } else {
1153 min.y = (int32_t)(viewport->y + viewport->height);
1154 max.y = (int32_t) ceilf(viewport->y);
1155 }
1156 /* the spec allows viewport->height to be 0.0f */
1157 if (min.y == max.y)
1158 max.y++;
1159 assert(min.x >= 0 && min.x < max.x);
1160 assert(min.y >= 0 && min.y < max.y);
1161
1162 VkExtent2D guardband_adj;
1163 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1164 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1165
1166 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1167 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]));
1168 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]));
1169 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]));
1170 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]));
1171 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]));
1172 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]));
1173
1174 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1175 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1176 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1177 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1178 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1179
1180 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1181 tu_cs_emit(cs,
1182 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1183 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1184 }
1185
1186 void
1187 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1188 {
1189 const VkOffset2D min = scissor->offset;
1190 const VkOffset2D max = {
1191 scissor->offset.x + scissor->extent.width,
1192 scissor->offset.y + scissor->extent.height,
1193 };
1194
1195 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1196 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1197 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1198 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1199 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1200 }
1201
1202 static void
1203 tu6_emit_gras_unknowns(struct tu_cs *cs)
1204 {
1205 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8000, 1);
1206 tu_cs_emit(cs, 0x80);
1207 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1208 tu_cs_emit(cs, 0x0);
1209 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
1210 tu_cs_emit(cs, 0x0);
1211 }
1212
1213 static void
1214 tu6_emit_point_size(struct tu_cs *cs)
1215 {
1216 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1217 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1218 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1219 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f));
1220 }
1221
1222 static uint32_t
1223 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1224 VkSampleCountFlagBits samples)
1225 {
1226 uint32_t gras_su_cntl = 0;
1227
1228 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1229 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1230 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1231 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1232
1233 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1234 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1235
1236 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1237
1238 if (rast_info->depthBiasEnable)
1239 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1240
1241 if (samples > VK_SAMPLE_COUNT_1_BIT)
1242 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1243
1244 return gras_su_cntl;
1245 }
1246
1247 void
1248 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1249 uint32_t gras_su_cntl,
1250 float line_width)
1251 {
1252 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1253 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1254
1255 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1256 tu_cs_emit(cs, gras_su_cntl);
1257 }
1258
1259 void
1260 tu6_emit_depth_bias(struct tu_cs *cs,
1261 float constant_factor,
1262 float clamp,
1263 float slope_factor)
1264 {
1265 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1266 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor));
1267 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor));
1268 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp));
1269 }
1270
1271 static void
1272 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1273 {
1274 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1275 tu_cs_emit(cs, 0);
1276 }
1277
1278 static void
1279 tu6_emit_depth_control(struct tu_cs *cs,
1280 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1281 {
1282 assert(!ds_info->depthBoundsTestEnable);
1283
1284 uint32_t rb_depth_cntl = 0;
1285 if (ds_info->depthTestEnable) {
1286 rb_depth_cntl |=
1287 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1288 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1289 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1290
1291 if (ds_info->depthWriteEnable)
1292 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1293 }
1294
1295 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1296 tu_cs_emit(cs, rb_depth_cntl);
1297 }
1298
1299 static void
1300 tu6_emit_stencil_control(struct tu_cs *cs,
1301 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1302 {
1303 uint32_t rb_stencil_control = 0;
1304 if (ds_info->stencilTestEnable) {
1305 const VkStencilOpState *front = &ds_info->front;
1306 const VkStencilOpState *back = &ds_info->back;
1307 rb_stencil_control |=
1308 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1309 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1310 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1311 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1312 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1313 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1314 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1315 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1316 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1317 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1318 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1319 }
1320
1321 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1322 tu_cs_emit(cs, rb_stencil_control);
1323 }
1324
1325 void
1326 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1327 {
1328 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1329 tu_cs_emit(
1330 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1331 }
1332
1333 void
1334 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1335 {
1336 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1337 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1338 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1339 }
1340
1341 void
1342 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1343 {
1344 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1345 tu_cs_emit(cs,
1346 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1347 }
1348
1349 static uint32_t
1350 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1351 bool has_alpha)
1352 {
1353 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1354 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1355 has_alpha ? att->srcColorBlendFactor
1356 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1357 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1358 has_alpha ? att->dstColorBlendFactor
1359 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1360 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1361 const enum adreno_rb_blend_factor src_alpha_factor =
1362 tu6_blend_factor(att->srcAlphaBlendFactor);
1363 const enum adreno_rb_blend_factor dst_alpha_factor =
1364 tu6_blend_factor(att->dstAlphaBlendFactor);
1365
1366 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1367 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1368 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1369 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1370 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1371 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1372 }
1373
1374 static uint32_t
1375 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1376 uint32_t rb_mrt_control_rop,
1377 bool is_int,
1378 bool has_alpha)
1379 {
1380 uint32_t rb_mrt_control =
1381 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1382
1383 /* ignore blending and logic op for integer attachments */
1384 if (is_int) {
1385 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1386 return rb_mrt_control;
1387 }
1388
1389 rb_mrt_control |= rb_mrt_control_rop;
1390
1391 if (att->blendEnable) {
1392 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1393
1394 if (has_alpha)
1395 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1396 }
1397
1398 return rb_mrt_control;
1399 }
1400
1401 static void
1402 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1403 const VkPipelineColorBlendStateCreateInfo *blend_info,
1404 const VkFormat attachment_formats[MAX_RTS],
1405 uint32_t *blend_enable_mask)
1406 {
1407 *blend_enable_mask = 0;
1408
1409 bool rop_reads_dst = false;
1410 uint32_t rb_mrt_control_rop = 0;
1411 if (blend_info->logicOpEnable) {
1412 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1413 rb_mrt_control_rop =
1414 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1415 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1416 }
1417
1418 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1419 const VkPipelineColorBlendAttachmentState *att =
1420 &blend_info->pAttachments[i];
1421 const VkFormat format = attachment_formats[i];
1422
1423 uint32_t rb_mrt_control = 0;
1424 uint32_t rb_mrt_blend_control = 0;
1425 if (format != VK_FORMAT_UNDEFINED) {
1426 const bool is_int = vk_format_is_int(format);
1427 const bool has_alpha = vk_format_has_alpha(format);
1428
1429 rb_mrt_control =
1430 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1431 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1432
1433 if (att->blendEnable || rop_reads_dst)
1434 *blend_enable_mask |= 1 << i;
1435 }
1436
1437 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1438 tu_cs_emit(cs, rb_mrt_control);
1439 tu_cs_emit(cs, rb_mrt_blend_control);
1440 }
1441
1442 for (uint32_t i = blend_info->attachmentCount; i < MAX_RTS; i++) {
1443 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1444 tu_cs_emit(cs, 0);
1445 tu_cs_emit(cs, 0);
1446 }
1447 }
1448
1449 static void
1450 tu6_emit_blend_control(struct tu_cs *cs,
1451 uint32_t blend_enable_mask,
1452 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1453 {
1454 assert(!msaa_info->sampleShadingEnable);
1455 assert(!msaa_info->alphaToOneEnable);
1456
1457 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1458 if (blend_enable_mask)
1459 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1460 if (msaa_info->alphaToCoverageEnable)
1461 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1462
1463 const uint32_t sample_mask =
1464 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1465 : ((1 << msaa_info->rasterizationSamples) - 1);
1466
1467 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1468 uint32_t rb_blend_cntl =
1469 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1470 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1471 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1472 if (msaa_info->alphaToCoverageEnable)
1473 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1474
1475 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1476 tu_cs_emit(cs, sp_blend_cntl);
1477
1478 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1479 tu_cs_emit(cs, rb_blend_cntl);
1480 }
1481
1482 void
1483 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1484 {
1485 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1486 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1487 }
1488
1489 static VkResult
1490 tu_pipeline_create(struct tu_device *dev,
1491 const VkAllocationCallbacks *pAllocator,
1492 struct tu_pipeline **out_pipeline)
1493 {
1494 struct tu_pipeline *pipeline =
1495 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
1496 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1497 if (!pipeline)
1498 return VK_ERROR_OUT_OF_HOST_MEMORY;
1499
1500 tu_cs_init(&pipeline->cs, TU_CS_MODE_SUB_STREAM, 2048);
1501
1502 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1503 VkResult result = tu_cs_reserve_space(dev, &pipeline->cs, 2048);
1504 if (result != VK_SUCCESS) {
1505 vk_free2(&dev->alloc, pAllocator, pipeline);
1506 return result;
1507 }
1508
1509 *out_pipeline = pipeline;
1510
1511 return VK_SUCCESS;
1512 }
1513
1514 static VkResult
1515 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1516 {
1517 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1518 NULL
1519 };
1520 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1521 gl_shader_stage stage =
1522 tu_shader_stage(builder->create_info->pStages[i].stage);
1523 stage_infos[stage] = &builder->create_info->pStages[i];
1524 }
1525
1526 struct tu_shader_compile_options options;
1527 tu_shader_compile_options_init(&options, builder->create_info);
1528
1529 /* compile shaders in reverse order */
1530 struct tu_shader *next_stage_shader = NULL;
1531 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1532 stage > MESA_SHADER_NONE; stage--) {
1533 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1534 if (!stage_info)
1535 continue;
1536
1537 struct tu_shader *shader =
1538 tu_shader_create(builder->device, stage, stage_info, builder->alloc);
1539 if (!shader)
1540 return VK_ERROR_OUT_OF_HOST_MEMORY;
1541
1542 VkResult result =
1543 tu_shader_compile(builder->device, shader, next_stage_shader,
1544 &options, builder->alloc);
1545 if (result != VK_SUCCESS)
1546 return result;
1547
1548 builder->shaders[stage] = shader;
1549 builder->shader_offsets[stage] = builder->shader_total_size;
1550 builder->shader_total_size +=
1551 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1552
1553 next_stage_shader = shader;
1554 }
1555
1556 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1557 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1558 builder->binning_vs_offset = builder->shader_total_size;
1559 builder->shader_total_size +=
1560 sizeof(uint32_t) * vs->variants[1].info.sizedwords;
1561 }
1562
1563 return VK_SUCCESS;
1564 }
1565
1566 static VkResult
1567 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1568 struct tu_pipeline *pipeline)
1569 {
1570 struct tu_bo *bo = &pipeline->program.binary_bo;
1571
1572 VkResult result =
1573 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1574 if (result != VK_SUCCESS)
1575 return result;
1576
1577 result = tu_bo_map(builder->device, bo);
1578 if (result != VK_SUCCESS)
1579 return result;
1580
1581 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1582 const struct tu_shader *shader = builder->shaders[i];
1583 if (!shader)
1584 continue;
1585
1586 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1587 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1588 }
1589
1590 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1591 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1592 memcpy(bo->map + builder->binning_vs_offset, vs->binning_binary,
1593 sizeof(uint32_t) * vs->variants[1].info.sizedwords);
1594 }
1595
1596 return VK_SUCCESS;
1597 }
1598
1599 static void
1600 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1601 struct tu_pipeline *pipeline)
1602 {
1603 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1604 builder->create_info->pDynamicState;
1605
1606 if (!dynamic_info)
1607 return;
1608
1609 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1610 pipeline->dynamic_state.mask |=
1611 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1612 }
1613 }
1614
1615 static void
1616 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1617 struct tu_pipeline *pipeline)
1618 {
1619 struct tu_cs prog_cs;
1620 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1621 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false);
1622 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1623
1624 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1625 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true);
1626 pipeline->program.binning_state_ib =
1627 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1628
1629 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1630 if (!builder->shaders[i])
1631 continue;
1632
1633 struct tu_program_descriptor_linkage *link = &pipeline->program.link[i];
1634 struct ir3_shader *shader = builder->shaders[i]->variants[0].shader;
1635
1636 link->ubo_state = shader->ubo_state;
1637 link->const_state = shader->const_state;
1638 link->constlen = builder->shaders[i]->variants[0].constlen;
1639 link->texture_map = builder->shaders[i]->texture_map;
1640 link->sampler_map = builder->shaders[i]->sampler_map;
1641 link->ubo_map = builder->shaders[i]->ubo_map;
1642 link->ssbo_map = builder->shaders[i]->ssbo_map;
1643 link->image_mapping = builder->shaders[i]->variants[0].image_mapping;
1644 }
1645 }
1646
1647 static void
1648 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1649 struct tu_pipeline *pipeline)
1650 {
1651 const VkPipelineVertexInputStateCreateInfo *vi_info =
1652 builder->create_info->pVertexInputState;
1653 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1654
1655 struct tu_cs vi_cs;
1656 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1657 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1658 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1659 pipeline->vi.bindings, pipeline->vi.strides,
1660 pipeline->vi.offsets, &pipeline->vi.count);
1661 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1662
1663 if (vs->has_binning_pass) {
1664 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1665 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1666 tu6_emit_vertex_input(
1667 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1668 pipeline->vi.binning_strides, pipeline->vi.binning_offsets,
1669 &pipeline->vi.binning_count);
1670 pipeline->vi.binning_state_ib =
1671 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1672 }
1673 }
1674
1675 static void
1676 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1677 struct tu_pipeline *pipeline)
1678 {
1679 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1680 builder->create_info->pInputAssemblyState;
1681
1682 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
1683 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
1684 }
1685
1686 static void
1687 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
1688 struct tu_pipeline *pipeline)
1689 {
1690 /* The spec says:
1691 *
1692 * pViewportState is a pointer to an instance of the
1693 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1694 * pipeline has rasterization disabled."
1695 *
1696 * We leave the relevant registers stale in that case.
1697 */
1698 if (builder->rasterizer_discard)
1699 return;
1700
1701 const VkPipelineViewportStateCreateInfo *vp_info =
1702 builder->create_info->pViewportState;
1703
1704 struct tu_cs vp_cs;
1705 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 15, &vp_cs);
1706
1707 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
1708 assert(vp_info->viewportCount == 1);
1709 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
1710 }
1711
1712 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
1713 assert(vp_info->scissorCount == 1);
1714 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
1715 }
1716
1717 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
1718 }
1719
1720 static void
1721 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
1722 struct tu_pipeline *pipeline)
1723 {
1724 const VkPipelineRasterizationStateCreateInfo *rast_info =
1725 builder->create_info->pRasterizationState;
1726
1727 assert(!rast_info->depthClampEnable);
1728 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
1729
1730 struct tu_cs rast_cs;
1731 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 20, &rast_cs);
1732
1733 /* move to hw ctx init? */
1734 tu6_emit_gras_unknowns(&rast_cs);
1735 tu6_emit_point_size(&rast_cs);
1736
1737 const uint32_t gras_su_cntl =
1738 tu6_gras_su_cntl(rast_info, builder->samples);
1739
1740 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
1741 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
1742
1743 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
1744 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
1745 rast_info->depthBiasClamp,
1746 rast_info->depthBiasSlopeFactor);
1747 }
1748
1749 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
1750
1751 pipeline->rast.gras_su_cntl = gras_su_cntl;
1752 }
1753
1754 static void
1755 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
1756 struct tu_pipeline *pipeline)
1757 {
1758 /* The spec says:
1759 *
1760 * pDepthStencilState is a pointer to an instance of the
1761 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1762 * the pipeline has rasterization disabled or if the subpass of the
1763 * render pass the pipeline is created against does not use a
1764 * depth/stencil attachment.
1765 *
1766 * We disable both depth and stenil tests in those cases.
1767 */
1768 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
1769 const VkPipelineDepthStencilStateCreateInfo *ds_info =
1770 builder->use_depth_stencil_attachment
1771 ? builder->create_info->pDepthStencilState
1772 : &dummy_ds_info;
1773
1774 struct tu_cs ds_cs;
1775 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 12, &ds_cs);
1776
1777 /* move to hw ctx init? */
1778 tu6_emit_alpha_control_disable(&ds_cs);
1779
1780 tu6_emit_depth_control(&ds_cs, ds_info);
1781 tu6_emit_stencil_control(&ds_cs, ds_info);
1782
1783 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
1784 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
1785 ds_info->back.compareMask);
1786 }
1787 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
1788 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
1789 ds_info->back.writeMask);
1790 }
1791 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
1792 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
1793 ds_info->back.reference);
1794 }
1795
1796 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
1797 }
1798
1799 static void
1800 tu_pipeline_builder_parse_multisample_and_color_blend(
1801 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
1802 {
1803 /* The spec says:
1804 *
1805 * pMultisampleState is a pointer to an instance of the
1806 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1807 * has rasterization disabled.
1808 *
1809 * Also,
1810 *
1811 * pColorBlendState is a pointer to an instance of the
1812 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1813 * pipeline has rasterization disabled or if the subpass of the render
1814 * pass the pipeline is created against does not use any color
1815 * attachments.
1816 *
1817 * We leave the relevant registers stale when rasterization is disabled.
1818 */
1819 if (builder->rasterizer_discard)
1820 return;
1821
1822 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
1823 const VkPipelineMultisampleStateCreateInfo *msaa_info =
1824 builder->create_info->pMultisampleState;
1825 const VkPipelineColorBlendStateCreateInfo *blend_info =
1826 builder->use_color_attachments ? builder->create_info->pColorBlendState
1827 : &dummy_blend_info;
1828
1829 struct tu_cs blend_cs;
1830 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, MAX_RTS * 3 + 9,
1831 &blend_cs);
1832
1833 uint32_t blend_enable_mask;
1834 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
1835 builder->color_attachment_formats,
1836 &blend_enable_mask);
1837
1838 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
1839 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
1840
1841 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
1842
1843 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
1844 }
1845
1846 static void
1847 tu_pipeline_finish(struct tu_pipeline *pipeline,
1848 struct tu_device *dev,
1849 const VkAllocationCallbacks *alloc)
1850 {
1851 tu_cs_finish(dev, &pipeline->cs);
1852
1853 if (pipeline->program.binary_bo.gem_handle)
1854 tu_bo_finish(dev, &pipeline->program.binary_bo);
1855 }
1856
1857 static VkResult
1858 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
1859 struct tu_pipeline **pipeline)
1860 {
1861 VkResult result = tu_pipeline_create(builder->device, builder->alloc,
1862 pipeline);
1863 if (result != VK_SUCCESS)
1864 return result;
1865
1866 /* compile and upload shaders */
1867 result = tu_pipeline_builder_compile_shaders(builder);
1868 if (result == VK_SUCCESS)
1869 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
1870 if (result != VK_SUCCESS) {
1871 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
1872 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
1873 *pipeline = VK_NULL_HANDLE;
1874
1875 return result;
1876 }
1877
1878 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
1879 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
1880 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
1881 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
1882 tu_pipeline_builder_parse_viewport(builder, *pipeline);
1883 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
1884 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
1885 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
1886
1887 /* we should have reserved enough space upfront such that the CS never
1888 * grows
1889 */
1890 assert((*pipeline)->cs.bo_count == 1);
1891
1892 return VK_SUCCESS;
1893 }
1894
1895 static void
1896 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
1897 {
1898 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1899 if (!builder->shaders[i])
1900 continue;
1901 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
1902 }
1903 }
1904
1905 static void
1906 tu_pipeline_builder_init_graphics(
1907 struct tu_pipeline_builder *builder,
1908 struct tu_device *dev,
1909 struct tu_pipeline_cache *cache,
1910 const VkGraphicsPipelineCreateInfo *create_info,
1911 const VkAllocationCallbacks *alloc)
1912 {
1913 *builder = (struct tu_pipeline_builder) {
1914 .device = dev,
1915 .cache = cache,
1916 .create_info = create_info,
1917 .alloc = alloc,
1918 };
1919
1920 builder->rasterizer_discard =
1921 create_info->pRasterizationState->rasterizerDiscardEnable;
1922
1923 if (builder->rasterizer_discard) {
1924 builder->samples = VK_SAMPLE_COUNT_1_BIT;
1925 } else {
1926 builder->samples = create_info->pMultisampleState->rasterizationSamples;
1927
1928 const struct tu_render_pass *pass =
1929 tu_render_pass_from_handle(create_info->renderPass);
1930 const struct tu_subpass *subpass =
1931 &pass->subpasses[create_info->subpass];
1932
1933 builder->use_depth_stencil_attachment =
1934 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
1935
1936 assert(subpass->color_count == 0 ||
1937 subpass->color_count == create_info->pColorBlendState->attachmentCount);
1938 builder->color_attachment_count = subpass->color_count;
1939 for (uint32_t i = 0; i < subpass->color_count; i++) {
1940 const uint32_t a = subpass->color_attachments[i].attachment;
1941 if (a == VK_ATTACHMENT_UNUSED)
1942 continue;
1943
1944 builder->color_attachment_formats[i] = pass->attachments[a].format;
1945 builder->use_color_attachments = true;
1946 }
1947 }
1948 }
1949
1950 static VkResult
1951 tu_graphics_pipeline_create(VkDevice device,
1952 VkPipelineCache pipelineCache,
1953 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1954 const VkAllocationCallbacks *pAllocator,
1955 VkPipeline *pPipeline)
1956 {
1957 TU_FROM_HANDLE(tu_device, dev, device);
1958 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
1959
1960 struct tu_pipeline_builder builder;
1961 tu_pipeline_builder_init_graphics(&builder, dev, cache,
1962 pCreateInfo, pAllocator);
1963
1964 struct tu_pipeline *pipeline = NULL;
1965 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
1966 tu_pipeline_builder_finish(&builder);
1967
1968 if (result == VK_SUCCESS)
1969 *pPipeline = tu_pipeline_to_handle(pipeline);
1970 else
1971 *pPipeline = NULL;
1972
1973 return result;
1974 }
1975
1976 VkResult
1977 tu_CreateGraphicsPipelines(VkDevice device,
1978 VkPipelineCache pipelineCache,
1979 uint32_t count,
1980 const VkGraphicsPipelineCreateInfo *pCreateInfos,
1981 const VkAllocationCallbacks *pAllocator,
1982 VkPipeline *pPipelines)
1983 {
1984 VkResult final_result = VK_SUCCESS;
1985
1986 for (uint32_t i = 0; i < count; i++) {
1987 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
1988 &pCreateInfos[i], pAllocator,
1989 &pPipelines[i]);
1990
1991 if (result != VK_SUCCESS)
1992 final_result = result;
1993 }
1994
1995 return final_result;
1996 }
1997
1998 static void
1999 tu6_emit_compute_program(struct tu_cs *cs,
2000 struct tu_shader *shader,
2001 const struct tu_bo *binary_bo)
2002 {
2003 const struct ir3_shader_variant *v = &shader->variants[0];
2004
2005 tu6_emit_cs_config(cs, v);
2006
2007 /* The compute program is the only one in the pipeline, so 0 offset. */
2008 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2009
2010 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2011 }
2012
2013 static VkResult
2014 tu_compute_upload_shader(VkDevice device,
2015 struct tu_pipeline *pipeline,
2016 struct tu_shader *shader)
2017 {
2018 TU_FROM_HANDLE(tu_device, dev, device);
2019 struct tu_bo *bo = &pipeline->program.binary_bo;
2020 struct ir3_shader_variant *v = &shader->variants[0];
2021
2022 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2023 VkResult result =
2024 tu_bo_init_new(dev, bo, shader_size);
2025 if (result != VK_SUCCESS)
2026 return result;
2027
2028 result = tu_bo_map(dev, bo);
2029 if (result != VK_SUCCESS)
2030 return result;
2031
2032 memcpy(bo->map, shader->binary, shader_size);
2033
2034 return VK_SUCCESS;
2035 }
2036
2037
2038 static VkResult
2039 tu_compute_pipeline_create(VkDevice device,
2040 VkPipelineCache _cache,
2041 const VkComputePipelineCreateInfo *pCreateInfo,
2042 const VkAllocationCallbacks *pAllocator,
2043 VkPipeline *pPipeline)
2044 {
2045 TU_FROM_HANDLE(tu_device, dev, device);
2046 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2047 VkResult result;
2048
2049 struct tu_pipeline *pipeline;
2050
2051 result = tu_pipeline_create(dev, pAllocator, &pipeline);
2052 if (result != VK_SUCCESS)
2053 return result;
2054
2055 struct tu_shader_compile_options options;
2056 tu_shader_compile_options_init(&options, NULL);
2057
2058 struct tu_shader *shader =
2059 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, pAllocator);
2060 if (!shader) {
2061 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2062 goto fail;
2063 }
2064
2065 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2066 if (result != VK_SUCCESS)
2067 return result;
2068
2069 struct tu_program_descriptor_linkage *link = &pipeline->program.link[MESA_SHADER_COMPUTE];
2070 struct ir3_shader_variant *v = &shader->variants[0];
2071
2072 link->ubo_state = v->shader->ubo_state;
2073 link->const_state = v->shader->const_state;
2074 link->constlen = v->constlen;
2075 link->texture_map = shader->texture_map;
2076 link->sampler_map = shader->sampler_map;
2077 link->ubo_map = shader->ubo_map;
2078 link->ssbo_map = shader->ssbo_map;
2079 link->image_mapping = v->image_mapping;
2080
2081 result = tu_compute_upload_shader(device, pipeline, shader);
2082 if (result != VK_SUCCESS)
2083 return result;
2084
2085 for (int i = 0; i < 3; i++)
2086 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2087
2088 struct tu_cs prog_cs;
2089 tu_cs_begin_sub_stream(dev, &pipeline->cs, 512, &prog_cs);
2090 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2091 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2092
2093 *pPipeline = tu_pipeline_to_handle(pipeline);
2094 return VK_SUCCESS;
2095
2096 fail:
2097 tu_shader_destroy(dev, shader, pAllocator);
2098 if (result != VK_SUCCESS) {
2099 tu_pipeline_finish(pipeline, dev, pAllocator);
2100 vk_free2(&dev->alloc, pAllocator, pipeline);
2101 }
2102
2103 return result;
2104 }
2105
2106 VkResult
2107 tu_CreateComputePipelines(VkDevice device,
2108 VkPipelineCache pipelineCache,
2109 uint32_t count,
2110 const VkComputePipelineCreateInfo *pCreateInfos,
2111 const VkAllocationCallbacks *pAllocator,
2112 VkPipeline *pPipelines)
2113 {
2114 VkResult final_result = VK_SUCCESS;
2115
2116 for (uint32_t i = 0; i < count; i++) {
2117 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2118 &pCreateInfos[i],
2119 pAllocator, &pPipelines[i]);
2120 if (result != VK_SUCCESS)
2121 final_result = result;
2122 }
2123
2124 return final_result;
2125 }
2126
2127 void
2128 tu_DestroyPipeline(VkDevice _device,
2129 VkPipeline _pipeline,
2130 const VkAllocationCallbacks *pAllocator)
2131 {
2132 TU_FROM_HANDLE(tu_device, dev, _device);
2133 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2134
2135 if (!_pipeline)
2136 return;
2137
2138 tu_pipeline_finish(pipeline, dev, pAllocator);
2139 vk_free2(&dev->alloc, pAllocator, pipeline);
2140 }