2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "main/menums.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
42 struct tu_pipeline_builder
44 struct tu_device
*device
;
45 struct tu_pipeline_cache
*cache
;
46 const VkAllocationCallbacks
*alloc
;
47 const VkGraphicsPipelineCreateInfo
*create_info
;
49 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
50 uint32_t shader_offsets
[MESA_SHADER_STAGES
];
51 uint32_t binning_vs_offset
;
52 uint32_t shader_total_size
;
54 bool rasterizer_discard
;
55 /* these states are affectd by rasterizer_discard */
56 VkSampleCountFlagBits samples
;
57 bool use_depth_stencil_attachment
;
58 bool use_color_attachments
;
59 uint32_t color_attachment_count
;
60 VkFormat color_attachment_formats
[MAX_RTS
];
63 static enum tu_dynamic_state_bits
64 tu_dynamic_state_bit(VkDynamicState state
)
67 case VK_DYNAMIC_STATE_VIEWPORT
:
68 return TU_DYNAMIC_VIEWPORT
;
69 case VK_DYNAMIC_STATE_SCISSOR
:
70 return TU_DYNAMIC_SCISSOR
;
71 case VK_DYNAMIC_STATE_LINE_WIDTH
:
72 return TU_DYNAMIC_LINE_WIDTH
;
73 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
74 return TU_DYNAMIC_DEPTH_BIAS
;
75 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
76 return TU_DYNAMIC_BLEND_CONSTANTS
;
77 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
78 return TU_DYNAMIC_DEPTH_BOUNDS
;
79 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
80 return TU_DYNAMIC_STENCIL_COMPARE_MASK
;
81 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
82 return TU_DYNAMIC_STENCIL_WRITE_MASK
;
83 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
84 return TU_DYNAMIC_STENCIL_REFERENCE
;
86 unreachable("invalid dynamic state");
91 static gl_shader_stage
92 tu_shader_stage(VkShaderStageFlagBits stage
)
95 case VK_SHADER_STAGE_VERTEX_BIT
:
96 return MESA_SHADER_VERTEX
;
97 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
98 return MESA_SHADER_TESS_CTRL
;
99 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
100 return MESA_SHADER_TESS_EVAL
;
101 case VK_SHADER_STAGE_GEOMETRY_BIT
:
102 return MESA_SHADER_GEOMETRY
;
103 case VK_SHADER_STAGE_FRAGMENT_BIT
:
104 return MESA_SHADER_FRAGMENT
;
105 case VK_SHADER_STAGE_COMPUTE_BIT
:
106 return MESA_SHADER_COMPUTE
;
108 unreachable("invalid VkShaderStageFlagBits");
109 return MESA_SHADER_NONE
;
113 static const VkVertexInputAttributeDescription
*
114 tu_find_vertex_input_attribute(
115 const VkPipelineVertexInputStateCreateInfo
*vi_info
, uint32_t slot
)
117 assert(slot
>= VERT_ATTRIB_GENERIC0
);
118 slot
-= VERT_ATTRIB_GENERIC0
;
119 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
120 if (vi_info
->pVertexAttributeDescriptions
[i
].location
== slot
)
121 return &vi_info
->pVertexAttributeDescriptions
[i
];
126 static const VkVertexInputBindingDescription
*
127 tu_find_vertex_input_binding(
128 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
129 const VkVertexInputAttributeDescription
*vi_attr
)
132 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
133 if (vi_info
->pVertexBindingDescriptions
[i
].binding
== vi_attr
->binding
)
134 return &vi_info
->pVertexBindingDescriptions
[i
];
140 tu_logic_op_reads_dst(VkLogicOp op
)
143 case VK_LOGIC_OP_CLEAR
:
144 case VK_LOGIC_OP_COPY
:
145 case VK_LOGIC_OP_COPY_INVERTED
:
146 case VK_LOGIC_OP_SET
:
154 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
156 /* treat dst alpha as 1.0 and avoid reading it */
158 case VK_BLEND_FACTOR_DST_ALPHA
:
159 return VK_BLEND_FACTOR_ONE
;
160 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
161 return VK_BLEND_FACTOR_ZERO
;
167 static enum pc_di_primtype
168 tu6_primtype(VkPrimitiveTopology topology
)
171 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
172 return DI_PT_POINTLIST
;
173 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
174 return DI_PT_LINELIST
;
175 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
176 return DI_PT_LINESTRIP
;
177 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
178 return DI_PT_TRILIST
;
179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
180 return DI_PT_TRISTRIP
;
181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
184 return DI_PT_LINE_ADJ
;
185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
186 return DI_PT_LINESTRIP_ADJ
;
187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
188 return DI_PT_TRI_ADJ
;
189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
190 return DI_PT_TRISTRIP_ADJ
;
191 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
193 unreachable("invalid primitive topology");
198 static enum adreno_compare_func
199 tu6_compare_func(VkCompareOp op
)
202 case VK_COMPARE_OP_NEVER
:
204 case VK_COMPARE_OP_LESS
:
206 case VK_COMPARE_OP_EQUAL
:
208 case VK_COMPARE_OP_LESS_OR_EQUAL
:
210 case VK_COMPARE_OP_GREATER
:
212 case VK_COMPARE_OP_NOT_EQUAL
:
213 return FUNC_NOTEQUAL
;
214 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
216 case VK_COMPARE_OP_ALWAYS
:
219 unreachable("invalid VkCompareOp");
224 static enum adreno_stencil_op
225 tu6_stencil_op(VkStencilOp op
)
228 case VK_STENCIL_OP_KEEP
:
230 case VK_STENCIL_OP_ZERO
:
232 case VK_STENCIL_OP_REPLACE
:
233 return STENCIL_REPLACE
;
234 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
235 return STENCIL_INCR_CLAMP
;
236 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
237 return STENCIL_DECR_CLAMP
;
238 case VK_STENCIL_OP_INVERT
:
239 return STENCIL_INVERT
;
240 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
241 return STENCIL_INCR_WRAP
;
242 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
243 return STENCIL_DECR_WRAP
;
245 unreachable("invalid VkStencilOp");
250 static enum a3xx_rop_code
251 tu6_rop(VkLogicOp op
)
254 case VK_LOGIC_OP_CLEAR
:
256 case VK_LOGIC_OP_AND
:
258 case VK_LOGIC_OP_AND_REVERSE
:
259 return ROP_AND_REVERSE
;
260 case VK_LOGIC_OP_COPY
:
262 case VK_LOGIC_OP_AND_INVERTED
:
263 return ROP_AND_INVERTED
;
264 case VK_LOGIC_OP_NO_OP
:
266 case VK_LOGIC_OP_XOR
:
270 case VK_LOGIC_OP_NOR
:
272 case VK_LOGIC_OP_EQUIVALENT
:
274 case VK_LOGIC_OP_INVERT
:
276 case VK_LOGIC_OP_OR_REVERSE
:
277 return ROP_OR_REVERSE
;
278 case VK_LOGIC_OP_COPY_INVERTED
:
279 return ROP_COPY_INVERTED
;
280 case VK_LOGIC_OP_OR_INVERTED
:
281 return ROP_OR_INVERTED
;
282 case VK_LOGIC_OP_NAND
:
284 case VK_LOGIC_OP_SET
:
287 unreachable("invalid VkLogicOp");
292 static enum adreno_rb_blend_factor
293 tu6_blend_factor(VkBlendFactor factor
)
296 case VK_BLEND_FACTOR_ZERO
:
298 case VK_BLEND_FACTOR_ONE
:
300 case VK_BLEND_FACTOR_SRC_COLOR
:
301 return FACTOR_SRC_COLOR
;
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
303 return FACTOR_ONE_MINUS_SRC_COLOR
;
304 case VK_BLEND_FACTOR_DST_COLOR
:
305 return FACTOR_DST_COLOR
;
306 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
307 return FACTOR_ONE_MINUS_DST_COLOR
;
308 case VK_BLEND_FACTOR_SRC_ALPHA
:
309 return FACTOR_SRC_ALPHA
;
310 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
311 return FACTOR_ONE_MINUS_SRC_ALPHA
;
312 case VK_BLEND_FACTOR_DST_ALPHA
:
313 return FACTOR_DST_ALPHA
;
314 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
315 return FACTOR_ONE_MINUS_DST_ALPHA
;
316 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
317 return FACTOR_CONSTANT_COLOR
;
318 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
319 return FACTOR_ONE_MINUS_CONSTANT_COLOR
;
320 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
321 return FACTOR_CONSTANT_ALPHA
;
322 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
323 return FACTOR_ONE_MINUS_CONSTANT_ALPHA
;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
325 return FACTOR_SRC_ALPHA_SATURATE
;
326 case VK_BLEND_FACTOR_SRC1_COLOR
:
327 return FACTOR_SRC1_COLOR
;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
329 return FACTOR_ONE_MINUS_SRC1_COLOR
;
330 case VK_BLEND_FACTOR_SRC1_ALPHA
:
331 return FACTOR_SRC1_ALPHA
;
332 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
333 return FACTOR_ONE_MINUS_SRC1_ALPHA
;
335 unreachable("invalid VkBlendFactor");
340 static enum a3xx_rb_blend_opcode
341 tu6_blend_op(VkBlendOp op
)
344 case VK_BLEND_OP_ADD
:
345 return BLEND_DST_PLUS_SRC
;
346 case VK_BLEND_OP_SUBTRACT
:
347 return BLEND_SRC_MINUS_DST
;
348 case VK_BLEND_OP_REVERSE_SUBTRACT
:
349 return BLEND_DST_MINUS_SRC
;
350 case VK_BLEND_OP_MIN
:
351 return BLEND_MIN_DST_SRC
;
352 case VK_BLEND_OP_MAX
:
353 return BLEND_MAX_DST_SRC
;
355 unreachable("invalid VkBlendOp");
356 return BLEND_DST_PLUS_SRC
;
361 tu6_emit_vs_config(struct tu_cs
*cs
, const struct ir3_shader_variant
*vs
)
363 uint32_t sp_vs_ctrl
=
364 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
365 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
366 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
367 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
);
369 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
;
371 uint32_t sp_vs_config
= A6XX_SP_VS_CONFIG_NTEX(vs
->num_samp
) |
372 A6XX_SP_VS_CONFIG_NSAMP(vs
->num_samp
);
374 sp_vs_config
|= A6XX_SP_VS_CONFIG_ENABLED
;
376 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
377 tu_cs_emit(cs
, sp_vs_ctrl
);
379 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CONFIG
, 2);
380 tu_cs_emit(cs
, sp_vs_config
);
381 tu_cs_emit(cs
, vs
->instrlen
);
383 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_VS_CNTL
, 1);
384 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs
->constlen
, 4)) |
385 A6XX_HLSQ_VS_CNTL_ENABLED
);
389 tu6_emit_hs_config(struct tu_cs
*cs
, const struct ir3_shader_variant
*hs
)
391 uint32_t sp_hs_config
= 0;
393 sp_hs_config
|= A6XX_SP_HS_CONFIG_ENABLED
;
395 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
398 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_CONFIG
, 2);
399 tu_cs_emit(cs
, sp_hs_config
);
400 tu_cs_emit(cs
, hs
->instrlen
);
402 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_HS_CNTL
, 1);
403 tu_cs_emit(cs
, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs
->constlen
, 4)));
407 tu6_emit_ds_config(struct tu_cs
*cs
, const struct ir3_shader_variant
*ds
)
409 uint32_t sp_ds_config
= 0;
411 sp_ds_config
|= A6XX_SP_DS_CONFIG_ENABLED
;
413 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_CONFIG
, 2);
414 tu_cs_emit(cs
, sp_ds_config
);
415 tu_cs_emit(cs
, ds
->instrlen
);
417 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_DS_CNTL
, 1);
418 tu_cs_emit(cs
, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds
->constlen
, 4)));
422 tu6_emit_gs_config(struct tu_cs
*cs
, const struct ir3_shader_variant
*gs
)
424 uint32_t sp_gs_config
= 0;
426 sp_gs_config
|= A6XX_SP_GS_CONFIG_ENABLED
;
428 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
431 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CONFIG
, 2);
432 tu_cs_emit(cs
, sp_gs_config
);
433 tu_cs_emit(cs
, gs
->instrlen
);
435 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_GS_CNTL
, 1);
436 tu_cs_emit(cs
, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs
->constlen
, 4)));
440 tu6_emit_fs_config(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
442 uint32_t sp_fs_ctrl
=
443 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) | 0x1000000 |
444 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
445 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
446 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
);
447 if (fs
->total_in
> 0 || fs
->frag_coord
)
448 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_VARYING
;
450 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
;
452 uint32_t sp_fs_config
= A6XX_SP_FS_CONFIG_NTEX(fs
->num_samp
) |
453 A6XX_SP_FS_CONFIG_NSAMP(fs
->num_samp
);
455 sp_fs_config
|= A6XX_SP_FS_CONFIG_ENABLED
;
457 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
460 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
463 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
464 tu_cs_emit(cs
, sp_fs_ctrl
);
466 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CONFIG
, 2);
467 tu_cs_emit(cs
, sp_fs_config
);
468 tu_cs_emit(cs
, fs
->instrlen
);
470 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_FS_CNTL
, 1);
471 tu_cs_emit(cs
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs
->constlen
, 4)) |
472 A6XX_HLSQ_FS_CNTL_ENABLED
);
476 tu6_emit_vs_system_values(struct tu_cs
*cs
,
477 const struct ir3_shader_variant
*vs
)
479 const uint32_t vertexid_regid
=
480 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
481 const uint32_t instanceid_regid
=
482 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
484 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
485 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
486 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
488 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_2 */
489 tu_cs_emit(cs
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
490 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
491 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_5 */
492 tu_cs_emit(cs
, 0x00000000); /* VFD_CONTROL_6 */
496 tu6_emit_vpc(struct tu_cs
*cs
,
497 const struct ir3_shader_variant
*vs
,
498 const struct ir3_shader_variant
*fs
,
501 struct ir3_shader_linkage linkage
= { 0 };
502 ir3_link_shaders(&linkage
, vs
, fs
);
504 if (vs
->shader
->stream_output
.num_outputs
&& !binning_pass
)
505 tu_finishme("stream output");
507 BITSET_DECLARE(vpc_var_enables
, 128) = { 0 };
508 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
509 const uint32_t comp_count
= util_last_bit(linkage
.var
[i
].compmask
);
510 for (uint32_t j
= 0; j
< comp_count
; j
++)
511 BITSET_SET(vpc_var_enables
, linkage
.var
[i
].loc
+ j
);
514 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
515 tu_cs_emit(cs
, ~vpc_var_enables
[0]);
516 tu_cs_emit(cs
, ~vpc_var_enables
[1]);
517 tu_cs_emit(cs
, ~vpc_var_enables
[2]);
518 tu_cs_emit(cs
, ~vpc_var_enables
[3]);
520 /* a6xx finds position/pointsize at the end */
521 const uint32_t position_regid
=
522 ir3_find_output_regid(vs
, VARYING_SLOT_POS
);
523 const uint32_t pointsize_regid
=
524 ir3_find_output_regid(vs
, VARYING_SLOT_PSIZ
);
525 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff;
526 if (position_regid
!= regid(63, 0)) {
527 position_loc
= linkage
.max_loc
;
528 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
530 if (pointsize_regid
!= regid(63, 0)) {
531 pointsize_loc
= linkage
.max_loc
;
532 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
535 /* map vs outputs to VPC */
536 assert(linkage
.cnt
<= 32);
537 const uint32_t sp_vs_out_count
= (linkage
.cnt
+ 1) / 2;
538 const uint32_t sp_vs_vpc_dst_count
= (linkage
.cnt
+ 3) / 4;
539 uint32_t sp_vs_out
[16];
540 uint32_t sp_vs_vpc_dst
[8];
541 sp_vs_out
[sp_vs_out_count
- 1] = 0;
542 sp_vs_vpc_dst
[sp_vs_vpc_dst_count
- 1] = 0;
543 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
544 ((uint16_t *) sp_vs_out
)[i
] =
545 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
546 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
547 ((uint8_t *) sp_vs_vpc_dst
)[i
] =
548 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
551 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count
);
552 tu_cs_emit_array(cs
, sp_vs_out
, sp_vs_out_count
);
554 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count
);
555 tu_cs_emit_array(cs
, sp_vs_vpc_dst
, sp_vs_vpc_dst_count
);
557 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
558 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
559 (fs
->total_in
> 0 ? A6XX_VPC_CNTL_0_VARYING
: 0) |
562 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
563 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
564 A6XX_VPC_PACK_PSIZELOC(pointsize_loc
) |
565 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
567 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
568 tu_cs_emit(cs
, 0x0000ffff); /* XXX */
570 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
571 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage
.cnt
));
573 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
574 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage
.max_loc
) |
575 (vs
->writes_psize
? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
: 0));
579 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
581 uint8_t *interp_mode
,
582 uint8_t *ps_repl_mode
)
596 PS_REPL_ONE_MINUS_T
= 3,
599 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
601 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
602 * fourth component occupy three consecutive varying slots
607 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
608 if (compmask
& 0x1) {
609 *ps_repl_mode
|= PS_REPL_S
<< shift
;
612 if (compmask
& 0x2) {
613 *ps_repl_mode
|= PS_REPL_T
<< shift
;
616 if (compmask
& 0x4) {
617 *interp_mode
|= INTERP_ZERO
<< shift
;
620 if (compmask
& 0x8) {
621 *interp_mode
|= INTERP_ONE
<< 6;
624 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
625 fs
->inputs
[index
].rasterflat
) {
626 for (int i
= 0; i
< 4; i
++) {
627 if (compmask
& (1 << i
)) {
628 *interp_mode
|= INTERP_FLAT
<< shift
;
638 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
639 const struct ir3_shader_variant
*fs
,
642 uint32_t interp_modes
[8] = { 0 };
643 uint32_t ps_repl_modes
[8] = { 0 };
647 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
649 /* get the mode for input i */
651 uint8_t ps_repl_mode
;
653 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
655 /* OR the mode into the array */
656 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
657 uint32_t n
= inloc
/ 32;
658 uint32_t shift
= inloc
% 32;
659 interp_modes
[n
] |= interp_mode
<< shift
;
660 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
661 if (shift
+ bits
> 32) {
665 interp_modes
[n
] |= interp_mode
>> shift
;
666 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
671 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
672 tu_cs_emit_array(cs
, interp_modes
, 8);
674 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
675 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
678 #define VALIDREG(r) ((r) != regid(63,0))
679 #define CONDREG(r, val) COND(VALIDREG(r), (val))
682 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
684 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
685 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
686 uint32_t smask_in_regid
;
688 bool sample_shading
= fs
->per_samp
; /* TODO | key->sample_shading; */
689 bool enable_varyings
= fs
->total_in
> 0;
691 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
692 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
693 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
694 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
695 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
696 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
);
697 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SAMPLE
);
698 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_CENTROID
);
699 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SIZE
);
701 if (fs
->num_sampler_prefetch
> 0) {
702 assert(VALIDREG(ij_pix_regid
));
703 /* also, it seems like ij_pix is *required* to be r0.x */
704 assert(ij_pix_regid
== regid(0, 0));
707 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
708 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
709 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
711 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
712 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
713 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
714 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
715 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
716 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
717 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
718 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
719 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
722 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
724 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
725 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
726 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
727 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
728 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
729 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
731 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
732 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
733 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
735 tu_cs_emit(cs
, 0xfc);
737 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
738 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
740 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_A982
, 1);
741 tu_cs_emit(cs
, 0); /* XXX */
743 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
744 tu_cs_emit(cs
, 0xff); /* XXX */
746 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
748 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
749 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
750 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
751 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
752 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
754 A6XX_GRAS_CNTL_SIZE
|
755 A6XX_GRAS_CNTL_XCOORD
|
756 A6XX_GRAS_CNTL_YCOORD
|
757 A6XX_GRAS_CNTL_ZCOORD
|
758 A6XX_GRAS_CNTL_WCOORD
) |
759 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
761 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
763 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
764 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
765 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
766 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
767 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
768 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
770 A6XX_RB_RENDER_CONTROL0_SIZE
|
771 A6XX_RB_RENDER_CONTROL0_XCOORD
|
772 A6XX_RB_RENDER_CONTROL0_YCOORD
|
773 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
774 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
775 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
777 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
778 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
779 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
780 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
784 tu6_emit_fs_outputs(struct tu_cs
*cs
,
785 const struct ir3_shader_variant
*fs
,
788 uint32_t smask_regid
, posz_regid
;
790 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
791 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
793 uint32_t fragdata_regid
[8];
794 if (fs
->color0_mrt
) {
795 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
796 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
797 fragdata_regid
[i
] = fragdata_regid
[0];
799 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
800 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
803 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
804 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
805 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
807 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
809 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
810 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
811 // TODO we could have a mix of half and full precision outputs,
812 // we really need to figure out half-precision from IR3_REG_HALF
813 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
814 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
817 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
818 tu_cs_emit(cs
, fs
->writes_pos
? A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
: 0);
819 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
821 uint32_t gras_su_depth_plane_cntl
= 0;
822 uint32_t rb_depth_plane_cntl
= 0;
823 if (fs
->no_earlyz
| fs
->writes_pos
) {
824 gras_su_depth_plane_cntl
|= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
825 rb_depth_plane_cntl
|= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
828 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
829 tu_cs_emit(cs
, gras_su_depth_plane_cntl
);
831 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
832 tu_cs_emit(cs
, rb_depth_plane_cntl
);
836 tu6_emit_shader_object(struct tu_cs
*cs
,
837 gl_shader_stage stage
,
838 const struct ir3_shader_variant
*variant
,
839 const struct tu_bo
*binary_bo
,
840 uint32_t binary_offset
)
844 enum a6xx_state_block sb
;
846 case MESA_SHADER_VERTEX
:
847 reg
= REG_A6XX_SP_VS_OBJ_START_LO
;
848 opcode
= CP_LOAD_STATE6_GEOM
;
851 case MESA_SHADER_TESS_CTRL
:
852 reg
= REG_A6XX_SP_HS_OBJ_START_LO
;
853 opcode
= CP_LOAD_STATE6_GEOM
;
856 case MESA_SHADER_TESS_EVAL
:
857 reg
= REG_A6XX_SP_DS_OBJ_START_LO
;
858 opcode
= CP_LOAD_STATE6_GEOM
;
861 case MESA_SHADER_GEOMETRY
:
862 reg
= REG_A6XX_SP_GS_OBJ_START_LO
;
863 opcode
= CP_LOAD_STATE6_GEOM
;
866 case MESA_SHADER_FRAGMENT
:
867 reg
= REG_A6XX_SP_FS_OBJ_START_LO
;
868 opcode
= CP_LOAD_STATE6_FRAG
;
871 case MESA_SHADER_COMPUTE
:
872 reg
= REG_A6XX_SP_CS_OBJ_START_LO
;
873 opcode
= CP_LOAD_STATE6_FRAG
;
877 unreachable("invalid gl_shader_stage");
878 opcode
= CP_LOAD_STATE6_GEOM
;
883 if (!variant
->instrlen
) {
884 tu_cs_emit_pkt4(cs
, reg
, 2);
885 tu_cs_emit_qw(cs
, 0);
889 assert(variant
->type
== stage
);
891 const uint64_t binary_iova
= binary_bo
->iova
+ binary_offset
;
892 assert((binary_iova
& 0x3) == 0);
894 tu_cs_emit_pkt4(cs
, reg
, 2);
895 tu_cs_emit_qw(cs
, binary_iova
);
897 /* always indirect */
898 const bool indirect
= true;
900 tu_cs_emit_pkt7(cs
, opcode
, 3);
901 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
902 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
903 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
904 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
905 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
906 tu_cs_emit_qw(cs
, binary_iova
);
908 const void *binary
= binary_bo
->map
+ binary_offset
;
910 tu_cs_emit_pkt7(cs
, opcode
, 3 + variant
->info
.sizedwords
);
911 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
912 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
913 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
914 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
915 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
916 tu_cs_emit_qw(cs
, 0);
917 tu_cs_emit_array(cs
, binary
, variant
->info
.sizedwords
);
922 tu6_emit_immediates(struct tu_cs
*cs
, const struct ir3_shader_variant
*v
,
923 uint32_t opcode
, enum a6xx_state_block block
)
929 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
930 uint32_t base
= const_state
->offsets
.immediate
;
931 int size
= const_state
->immediates_count
;
933 /* truncate size to avoid writing constants that shader
936 size
= MIN2(size
+ base
, v
->constlen
) - base
;
941 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
* 4);
942 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
943 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
944 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
945 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
946 CP_LOAD_STATE6_0_NUM_UNIT(size
));
947 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
948 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
950 for (unsigned i
= 0; i
< size
; i
++) {
951 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
952 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
953 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
954 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
959 tu6_emit_program(struct tu_cs
*cs
,
960 const struct tu_pipeline_builder
*builder
,
961 const struct tu_bo
*binary_bo
,
964 static const struct ir3_shader_variant dummy_variant
= {
965 .type
= MESA_SHADER_NONE
967 assert(builder
->shaders
[MESA_SHADER_VERTEX
]);
968 const struct ir3_shader_variant
*vs
=
969 &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[0];
970 const struct ir3_shader_variant
*hs
=
971 builder
->shaders
[MESA_SHADER_TESS_CTRL
]
972 ? &builder
->shaders
[MESA_SHADER_TESS_CTRL
]->variants
[0]
974 const struct ir3_shader_variant
*ds
=
975 builder
->shaders
[MESA_SHADER_TESS_EVAL
]
976 ? &builder
->shaders
[MESA_SHADER_TESS_EVAL
]->variants
[0]
978 const struct ir3_shader_variant
*gs
=
979 builder
->shaders
[MESA_SHADER_GEOMETRY
]
980 ? &builder
->shaders
[MESA_SHADER_GEOMETRY
]->variants
[0]
982 const struct ir3_shader_variant
*fs
=
983 builder
->shaders
[MESA_SHADER_FRAGMENT
]
984 ? &builder
->shaders
[MESA_SHADER_FRAGMENT
]->variants
[0]
988 vs
= &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[1];
992 tu6_emit_vs_config(cs
, vs
);
993 tu6_emit_hs_config(cs
, hs
);
994 tu6_emit_ds_config(cs
, ds
);
995 tu6_emit_gs_config(cs
, gs
);
996 tu6_emit_fs_config(cs
, fs
);
998 tu6_emit_vs_system_values(cs
, vs
);
999 tu6_emit_vpc(cs
, vs
, fs
, binning_pass
);
1000 tu6_emit_vpc_varying_modes(cs
, fs
, binning_pass
);
1001 tu6_emit_fs_inputs(cs
, fs
);
1002 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
);
1004 tu6_emit_shader_object(cs
, MESA_SHADER_VERTEX
, vs
, binary_bo
,
1005 builder
->shader_offsets
[MESA_SHADER_VERTEX
]);
1007 tu6_emit_shader_object(cs
, MESA_SHADER_FRAGMENT
, fs
, binary_bo
,
1008 builder
->shader_offsets
[MESA_SHADER_FRAGMENT
]);
1010 tu6_emit_immediates(cs
, vs
, CP_LOAD_STATE6_GEOM
, SB6_VS_SHADER
);
1012 tu6_emit_immediates(cs
, fs
, CP_LOAD_STATE6_FRAG
, SB6_FS_SHADER
);
1016 tu6_emit_vertex_input(struct tu_cs
*cs
,
1017 const struct ir3_shader_variant
*vs
,
1018 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
1019 uint8_t bindings
[MAX_VERTEX_ATTRIBS
],
1020 uint16_t strides
[MAX_VERTEX_ATTRIBS
],
1021 uint16_t offsets
[MAX_VERTEX_ATTRIBS
],
1024 uint32_t vfd_decode_idx
= 0;
1026 for (uint32_t i
= 0; i
< vs
->inputs_count
; i
++) {
1027 if (vs
->inputs
[i
].sysval
|| !vs
->inputs
[i
].compmask
)
1030 const VkVertexInputAttributeDescription
*vi_attr
=
1031 tu_find_vertex_input_attribute(vi_info
, vs
->inputs
[i
].slot
);
1032 const VkVertexInputBindingDescription
*vi_binding
=
1033 tu_find_vertex_input_binding(vi_info
, vi_attr
);
1034 assert(vi_attr
&& vi_binding
);
1036 const struct tu_native_format
*format
=
1037 tu6_get_native_format(vi_attr
->format
);
1038 assert(format
&& format
->vtx
>= 0);
1040 uint32_t vfd_decode
= A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx
) |
1041 A6XX_VFD_DECODE_INSTR_FORMAT(format
->vtx
) |
1042 A6XX_VFD_DECODE_INSTR_SWAP(format
->swap
) |
1043 A6XX_VFD_DECODE_INSTR_UNK30
;
1044 if (vi_binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1045 vfd_decode
|= A6XX_VFD_DECODE_INSTR_INSTANCED
;
1046 if (!vk_format_is_int(vi_attr
->format
))
1047 vfd_decode
|= A6XX_VFD_DECODE_INSTR_FLOAT
;
1049 const uint32_t vfd_decode_step_rate
= 1;
1051 const uint32_t vfd_dest_cntl
=
1052 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs
->inputs
[i
].compmask
) |
1053 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs
->inputs
[i
].regid
);
1055 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DECODE(vfd_decode_idx
), 2);
1056 tu_cs_emit(cs
, vfd_decode
);
1057 tu_cs_emit(cs
, vfd_decode_step_rate
);
1059 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx
), 1);
1060 tu_cs_emit(cs
, vfd_dest_cntl
);
1062 bindings
[vfd_decode_idx
] = vi_binding
->binding
;
1063 strides
[vfd_decode_idx
] = vi_binding
->stride
;
1064 offsets
[vfd_decode_idx
] = vi_attr
->offset
;
1067 assert(vfd_decode_idx
<= MAX_VERTEX_ATTRIBS
);
1070 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_0
, 1);
1072 cs
, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx
) | (vfd_decode_idx
<< 8));
1074 *count
= vfd_decode_idx
;
1078 tu6_guardband_adj(uint32_t v
)
1081 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1087 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1091 scales
[0] = viewport
->width
/ 2.0f
;
1092 scales
[1] = viewport
->height
/ 2.0f
;
1093 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1094 offsets
[0] = viewport
->x
+ scales
[0];
1095 offsets
[1] = viewport
->y
+ scales
[1];
1096 offsets
[2] = viewport
->minDepth
;
1100 min
.x
= (int32_t) viewport
->x
;
1101 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1102 if (viewport
->height
>= 0.0f
) {
1103 min
.y
= (int32_t) viewport
->y
;
1104 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1106 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1107 max
.y
= (int32_t) ceilf(viewport
->y
);
1109 /* the spec allows viewport->height to be 0.0f */
1112 assert(min
.x
>= 0 && min
.x
< max
.x
);
1113 assert(min
.y
>= 0 && min
.y
< max
.y
);
1115 VkExtent2D guardband_adj
;
1116 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1117 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1119 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
1120 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets
[0]));
1121 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XSCALE_0(scales
[0]));
1122 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets
[1]));
1123 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YSCALE_0(scales
[1]));
1124 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets
[2]));
1125 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales
[2]));
1127 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
1128 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min
.x
) |
1129 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min
.y
));
1130 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max
.x
- 1) |
1131 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max
.y
- 1));
1133 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1135 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1136 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1140 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1142 const VkOffset2D min
= scissor
->offset
;
1143 const VkOffset2D max
= {
1144 scissor
->offset
.x
+ scissor
->extent
.width
,
1145 scissor
->offset
.y
+ scissor
->extent
.height
,
1148 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
1149 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min
.x
) |
1150 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min
.y
));
1151 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max
.x
- 1) |
1152 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max
.y
- 1));
1156 tu6_emit_gras_unknowns(struct tu_cs
*cs
)
1158 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8000
, 1);
1159 tu_cs_emit(cs
, 0x80);
1160 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8001
, 1);
1161 tu_cs_emit(cs
, 0x0);
1162 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LAYER_CNTL
, 1);
1163 tu_cs_emit(cs
, 0x0);
1167 tu6_emit_point_size(struct tu_cs
*cs
)
1169 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POINT_MINMAX
, 2);
1170 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f
/ 16.0f
) |
1171 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f
));
1172 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_SIZE(1.0f
));
1176 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1177 VkSampleCountFlagBits samples
)
1179 uint32_t gras_su_cntl
= 0;
1181 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1182 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1183 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1184 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1186 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1187 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1189 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1191 if (rast_info
->depthBiasEnable
)
1192 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1194 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1195 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1197 return gras_su_cntl
;
1201 tu6_emit_gras_su_cntl(struct tu_cs
*cs
,
1202 uint32_t gras_su_cntl
,
1205 assert((gras_su_cntl
& A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
) == 0);
1206 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width
/ 2.0f
);
1208 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_CNTL
, 1);
1209 tu_cs_emit(cs
, gras_su_cntl
);
1213 tu6_emit_depth_bias(struct tu_cs
*cs
,
1214 float constant_factor
,
1218 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1219 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
));
1220 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
));
1221 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
));
1225 tu6_emit_alpha_control_disable(struct tu_cs
*cs
)
1227 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_ALPHA_CONTROL
, 1);
1232 tu6_emit_depth_control(struct tu_cs
*cs
,
1233 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1235 assert(!ds_info
->depthBoundsTestEnable
);
1237 uint32_t rb_depth_cntl
= 0;
1238 if (ds_info
->depthTestEnable
) {
1240 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1241 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1242 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1244 if (ds_info
->depthWriteEnable
)
1245 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1248 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1249 tu_cs_emit(cs
, rb_depth_cntl
);
1253 tu6_emit_stencil_control(struct tu_cs
*cs
,
1254 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1256 uint32_t rb_stencil_control
= 0;
1257 if (ds_info
->stencilTestEnable
) {
1258 const VkStencilOpState
*front
= &ds_info
->front
;
1259 const VkStencilOpState
*back
= &ds_info
->back
;
1260 rb_stencil_control
|=
1261 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1262 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1263 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1264 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1265 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1266 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1267 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1268 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1269 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1270 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1271 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1274 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1275 tu_cs_emit(cs
, rb_stencil_control
);
1279 tu6_emit_stencil_compare_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1281 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILMASK
, 1);
1283 cs
, A6XX_RB_STENCILMASK_MASK(front
) | A6XX_RB_STENCILMASK_BFMASK(back
));
1287 tu6_emit_stencil_write_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1289 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILWRMASK
, 1);
1290 tu_cs_emit(cs
, A6XX_RB_STENCILWRMASK_WRMASK(front
) |
1291 A6XX_RB_STENCILWRMASK_BFWRMASK(back
));
1295 tu6_emit_stencil_reference(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1297 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILREF
, 1);
1299 A6XX_RB_STENCILREF_REF(front
) | A6XX_RB_STENCILREF_BFREF(back
));
1303 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1306 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1307 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1308 has_alpha
? att
->srcColorBlendFactor
1309 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1310 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1311 has_alpha
? att
->dstColorBlendFactor
1312 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1313 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1314 const enum adreno_rb_blend_factor src_alpha_factor
=
1315 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1316 const enum adreno_rb_blend_factor dst_alpha_factor
=
1317 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1319 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1320 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1321 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1322 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1323 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1324 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1328 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1329 uint32_t rb_mrt_control_rop
,
1333 uint32_t rb_mrt_control
=
1334 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1336 /* ignore blending and logic op for integer attachments */
1338 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1339 return rb_mrt_control
;
1342 rb_mrt_control
|= rb_mrt_control_rop
;
1344 if (att
->blendEnable
) {
1345 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1348 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1351 return rb_mrt_control
;
1355 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1356 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1357 const VkFormat attachment_formats
[MAX_RTS
],
1358 uint32_t *blend_enable_mask
)
1360 *blend_enable_mask
= 0;
1362 bool rop_reads_dst
= false;
1363 uint32_t rb_mrt_control_rop
= 0;
1364 if (blend_info
->logicOpEnable
) {
1365 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1366 rb_mrt_control_rop
=
1367 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1368 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1371 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
1372 const VkPipelineColorBlendAttachmentState
*att
=
1373 &blend_info
->pAttachments
[i
];
1374 const VkFormat format
= attachment_formats
[i
];
1376 uint32_t rb_mrt_control
= 0;
1377 uint32_t rb_mrt_blend_control
= 0;
1378 if (format
!= VK_FORMAT_UNDEFINED
) {
1379 const bool is_int
= vk_format_is_int(format
);
1380 const bool has_alpha
= vk_format_has_alpha(format
);
1383 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
1384 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
1386 if (att
->blendEnable
|| rop_reads_dst
)
1387 *blend_enable_mask
|= 1 << i
;
1390 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1391 tu_cs_emit(cs
, rb_mrt_control
);
1392 tu_cs_emit(cs
, rb_mrt_blend_control
);
1395 for (uint32_t i
= blend_info
->attachmentCount
; i
< MAX_RTS
; i
++) {
1396 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1403 tu6_emit_blend_control(struct tu_cs
*cs
,
1404 uint32_t blend_enable_mask
,
1405 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
1407 assert(!msaa_info
->sampleShadingEnable
);
1408 assert(!msaa_info
->alphaToOneEnable
);
1410 uint32_t sp_blend_cntl
= A6XX_SP_BLEND_CNTL_UNK8
;
1411 if (blend_enable_mask
)
1412 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ENABLED
;
1413 if (msaa_info
->alphaToCoverageEnable
)
1414 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1416 const uint32_t sample_mask
=
1417 msaa_info
->pSampleMask
? *msaa_info
->pSampleMask
1418 : ((1 << msaa_info
->rasterizationSamples
) - 1);
1420 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1421 uint32_t rb_blend_cntl
=
1422 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask
) |
1423 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND
|
1424 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask
);
1425 if (msaa_info
->alphaToCoverageEnable
)
1426 rb_blend_cntl
|= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1428 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_BLEND_CNTL
, 1);
1429 tu_cs_emit(cs
, sp_blend_cntl
);
1431 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_CNTL
, 1);
1432 tu_cs_emit(cs
, rb_blend_cntl
);
1436 tu6_emit_blend_constants(struct tu_cs
*cs
, const float constants
[4])
1438 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
1439 tu_cs_emit_array(cs
, (const uint32_t *) constants
, 4);
1443 tu_pipeline_builder_create_pipeline(struct tu_pipeline_builder
*builder
,
1444 struct tu_pipeline
**out_pipeline
)
1446 struct tu_device
*dev
= builder
->device
;
1448 struct tu_pipeline
*pipeline
=
1449 vk_zalloc2(&dev
->alloc
, builder
->alloc
, sizeof(*pipeline
), 8,
1450 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1452 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1454 tu_cs_init(&pipeline
->cs
, TU_CS_MODE_SUB_STREAM
, 2048);
1456 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1457 VkResult result
= tu_cs_reserve_space(dev
, &pipeline
->cs
, 2048);
1458 if (result
!= VK_SUCCESS
) {
1459 vk_free2(&dev
->alloc
, builder
->alloc
, pipeline
);
1463 *out_pipeline
= pipeline
;
1469 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
)
1471 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
1474 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1475 gl_shader_stage stage
=
1476 tu_shader_stage(builder
->create_info
->pStages
[i
].stage
);
1477 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
1480 struct tu_shader_compile_options options
;
1481 tu_shader_compile_options_init(&options
, builder
->create_info
);
1483 /* compile shaders in reverse order */
1484 struct tu_shader
*next_stage_shader
= NULL
;
1485 for (gl_shader_stage stage
= MESA_SHADER_STAGES
- 1;
1486 stage
> MESA_SHADER_NONE
; stage
--) {
1487 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
1491 struct tu_shader
*shader
=
1492 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->alloc
);
1494 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1497 tu_shader_compile(builder
->device
, shader
, next_stage_shader
,
1498 &options
, builder
->alloc
);
1499 if (result
!= VK_SUCCESS
)
1502 builder
->shaders
[stage
] = shader
;
1503 builder
->shader_offsets
[stage
] = builder
->shader_total_size
;
1504 builder
->shader_total_size
+=
1505 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
;
1507 next_stage_shader
= shader
;
1510 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1511 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1512 builder
->binning_vs_offset
= builder
->shader_total_size
;
1513 builder
->shader_total_size
+=
1514 sizeof(uint32_t) * vs
->variants
[1].info
.sizedwords
;
1521 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder
*builder
,
1522 struct tu_pipeline
*pipeline
)
1524 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
1527 tu_bo_init_new(builder
->device
, bo
, builder
->shader_total_size
);
1528 if (result
!= VK_SUCCESS
)
1531 result
= tu_bo_map(builder
->device
, bo
);
1532 if (result
!= VK_SUCCESS
)
1535 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1536 const struct tu_shader
*shader
= builder
->shaders
[i
];
1540 memcpy(bo
->map
+ builder
->shader_offsets
[i
], shader
->binary
,
1541 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
);
1544 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1545 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1546 memcpy(bo
->map
+ builder
->binning_vs_offset
, vs
->binning_binary
,
1547 sizeof(uint32_t) * vs
->variants
[1].info
.sizedwords
);
1554 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
1555 struct tu_pipeline
*pipeline
)
1557 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
1558 builder
->create_info
->pDynamicState
;
1563 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
1564 pipeline
->dynamic_state
.mask
|=
1565 tu_dynamic_state_bit(dynamic_info
->pDynamicStates
[i
]);
1570 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
1571 struct tu_pipeline
*pipeline
)
1573 struct tu_cs prog_cs
;
1574 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 512, &prog_cs
);
1575 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, false);
1576 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1578 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 512, &prog_cs
);
1579 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, true);
1580 pipeline
->program
.binning_state_ib
=
1581 tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1583 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1584 if (!builder
->shaders
[i
])
1587 struct tu_program_descriptor_linkage
*link
= &pipeline
->program
.link
[i
];
1588 struct ir3_shader
*shader
= builder
->shaders
[i
]->variants
[0].shader
;
1590 link
->ubo_state
= shader
->ubo_state
;
1591 link
->const_state
= shader
->const_state
;
1592 link
->constlen
= builder
->shaders
[i
]->variants
[0].constlen
;
1593 link
->texture_map
= builder
->shaders
[i
]->texture_map
;
1594 link
->sampler_map
= builder
->shaders
[i
]->sampler_map
;
1595 link
->ubo_map
= builder
->shaders
[i
]->ubo_map
;
1596 link
->ssbo_map
= builder
->shaders
[i
]->ssbo_map
;
1597 link
->image_mapping
= builder
->shaders
[i
]->variants
[0].image_mapping
;
1602 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
1603 struct tu_pipeline
*pipeline
)
1605 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1606 builder
->create_info
->pVertexInputState
;
1607 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1610 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
,
1611 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
1612 tu6_emit_vertex_input(&vi_cs
, &vs
->variants
[0], vi_info
,
1613 pipeline
->vi
.bindings
, pipeline
->vi
.strides
,
1614 pipeline
->vi
.offsets
, &pipeline
->vi
.count
);
1615 pipeline
->vi
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
1617 if (vs
->has_binning_pass
) {
1618 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
,
1619 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
1620 tu6_emit_vertex_input(
1621 &vi_cs
, &vs
->variants
[1], vi_info
, pipeline
->vi
.binning_bindings
,
1622 pipeline
->vi
.binning_strides
, pipeline
->vi
.binning_offsets
,
1623 &pipeline
->vi
.binning_count
);
1624 pipeline
->vi
.binning_state_ib
=
1625 tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
1630 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
1631 struct tu_pipeline
*pipeline
)
1633 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1634 builder
->create_info
->pInputAssemblyState
;
1636 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
1637 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
1641 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
1642 struct tu_pipeline
*pipeline
)
1646 * pViewportState is a pointer to an instance of the
1647 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1648 * pipeline has rasterization disabled."
1650 * We leave the relevant registers stale in that case.
1652 if (builder
->rasterizer_discard
)
1655 const VkPipelineViewportStateCreateInfo
*vp_info
=
1656 builder
->create_info
->pViewportState
;
1659 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 15, &vp_cs
);
1661 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
1662 assert(vp_info
->viewportCount
== 1);
1663 tu6_emit_viewport(&vp_cs
, vp_info
->pViewports
);
1666 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
1667 assert(vp_info
->scissorCount
== 1);
1668 tu6_emit_scissor(&vp_cs
, vp_info
->pScissors
);
1671 pipeline
->vp
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vp_cs
);
1675 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
1676 struct tu_pipeline
*pipeline
)
1678 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
1679 builder
->create_info
->pRasterizationState
;
1681 assert(!rast_info
->depthClampEnable
);
1682 assert(rast_info
->polygonMode
== VK_POLYGON_MODE_FILL
);
1684 struct tu_cs rast_cs
;
1685 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 20, &rast_cs
);
1687 /* move to hw ctx init? */
1688 tu6_emit_gras_unknowns(&rast_cs
);
1689 tu6_emit_point_size(&rast_cs
);
1691 const uint32_t gras_su_cntl
=
1692 tu6_gras_su_cntl(rast_info
, builder
->samples
);
1694 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
))
1695 tu6_emit_gras_su_cntl(&rast_cs
, gras_su_cntl
, rast_info
->lineWidth
);
1697 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_DEPTH_BIAS
)) {
1698 tu6_emit_depth_bias(&rast_cs
, rast_info
->depthBiasConstantFactor
,
1699 rast_info
->depthBiasClamp
,
1700 rast_info
->depthBiasSlopeFactor
);
1703 pipeline
->rast
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &rast_cs
);
1705 pipeline
->rast
.gras_su_cntl
= gras_su_cntl
;
1709 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
1710 struct tu_pipeline
*pipeline
)
1714 * pDepthStencilState is a pointer to an instance of the
1715 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1716 * the pipeline has rasterization disabled or if the subpass of the
1717 * render pass the pipeline is created against does not use a
1718 * depth/stencil attachment.
1720 * We disable both depth and stenil tests in those cases.
1722 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
1723 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
1724 builder
->use_depth_stencil_attachment
1725 ? builder
->create_info
->pDepthStencilState
1729 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 12, &ds_cs
);
1731 /* move to hw ctx init? */
1732 tu6_emit_alpha_control_disable(&ds_cs
);
1734 tu6_emit_depth_control(&ds_cs
, ds_info
);
1735 tu6_emit_stencil_control(&ds_cs
, ds_info
);
1737 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
1738 tu6_emit_stencil_compare_mask(&ds_cs
, ds_info
->front
.compareMask
,
1739 ds_info
->back
.compareMask
);
1741 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
1742 tu6_emit_stencil_write_mask(&ds_cs
, ds_info
->front
.writeMask
,
1743 ds_info
->back
.writeMask
);
1745 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
1746 tu6_emit_stencil_reference(&ds_cs
, ds_info
->front
.reference
,
1747 ds_info
->back
.reference
);
1750 pipeline
->ds
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &ds_cs
);
1754 tu_pipeline_builder_parse_multisample_and_color_blend(
1755 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
1759 * pMultisampleState is a pointer to an instance of the
1760 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1761 * has rasterization disabled.
1765 * pColorBlendState is a pointer to an instance of the
1766 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1767 * pipeline has rasterization disabled or if the subpass of the render
1768 * pass the pipeline is created against does not use any color
1771 * We leave the relevant registers stale when rasterization is disabled.
1773 if (builder
->rasterizer_discard
)
1776 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
1777 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
1778 builder
->create_info
->pMultisampleState
;
1779 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
1780 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
1781 : &dummy_blend_info
;
1783 struct tu_cs blend_cs
;
1784 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, MAX_RTS
* 3 + 9,
1787 uint32_t blend_enable_mask
;
1788 tu6_emit_rb_mrt_controls(&blend_cs
, blend_info
,
1789 builder
->color_attachment_formats
,
1790 &blend_enable_mask
);
1792 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_BLEND_CONSTANTS
))
1793 tu6_emit_blend_constants(&blend_cs
, blend_info
->blendConstants
);
1795 tu6_emit_blend_control(&blend_cs
, blend_enable_mask
, msaa_info
);
1797 pipeline
->blend
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &blend_cs
);
1801 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
1802 struct tu_device
*dev
,
1803 const VkAllocationCallbacks
*alloc
)
1805 tu_cs_finish(dev
, &pipeline
->cs
);
1807 if (pipeline
->program
.binary_bo
.gem_handle
)
1808 tu_bo_finish(dev
, &pipeline
->program
.binary_bo
);
1812 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
1813 struct tu_pipeline
**pipeline
)
1815 VkResult result
= tu_pipeline_builder_create_pipeline(builder
, pipeline
);
1816 if (result
!= VK_SUCCESS
)
1819 /* compile and upload shaders */
1820 result
= tu_pipeline_builder_compile_shaders(builder
);
1821 if (result
== VK_SUCCESS
)
1822 result
= tu_pipeline_builder_upload_shaders(builder
, *pipeline
);
1823 if (result
!= VK_SUCCESS
) {
1824 tu_pipeline_finish(*pipeline
, builder
->device
, builder
->alloc
);
1825 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
1826 *pipeline
= VK_NULL_HANDLE
;
1831 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
1832 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
1833 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
1834 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
1835 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
1836 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
1837 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
1838 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
1840 /* we should have reserved enough space upfront such that the CS never
1843 assert((*pipeline
)->cs
.bo_count
== 1);
1849 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
1851 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1852 if (!builder
->shaders
[i
])
1854 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
1859 tu_pipeline_builder_init_graphics(
1860 struct tu_pipeline_builder
*builder
,
1861 struct tu_device
*dev
,
1862 struct tu_pipeline_cache
*cache
,
1863 const VkGraphicsPipelineCreateInfo
*create_info
,
1864 const VkAllocationCallbacks
*alloc
)
1866 *builder
= (struct tu_pipeline_builder
) {
1869 .create_info
= create_info
,
1873 builder
->rasterizer_discard
=
1874 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
1876 if (builder
->rasterizer_discard
) {
1877 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
1879 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
1881 const struct tu_render_pass
*pass
=
1882 tu_render_pass_from_handle(create_info
->renderPass
);
1883 const struct tu_subpass
*subpass
=
1884 &pass
->subpasses
[create_info
->subpass
];
1886 builder
->use_depth_stencil_attachment
=
1887 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
;
1889 assert(subpass
->color_count
== 0 ||
1890 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
1891 builder
->color_attachment_count
= subpass
->color_count
;
1892 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
1893 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
1894 if (a
== VK_ATTACHMENT_UNUSED
)
1897 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
1898 builder
->use_color_attachments
= true;
1904 tu_CreateGraphicsPipelines(VkDevice device
,
1905 VkPipelineCache pipelineCache
,
1907 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
1908 const VkAllocationCallbacks
*pAllocator
,
1909 VkPipeline
*pPipelines
)
1911 TU_FROM_HANDLE(tu_device
, dev
, device
);
1912 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
1913 VkResult final_result
= VK_SUCCESS
;
1915 for (uint32_t i
= 0; i
< count
; i
++) {
1916 struct tu_pipeline_builder builder
;
1917 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
1918 &pCreateInfos
[i
], pAllocator
);
1920 struct tu_pipeline
*pipeline
= NULL
;
1921 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
1922 tu_pipeline_builder_finish(&builder
);
1924 if (result
== VK_SUCCESS
) {
1925 pPipelines
[i
] = tu_pipeline_to_handle(pipeline
);
1927 pPipelines
[i
] = NULL
;
1928 final_result
= result
;
1932 return final_result
;
1936 tu_compute_pipeline_create(VkDevice _device
,
1937 VkPipelineCache _cache
,
1938 const VkComputePipelineCreateInfo
*pCreateInfo
,
1939 const VkAllocationCallbacks
*pAllocator
,
1940 VkPipeline
*pPipeline
)
1946 tu_CreateComputePipelines(VkDevice _device
,
1947 VkPipelineCache pipelineCache
,
1949 const VkComputePipelineCreateInfo
*pCreateInfos
,
1950 const VkAllocationCallbacks
*pAllocator
,
1951 VkPipeline
*pPipelines
)
1953 VkResult result
= VK_SUCCESS
;
1956 for (; i
< count
; i
++) {
1958 r
= tu_compute_pipeline_create(_device
, pipelineCache
, &pCreateInfos
[i
],
1959 pAllocator
, &pPipelines
[i
]);
1960 if (r
!= VK_SUCCESS
) {
1963 pPipelines
[i
] = VK_NULL_HANDLE
;
1970 tu_DestroyPipeline(VkDevice _device
,
1971 VkPipeline _pipeline
,
1972 const VkAllocationCallbacks
*pAllocator
)
1974 TU_FROM_HANDLE(tu_device
, dev
, _device
);
1975 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
1980 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
1981 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);