2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "main/menums.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
42 struct tu_pipeline_builder
44 struct tu_device
*device
;
45 struct tu_pipeline_cache
*cache
;
46 struct tu_pipeline_layout
*layout
;
47 const VkAllocationCallbacks
*alloc
;
48 const VkGraphicsPipelineCreateInfo
*create_info
;
50 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
51 uint32_t shader_offsets
[MESA_SHADER_STAGES
];
52 uint32_t binning_vs_offset
;
53 uint32_t shader_total_size
;
55 bool rasterizer_discard
;
56 /* these states are affectd by rasterizer_discard */
57 VkSampleCountFlagBits samples
;
58 bool use_depth_stencil_attachment
;
59 bool use_color_attachments
;
60 uint32_t color_attachment_count
;
61 VkFormat color_attachment_formats
[MAX_RTS
];
64 static enum tu_dynamic_state_bits
65 tu_dynamic_state_bit(VkDynamicState state
)
68 case VK_DYNAMIC_STATE_VIEWPORT
:
69 return TU_DYNAMIC_VIEWPORT
;
70 case VK_DYNAMIC_STATE_SCISSOR
:
71 return TU_DYNAMIC_SCISSOR
;
72 case VK_DYNAMIC_STATE_LINE_WIDTH
:
73 return TU_DYNAMIC_LINE_WIDTH
;
74 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
75 return TU_DYNAMIC_DEPTH_BIAS
;
76 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
77 return TU_DYNAMIC_BLEND_CONSTANTS
;
78 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
79 return TU_DYNAMIC_DEPTH_BOUNDS
;
80 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
81 return TU_DYNAMIC_STENCIL_COMPARE_MASK
;
82 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
83 return TU_DYNAMIC_STENCIL_WRITE_MASK
;
84 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
85 return TU_DYNAMIC_STENCIL_REFERENCE
;
87 unreachable("invalid dynamic state");
92 static gl_shader_stage
93 tu_shader_stage(VkShaderStageFlagBits stage
)
96 case VK_SHADER_STAGE_VERTEX_BIT
:
97 return MESA_SHADER_VERTEX
;
98 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
99 return MESA_SHADER_TESS_CTRL
;
100 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
101 return MESA_SHADER_TESS_EVAL
;
102 case VK_SHADER_STAGE_GEOMETRY_BIT
:
103 return MESA_SHADER_GEOMETRY
;
104 case VK_SHADER_STAGE_FRAGMENT_BIT
:
105 return MESA_SHADER_FRAGMENT
;
106 case VK_SHADER_STAGE_COMPUTE_BIT
:
107 return MESA_SHADER_COMPUTE
;
109 unreachable("invalid VkShaderStageFlagBits");
110 return MESA_SHADER_NONE
;
114 static const VkVertexInputAttributeDescription
*
115 tu_find_vertex_input_attribute(
116 const VkPipelineVertexInputStateCreateInfo
*vi_info
, uint32_t slot
)
118 assert(slot
>= VERT_ATTRIB_GENERIC0
);
119 slot
-= VERT_ATTRIB_GENERIC0
;
120 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
121 if (vi_info
->pVertexAttributeDescriptions
[i
].location
== slot
)
122 return &vi_info
->pVertexAttributeDescriptions
[i
];
127 static const VkVertexInputBindingDescription
*
128 tu_find_vertex_input_binding(
129 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
130 const VkVertexInputAttributeDescription
*vi_attr
)
133 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
134 if (vi_info
->pVertexBindingDescriptions
[i
].binding
== vi_attr
->binding
)
135 return &vi_info
->pVertexBindingDescriptions
[i
];
141 tu_logic_op_reads_dst(VkLogicOp op
)
144 case VK_LOGIC_OP_CLEAR
:
145 case VK_LOGIC_OP_COPY
:
146 case VK_LOGIC_OP_COPY_INVERTED
:
147 case VK_LOGIC_OP_SET
:
155 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
157 /* treat dst alpha as 1.0 and avoid reading it */
159 case VK_BLEND_FACTOR_DST_ALPHA
:
160 return VK_BLEND_FACTOR_ONE
;
161 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
162 return VK_BLEND_FACTOR_ZERO
;
168 static enum pc_di_primtype
169 tu6_primtype(VkPrimitiveTopology topology
)
172 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
173 return DI_PT_POINTLIST
;
174 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
175 return DI_PT_LINELIST
;
176 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
177 return DI_PT_LINESTRIP
;
178 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
179 return DI_PT_TRILIST
;
180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
181 return DI_PT_TRISTRIP
;
182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
185 return DI_PT_LINE_ADJ
;
186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
187 return DI_PT_LINESTRIP_ADJ
;
188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
189 return DI_PT_TRI_ADJ
;
190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
191 return DI_PT_TRISTRIP_ADJ
;
192 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
194 unreachable("invalid primitive topology");
199 static enum adreno_compare_func
200 tu6_compare_func(VkCompareOp op
)
203 case VK_COMPARE_OP_NEVER
:
205 case VK_COMPARE_OP_LESS
:
207 case VK_COMPARE_OP_EQUAL
:
209 case VK_COMPARE_OP_LESS_OR_EQUAL
:
211 case VK_COMPARE_OP_GREATER
:
213 case VK_COMPARE_OP_NOT_EQUAL
:
214 return FUNC_NOTEQUAL
;
215 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
217 case VK_COMPARE_OP_ALWAYS
:
220 unreachable("invalid VkCompareOp");
225 static enum adreno_stencil_op
226 tu6_stencil_op(VkStencilOp op
)
229 case VK_STENCIL_OP_KEEP
:
231 case VK_STENCIL_OP_ZERO
:
233 case VK_STENCIL_OP_REPLACE
:
234 return STENCIL_REPLACE
;
235 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
236 return STENCIL_INCR_CLAMP
;
237 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
238 return STENCIL_DECR_CLAMP
;
239 case VK_STENCIL_OP_INVERT
:
240 return STENCIL_INVERT
;
241 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
242 return STENCIL_INCR_WRAP
;
243 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
244 return STENCIL_DECR_WRAP
;
246 unreachable("invalid VkStencilOp");
251 static enum a3xx_rop_code
252 tu6_rop(VkLogicOp op
)
255 case VK_LOGIC_OP_CLEAR
:
257 case VK_LOGIC_OP_AND
:
259 case VK_LOGIC_OP_AND_REVERSE
:
260 return ROP_AND_REVERSE
;
261 case VK_LOGIC_OP_COPY
:
263 case VK_LOGIC_OP_AND_INVERTED
:
264 return ROP_AND_INVERTED
;
265 case VK_LOGIC_OP_NO_OP
:
267 case VK_LOGIC_OP_XOR
:
271 case VK_LOGIC_OP_NOR
:
273 case VK_LOGIC_OP_EQUIVALENT
:
275 case VK_LOGIC_OP_INVERT
:
277 case VK_LOGIC_OP_OR_REVERSE
:
278 return ROP_OR_REVERSE
;
279 case VK_LOGIC_OP_COPY_INVERTED
:
280 return ROP_COPY_INVERTED
;
281 case VK_LOGIC_OP_OR_INVERTED
:
282 return ROP_OR_INVERTED
;
283 case VK_LOGIC_OP_NAND
:
285 case VK_LOGIC_OP_SET
:
288 unreachable("invalid VkLogicOp");
293 static enum adreno_rb_blend_factor
294 tu6_blend_factor(VkBlendFactor factor
)
297 case VK_BLEND_FACTOR_ZERO
:
299 case VK_BLEND_FACTOR_ONE
:
301 case VK_BLEND_FACTOR_SRC_COLOR
:
302 return FACTOR_SRC_COLOR
;
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
304 return FACTOR_ONE_MINUS_SRC_COLOR
;
305 case VK_BLEND_FACTOR_DST_COLOR
:
306 return FACTOR_DST_COLOR
;
307 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
308 return FACTOR_ONE_MINUS_DST_COLOR
;
309 case VK_BLEND_FACTOR_SRC_ALPHA
:
310 return FACTOR_SRC_ALPHA
;
311 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
312 return FACTOR_ONE_MINUS_SRC_ALPHA
;
313 case VK_BLEND_FACTOR_DST_ALPHA
:
314 return FACTOR_DST_ALPHA
;
315 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
316 return FACTOR_ONE_MINUS_DST_ALPHA
;
317 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
318 return FACTOR_CONSTANT_COLOR
;
319 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
320 return FACTOR_ONE_MINUS_CONSTANT_COLOR
;
321 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
322 return FACTOR_CONSTANT_ALPHA
;
323 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
324 return FACTOR_ONE_MINUS_CONSTANT_ALPHA
;
325 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
326 return FACTOR_SRC_ALPHA_SATURATE
;
327 case VK_BLEND_FACTOR_SRC1_COLOR
:
328 return FACTOR_SRC1_COLOR
;
329 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
330 return FACTOR_ONE_MINUS_SRC1_COLOR
;
331 case VK_BLEND_FACTOR_SRC1_ALPHA
:
332 return FACTOR_SRC1_ALPHA
;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
334 return FACTOR_ONE_MINUS_SRC1_ALPHA
;
336 unreachable("invalid VkBlendFactor");
341 static enum a3xx_rb_blend_opcode
342 tu6_blend_op(VkBlendOp op
)
345 case VK_BLEND_OP_ADD
:
346 return BLEND_DST_PLUS_SRC
;
347 case VK_BLEND_OP_SUBTRACT
:
348 return BLEND_SRC_MINUS_DST
;
349 case VK_BLEND_OP_REVERSE_SUBTRACT
:
350 return BLEND_DST_MINUS_SRC
;
351 case VK_BLEND_OP_MIN
:
352 return BLEND_MIN_DST_SRC
;
353 case VK_BLEND_OP_MAX
:
354 return BLEND_MAX_DST_SRC
;
356 unreachable("invalid VkBlendOp");
357 return BLEND_DST_PLUS_SRC
;
362 tu_shader_nibo(const struct tu_shader
*shader
)
364 /* Don't use ir3_shader_nibo(), because that would include declared but
365 * unused storage images and SSBOs.
367 return shader
->ssbo_map
.num_desc
+ shader
->image_map
.num_desc
;
371 tu6_emit_vs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
372 const struct ir3_shader_variant
*vs
)
374 uint32_t sp_vs_ctrl
=
375 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
376 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
377 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
378 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
);
380 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
;
381 if (vs
->need_fine_derivatives
)
382 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_DIFF_FINE
;
384 uint32_t sp_vs_config
= A6XX_SP_VS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
385 A6XX_SP_VS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
);
387 sp_vs_config
|= A6XX_SP_VS_CONFIG_ENABLED
;
389 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
390 tu_cs_emit(cs
, sp_vs_ctrl
);
392 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CONFIG
, 2);
393 tu_cs_emit(cs
, sp_vs_config
);
394 tu_cs_emit(cs
, vs
->instrlen
);
396 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_VS_CNTL
, 1);
397 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs
->constlen
, 4)) |
398 A6XX_HLSQ_VS_CNTL_ENABLED
);
402 tu6_emit_hs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
403 const struct ir3_shader_variant
*hs
)
405 uint32_t sp_hs_config
= 0;
407 sp_hs_config
|= A6XX_SP_HS_CONFIG_ENABLED
;
409 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
412 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_CONFIG
, 2);
413 tu_cs_emit(cs
, sp_hs_config
);
414 tu_cs_emit(cs
, hs
->instrlen
);
416 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_HS_CNTL
, 1);
417 tu_cs_emit(cs
, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs
->constlen
, 4)));
421 tu6_emit_ds_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
422 const struct ir3_shader_variant
*ds
)
424 uint32_t sp_ds_config
= 0;
426 sp_ds_config
|= A6XX_SP_DS_CONFIG_ENABLED
;
428 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_CONFIG
, 2);
429 tu_cs_emit(cs
, sp_ds_config
);
430 tu_cs_emit(cs
, ds
->instrlen
);
432 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_DS_CNTL
, 1);
433 tu_cs_emit(cs
, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds
->constlen
, 4)));
437 tu6_emit_gs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
438 const struct ir3_shader_variant
*gs
)
440 uint32_t sp_gs_config
= 0;
442 sp_gs_config
|= A6XX_SP_GS_CONFIG_ENABLED
;
444 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
447 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CONFIG
, 2);
448 tu_cs_emit(cs
, sp_gs_config
);
449 tu_cs_emit(cs
, gs
->instrlen
);
451 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_GS_CNTL
, 1);
452 tu_cs_emit(cs
, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs
->constlen
, 4)));
456 tu6_emit_fs_config(struct tu_cs
*cs
, struct tu_shader
*shader
,
457 const struct ir3_shader_variant
*fs
)
459 uint32_t sp_fs_ctrl
=
460 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) | 0x1000000 |
461 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
462 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
463 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
);
464 if (fs
->total_in
> 0)
465 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_VARYING
;
467 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
;
468 if (fs
->need_fine_derivatives
)
469 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_DIFF_FINE
;
471 uint32_t sp_fs_config
= 0;
472 unsigned shader_nibo
= 0;
474 shader_nibo
= tu_shader_nibo(shader
);
475 sp_fs_config
= A6XX_SP_FS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
476 A6XX_SP_FS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
) |
477 A6XX_SP_FS_CONFIG_NIBO(shader_nibo
);
481 sp_fs_config
|= A6XX_SP_FS_CONFIG_ENABLED
;
483 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
484 tu_cs_emit(cs
, sp_fs_ctrl
);
486 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CONFIG
, 2);
487 tu_cs_emit(cs
, sp_fs_config
);
488 tu_cs_emit(cs
, fs
->instrlen
);
490 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_FS_CNTL
, 1);
491 tu_cs_emit(cs
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs
->constlen
, 4)) |
492 A6XX_HLSQ_FS_CNTL_ENABLED
);
494 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_IBO_COUNT
, 1);
495 tu_cs_emit(cs
, shader_nibo
);
499 tu6_emit_cs_config(struct tu_cs
*cs
, const struct tu_shader
*shader
,
500 const struct ir3_shader_variant
*v
)
502 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
503 tu_cs_emit(cs
, 0xff);
505 unsigned constlen
= align(v
->constlen
, 4);
506 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL
, 1);
507 tu_cs_emit(cs
, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen
) |
508 A6XX_HLSQ_CS_CNTL_ENABLED
);
510 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CONFIG
, 2);
511 tu_cs_emit(cs
, A6XX_SP_CS_CONFIG_ENABLED
|
512 A6XX_SP_CS_CONFIG_NIBO(tu_shader_nibo(shader
)) |
513 A6XX_SP_CS_CONFIG_NTEX(shader
->texture_map
.num_desc
) |
514 A6XX_SP_CS_CONFIG_NSAMP(shader
->sampler_map
.num_desc
));
515 tu_cs_emit(cs
, v
->instrlen
);
517 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_CTRL_REG0
, 1);
518 tu_cs_emit(cs
, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
519 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v
->info
.max_reg
+ 1) |
520 A6XX_SP_CS_CTRL_REG0_MERGEDREGS
|
521 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v
->branchstack
) |
522 COND(v
->need_pixlod
, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE
) |
523 COND(v
->need_fine_derivatives
, A6XX_SP_CS_CTRL_REG0_DIFF_FINE
));
525 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
526 tu_cs_emit(cs
, 0x41);
528 uint32_t local_invocation_id
=
529 ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
530 uint32_t work_group_id
=
531 ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
533 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
535 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
536 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
537 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
538 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
539 tu_cs_emit(cs
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
541 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_IBO_COUNT
, 1);
542 tu_cs_emit(cs
, tu_shader_nibo(shader
));
546 tu6_emit_vs_system_values(struct tu_cs
*cs
,
547 const struct ir3_shader_variant
*vs
)
549 const uint32_t vertexid_regid
=
550 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
551 const uint32_t instanceid_regid
=
552 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
554 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
555 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
556 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
558 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_2 */
559 tu_cs_emit(cs
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
560 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
561 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_5 */
562 tu_cs_emit(cs
, 0x00000000); /* VFD_CONTROL_6 */
565 /* Add any missing varyings needed for stream-out. Otherwise varyings not
566 * used by fragment shader will be stripped out.
569 tu6_link_streamout(struct ir3_shader_linkage
*l
,
570 const struct ir3_shader_variant
*v
)
572 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
575 * First, any stream-out varyings not already in linkage map (ie. also
576 * consumed by frag shader) need to be added:
578 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
579 const struct ir3_stream_output
*out
= &info
->output
[i
];
581 (1 << (out
->num_components
+ out
->start_component
)) - 1;
582 unsigned k
= out
->register_index
;
583 unsigned idx
, nextloc
= 0;
585 /* psize/pos need to be the last entries in linkage map, and will
586 * get added link_stream_out, so skip over them:
588 if (v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
||
589 v
->outputs
[k
].slot
== VARYING_SLOT_POS
)
592 for (idx
= 0; idx
< l
->cnt
; idx
++) {
593 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
595 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
598 /* add if not already in linkage map: */
600 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
602 /* expand component-mask if needed, ie streaming out all components
603 * but frag shader doesn't consume all components:
605 if (compmask
& ~l
->var
[idx
].compmask
) {
606 l
->var
[idx
].compmask
|= compmask
;
607 l
->max_loc
= MAX2(l
->max_loc
, l
->var
[idx
].loc
+
608 util_last_bit(l
->var
[idx
].compmask
));
614 tu6_setup_streamout(const struct ir3_shader_variant
*v
,
615 struct ir3_shader_linkage
*l
, struct tu_streamout_state
*tf
)
617 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
619 memset(tf
, 0, sizeof(*tf
));
621 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
623 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
625 /* set stride info to the streamout state */
626 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
627 tf
->stride
[i
] = info
->stride
[i
];
629 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
630 const struct ir3_stream_output
*out
= &info
->output
[i
];
631 unsigned k
= out
->register_index
;
634 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
636 /* linkage map sorted by order frag shader wants things, so
637 * a bit less ideal here..
639 for (idx
= 0; idx
< l
->cnt
; idx
++)
640 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
643 debug_assert(idx
< l
->cnt
);
645 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
646 unsigned c
= j
+ out
->start_component
;
647 unsigned loc
= l
->var
[idx
].loc
+ c
;
648 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
651 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
652 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
653 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
655 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
656 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
657 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
662 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
663 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
664 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
665 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
666 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
670 tu6_emit_vpc(struct tu_cs
*cs
,
671 const struct ir3_shader_variant
*vs
,
672 const struct ir3_shader_variant
*fs
,
674 struct tu_streamout_state
*tf
)
676 struct ir3_shader_linkage linkage
= { 0 };
677 ir3_link_shaders(&linkage
, vs
, fs
);
679 if (vs
->shader
->stream_output
.num_outputs
)
680 tu6_link_streamout(&linkage
, vs
);
682 BITSET_DECLARE(vpc_var_enables
, 128) = { 0 };
683 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
684 const uint32_t comp_count
= util_last_bit(linkage
.var
[i
].compmask
);
685 for (uint32_t j
= 0; j
< comp_count
; j
++)
686 BITSET_SET(vpc_var_enables
, linkage
.var
[i
].loc
+ j
);
689 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
690 tu_cs_emit(cs
, ~vpc_var_enables
[0]);
691 tu_cs_emit(cs
, ~vpc_var_enables
[1]);
692 tu_cs_emit(cs
, ~vpc_var_enables
[2]);
693 tu_cs_emit(cs
, ~vpc_var_enables
[3]);
695 /* a6xx finds position/pointsize at the end */
696 const uint32_t position_regid
=
697 ir3_find_output_regid(vs
, VARYING_SLOT_POS
);
698 const uint32_t pointsize_regid
=
699 ir3_find_output_regid(vs
, VARYING_SLOT_PSIZ
);
700 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff;
701 if (position_regid
!= regid(63, 0)) {
702 position_loc
= linkage
.max_loc
;
703 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
705 if (pointsize_regid
!= regid(63, 0)) {
706 pointsize_loc
= linkage
.max_loc
;
707 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
710 if (vs
->shader
->stream_output
.num_outputs
)
711 tu6_setup_streamout(vs
, &linkage
, tf
);
713 /* map vs outputs to VPC */
714 assert(linkage
.cnt
<= 32);
715 const uint32_t sp_vs_out_count
= (linkage
.cnt
+ 1) / 2;
716 const uint32_t sp_vs_vpc_dst_count
= (linkage
.cnt
+ 3) / 4;
717 uint32_t sp_vs_out
[16];
718 uint32_t sp_vs_vpc_dst
[8];
719 sp_vs_out
[sp_vs_out_count
- 1] = 0;
720 sp_vs_vpc_dst
[sp_vs_vpc_dst_count
- 1] = 0;
721 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
722 ((uint16_t *) sp_vs_out
)[i
] =
723 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
724 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
725 ((uint8_t *) sp_vs_vpc_dst
)[i
] =
726 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
729 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count
);
730 tu_cs_emit_array(cs
, sp_vs_out
, sp_vs_out_count
);
732 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count
);
733 tu_cs_emit_array(cs
, sp_vs_vpc_dst
, sp_vs_vpc_dst_count
);
735 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
736 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
737 (fs
->total_in
> 0 ? A6XX_VPC_CNTL_0_VARYING
: 0) |
740 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
741 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
742 A6XX_VPC_PACK_PSIZELOC(pointsize_loc
) |
743 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
745 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
746 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage
.cnt
));
748 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
749 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage
.max_loc
) |
750 (vs
->writes_psize
? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
: 0));
754 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
756 uint8_t *interp_mode
,
757 uint8_t *ps_repl_mode
)
771 PS_REPL_ONE_MINUS_T
= 3,
774 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
776 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
777 * fourth component occupy three consecutive varying slots
782 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
783 if (compmask
& 0x1) {
784 *ps_repl_mode
|= PS_REPL_S
<< shift
;
787 if (compmask
& 0x2) {
788 *ps_repl_mode
|= PS_REPL_T
<< shift
;
791 if (compmask
& 0x4) {
792 *interp_mode
|= INTERP_ZERO
<< shift
;
795 if (compmask
& 0x8) {
796 *interp_mode
|= INTERP_ONE
<< 6;
799 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
800 fs
->inputs
[index
].rasterflat
) {
801 for (int i
= 0; i
< 4; i
++) {
802 if (compmask
& (1 << i
)) {
803 *interp_mode
|= INTERP_FLAT
<< shift
;
813 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
814 const struct ir3_shader_variant
*fs
,
817 uint32_t interp_modes
[8] = { 0 };
818 uint32_t ps_repl_modes
[8] = { 0 };
822 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
824 /* get the mode for input i */
826 uint8_t ps_repl_mode
;
828 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
830 /* OR the mode into the array */
831 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
832 uint32_t n
= inloc
/ 32;
833 uint32_t shift
= inloc
% 32;
834 interp_modes
[n
] |= interp_mode
<< shift
;
835 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
836 if (shift
+ bits
> 32) {
840 interp_modes
[n
] |= interp_mode
>> shift
;
841 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
846 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
847 tu_cs_emit_array(cs
, interp_modes
, 8);
849 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
850 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
854 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
856 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
857 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
858 uint32_t smask_in_regid
;
860 bool sample_shading
= fs
->per_samp
; /* TODO | key->sample_shading; */
861 bool enable_varyings
= fs
->total_in
> 0;
863 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
864 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
865 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
866 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
867 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
868 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
869 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
870 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
871 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
873 if (fs
->num_sampler_prefetch
> 0) {
874 assert(VALIDREG(ij_pix_regid
));
875 /* also, it seems like ij_pix is *required* to be r0.x */
876 assert(ij_pix_regid
== regid(0, 0));
879 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
880 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
881 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
883 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
884 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
885 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
886 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
887 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
888 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
889 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
890 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
891 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
894 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
896 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
897 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
898 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
899 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
900 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
901 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
903 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
904 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
905 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
907 tu_cs_emit(cs
, 0xfc);
909 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
910 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
912 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
913 tu_cs_emit(cs
, 0xff); /* XXX */
915 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
917 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
918 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
919 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
920 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
921 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
923 A6XX_GRAS_CNTL_SIZE
|
924 A6XX_GRAS_CNTL_XCOORD
|
925 A6XX_GRAS_CNTL_YCOORD
|
926 A6XX_GRAS_CNTL_ZCOORD
|
927 A6XX_GRAS_CNTL_WCOORD
) |
928 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
930 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
932 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
933 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
934 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
935 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
936 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
937 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
939 A6XX_RB_RENDER_CONTROL0_SIZE
|
940 A6XX_RB_RENDER_CONTROL0_XCOORD
|
941 A6XX_RB_RENDER_CONTROL0_YCOORD
|
942 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
943 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
944 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
946 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
947 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
948 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
949 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
951 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
952 tu_cs_emit(cs
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
954 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
955 tu_cs_emit(cs
, COND(sample_shading
, 0x6)); // XXX
957 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
958 tu_cs_emit(cs
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
962 tu6_emit_fs_outputs(struct tu_cs
*cs
,
963 const struct ir3_shader_variant
*fs
,
966 uint32_t smask_regid
, posz_regid
;
968 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
969 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
971 uint32_t fragdata_regid
[8];
972 if (fs
->color0_mrt
) {
973 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
974 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
975 fragdata_regid
[i
] = fragdata_regid
[0];
977 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
978 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
981 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
982 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
983 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
985 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
987 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
988 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
989 // TODO we could have a mix of half and full precision outputs,
990 // we really need to figure out half-precision from IR3_REG_HALF
991 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
992 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
995 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
996 tu_cs_emit(cs
, COND(fs
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
) |
997 COND(fs
->writes_smask
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK
));
998 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1000 uint32_t gras_su_depth_plane_cntl
= 0;
1001 uint32_t rb_depth_plane_cntl
= 0;
1002 if (fs
->no_earlyz
|| fs
->writes_pos
) {
1003 gras_su_depth_plane_cntl
|= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
1004 rb_depth_plane_cntl
|= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
1007 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
1008 tu_cs_emit(cs
, gras_su_depth_plane_cntl
);
1010 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
1011 tu_cs_emit(cs
, rb_depth_plane_cntl
);
1015 tu6_emit_shader_object(struct tu_cs
*cs
,
1016 gl_shader_stage stage
,
1017 const struct ir3_shader_variant
*variant
,
1018 const struct tu_bo
*binary_bo
,
1019 uint32_t binary_offset
)
1023 enum a6xx_state_block sb
;
1025 case MESA_SHADER_VERTEX
:
1026 reg
= REG_A6XX_SP_VS_OBJ_START_LO
;
1027 opcode
= CP_LOAD_STATE6_GEOM
;
1030 case MESA_SHADER_TESS_CTRL
:
1031 reg
= REG_A6XX_SP_HS_OBJ_START_LO
;
1032 opcode
= CP_LOAD_STATE6_GEOM
;
1035 case MESA_SHADER_TESS_EVAL
:
1036 reg
= REG_A6XX_SP_DS_OBJ_START_LO
;
1037 opcode
= CP_LOAD_STATE6_GEOM
;
1040 case MESA_SHADER_GEOMETRY
:
1041 reg
= REG_A6XX_SP_GS_OBJ_START_LO
;
1042 opcode
= CP_LOAD_STATE6_GEOM
;
1045 case MESA_SHADER_FRAGMENT
:
1046 reg
= REG_A6XX_SP_FS_OBJ_START_LO
;
1047 opcode
= CP_LOAD_STATE6_FRAG
;
1050 case MESA_SHADER_COMPUTE
:
1051 reg
= REG_A6XX_SP_CS_OBJ_START_LO
;
1052 opcode
= CP_LOAD_STATE6_FRAG
;
1056 unreachable("invalid gl_shader_stage");
1057 opcode
= CP_LOAD_STATE6_GEOM
;
1062 if (!variant
->instrlen
) {
1063 tu_cs_emit_pkt4(cs
, reg
, 2);
1064 tu_cs_emit_qw(cs
, 0);
1068 assert(variant
->type
== stage
);
1070 const uint64_t binary_iova
= binary_bo
->iova
+ binary_offset
;
1071 assert((binary_iova
& 0xf) == 0);
1072 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1073 * of the shader. this could be a potential source of problems at some point
1074 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1077 tu_cs_emit_pkt4(cs
, reg
, 2);
1078 tu_cs_emit_qw(cs
, binary_iova
);
1080 /* always indirect */
1081 const bool indirect
= true;
1083 tu_cs_emit_pkt7(cs
, opcode
, 3);
1084 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1085 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
1086 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1087 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
1088 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
1089 tu_cs_emit_qw(cs
, binary_iova
);
1091 const void *binary
= binary_bo
->map
+ binary_offset
;
1093 tu_cs_emit_pkt7(cs
, opcode
, 3 + variant
->info
.sizedwords
);
1094 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1095 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
1096 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
1097 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
1098 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
1099 tu_cs_emit_qw(cs
, 0);
1100 tu_cs_emit_array(cs
, binary
, variant
->info
.sizedwords
);
1105 tu6_emit_immediates(struct tu_cs
*cs
, const struct ir3_shader_variant
*v
,
1106 uint32_t opcode
, enum a6xx_state_block block
)
1112 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
1113 uint32_t base
= const_state
->offsets
.immediate
;
1114 int size
= const_state
->immediates_count
;
1116 /* truncate size to avoid writing constants that shader
1119 size
= MIN2(size
+ base
, v
->constlen
) - base
;
1124 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
* 4);
1125 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
1126 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1127 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
1128 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
1129 CP_LOAD_STATE6_0_NUM_UNIT(size
));
1130 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1131 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1133 for (unsigned i
= 0; i
< size
; i
++) {
1134 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
1135 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
1136 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
1137 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
1142 tu6_emit_program(struct tu_cs
*cs
,
1143 const struct tu_pipeline_builder
*builder
,
1144 const struct tu_bo
*binary_bo
,
1146 struct tu_streamout_state
*tf
)
1148 static const struct ir3_shader_variant dummy_variant
= {
1149 .type
= MESA_SHADER_NONE
1151 assert(builder
->shaders
[MESA_SHADER_VERTEX
]);
1152 const struct ir3_shader_variant
*vs
=
1153 &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[0];
1154 const struct ir3_shader_variant
*hs
=
1155 builder
->shaders
[MESA_SHADER_TESS_CTRL
]
1156 ? &builder
->shaders
[MESA_SHADER_TESS_CTRL
]->variants
[0]
1158 const struct ir3_shader_variant
*ds
=
1159 builder
->shaders
[MESA_SHADER_TESS_EVAL
]
1160 ? &builder
->shaders
[MESA_SHADER_TESS_EVAL
]->variants
[0]
1162 const struct ir3_shader_variant
*gs
=
1163 builder
->shaders
[MESA_SHADER_GEOMETRY
]
1164 ? &builder
->shaders
[MESA_SHADER_GEOMETRY
]->variants
[0]
1166 const struct ir3_shader_variant
*fs
=
1167 builder
->shaders
[MESA_SHADER_FRAGMENT
]
1168 ? &builder
->shaders
[MESA_SHADER_FRAGMENT
]->variants
[0]
1172 /* if we have streamout, use full VS in binning pass, as the
1173 * binning pass VS will have outputs on other than position/psize
1176 if (vs
->shader
->stream_output
.num_outputs
== 0)
1177 vs
= &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[1];
1178 fs
= &dummy_variant
;
1181 tu6_emit_vs_config(cs
, builder
->shaders
[MESA_SHADER_VERTEX
], vs
);
1182 tu6_emit_hs_config(cs
, builder
->shaders
[MESA_SHADER_TESS_CTRL
], hs
);
1183 tu6_emit_ds_config(cs
, builder
->shaders
[MESA_SHADER_TESS_EVAL
], ds
);
1184 tu6_emit_gs_config(cs
, builder
->shaders
[MESA_SHADER_GEOMETRY
], gs
);
1185 tu6_emit_fs_config(cs
, builder
->shaders
[MESA_SHADER_FRAGMENT
], fs
);
1187 tu6_emit_vs_system_values(cs
, vs
);
1188 tu6_emit_vpc(cs
, vs
, fs
, binning_pass
, tf
);
1189 tu6_emit_vpc_varying_modes(cs
, fs
, binning_pass
);
1190 tu6_emit_fs_inputs(cs
, fs
);
1191 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
);
1193 tu6_emit_shader_object(cs
, MESA_SHADER_VERTEX
, vs
, binary_bo
,
1194 binning_pass
? builder
->binning_vs_offset
: builder
->shader_offsets
[MESA_SHADER_VERTEX
]);
1196 tu6_emit_shader_object(cs
, MESA_SHADER_FRAGMENT
, fs
, binary_bo
,
1197 builder
->shader_offsets
[MESA_SHADER_FRAGMENT
]);
1199 tu6_emit_immediates(cs
, vs
, CP_LOAD_STATE6_GEOM
, SB6_VS_SHADER
);
1201 tu6_emit_immediates(cs
, fs
, CP_LOAD_STATE6_FRAG
, SB6_FS_SHADER
);
1205 tu6_emit_vertex_input(struct tu_cs
*cs
,
1206 const struct ir3_shader_variant
*vs
,
1207 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
1208 uint8_t bindings
[MAX_VERTEX_ATTRIBS
],
1209 uint16_t strides
[MAX_VERTEX_ATTRIBS
],
1210 uint16_t offsets
[MAX_VERTEX_ATTRIBS
],
1213 uint32_t vfd_decode_idx
= 0;
1215 for (uint32_t i
= 0; i
< vs
->inputs_count
; i
++) {
1216 if (vs
->inputs
[i
].sysval
|| !vs
->inputs
[i
].compmask
)
1219 const VkVertexInputAttributeDescription
*vi_attr
=
1220 tu_find_vertex_input_attribute(vi_info
, vs
->inputs
[i
].slot
);
1221 const VkVertexInputBindingDescription
*vi_binding
=
1222 tu_find_vertex_input_binding(vi_info
, vi_attr
);
1223 assert(vi_attr
&& vi_binding
);
1225 const struct tu_native_format format
= tu6_format_vtx(vi_attr
->format
);
1227 uint32_t vfd_decode
= A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx
) |
1228 A6XX_VFD_DECODE_INSTR_FORMAT(format
.fmt
) |
1229 A6XX_VFD_DECODE_INSTR_SWAP(format
.swap
) |
1230 A6XX_VFD_DECODE_INSTR_UNK30
;
1231 if (vi_binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1232 vfd_decode
|= A6XX_VFD_DECODE_INSTR_INSTANCED
;
1233 if (!vk_format_is_int(vi_attr
->format
))
1234 vfd_decode
|= A6XX_VFD_DECODE_INSTR_FLOAT
;
1236 const uint32_t vfd_decode_step_rate
= 1;
1238 const uint32_t vfd_dest_cntl
=
1239 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs
->inputs
[i
].compmask
) |
1240 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs
->inputs
[i
].regid
);
1242 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DECODE(vfd_decode_idx
), 2);
1243 tu_cs_emit(cs
, vfd_decode
);
1244 tu_cs_emit(cs
, vfd_decode_step_rate
);
1246 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx
), 1);
1247 tu_cs_emit(cs
, vfd_dest_cntl
);
1249 bindings
[vfd_decode_idx
] = vi_binding
->binding
;
1250 strides
[vfd_decode_idx
] = vi_binding
->stride
;
1251 offsets
[vfd_decode_idx
] = vi_attr
->offset
;
1254 assert(vfd_decode_idx
<= MAX_VERTEX_ATTRIBS
);
1257 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_0
, 1);
1259 cs
, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx
) | (vfd_decode_idx
<< 8));
1261 *count
= vfd_decode_idx
;
1265 tu6_guardband_adj(uint32_t v
)
1268 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1274 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1278 scales
[0] = viewport
->width
/ 2.0f
;
1279 scales
[1] = viewport
->height
/ 2.0f
;
1280 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1281 offsets
[0] = viewport
->x
+ scales
[0];
1282 offsets
[1] = viewport
->y
+ scales
[1];
1283 offsets
[2] = viewport
->minDepth
;
1287 min
.x
= (int32_t) viewport
->x
;
1288 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1289 if (viewport
->height
>= 0.0f
) {
1290 min
.y
= (int32_t) viewport
->y
;
1291 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1293 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1294 max
.y
= (int32_t) ceilf(viewport
->y
);
1296 /* the spec allows viewport->height to be 0.0f */
1299 assert(min
.x
>= 0 && min
.x
< max
.x
);
1300 assert(min
.y
>= 0 && min
.y
< max
.y
);
1302 VkExtent2D guardband_adj
;
1303 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1304 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1306 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
1307 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets
[0]).value
);
1308 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XSCALE_0(scales
[0]).value
);
1309 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets
[1]).value
);
1310 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YSCALE_0(scales
[1]).value
);
1311 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets
[2]).value
);
1312 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales
[2]).value
);
1314 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
1315 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min
.x
) |
1316 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min
.y
));
1317 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max
.x
- 1) |
1318 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max
.y
- 1));
1320 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1322 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1323 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1327 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1329 const VkOffset2D min
= scissor
->offset
;
1330 const VkOffset2D max
= {
1331 scissor
->offset
.x
+ scissor
->extent
.width
,
1332 scissor
->offset
.y
+ scissor
->extent
.height
,
1335 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
1336 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min
.x
) |
1337 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min
.y
));
1338 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max
.x
- 1) |
1339 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max
.y
- 1));
1343 tu6_emit_gras_unknowns(struct tu_cs
*cs
)
1345 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_DISABLE_CNTL
, 1);
1346 tu_cs_emit(cs
, A6XX_GRAS_DISABLE_CNTL_VP_CLIP_CODE_IGNORE
);
1347 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8001
, 1);
1348 tu_cs_emit(cs
, 0x0);
1349 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LAYER_CNTL
, 1);
1350 tu_cs_emit(cs
, 0x0);
1354 tu6_emit_point_size(struct tu_cs
*cs
)
1356 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POINT_MINMAX
, 2);
1357 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f
/ 16.0f
) |
1358 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f
));
1359 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_SIZE(1.0f
).value
);
1363 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1364 VkSampleCountFlagBits samples
)
1366 uint32_t gras_su_cntl
= 0;
1368 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1369 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1370 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1371 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1373 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1374 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1376 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1378 if (rast_info
->depthBiasEnable
)
1379 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1381 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1382 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1384 return gras_su_cntl
;
1388 tu6_emit_gras_su_cntl(struct tu_cs
*cs
,
1389 uint32_t gras_su_cntl
,
1392 assert((gras_su_cntl
& A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
) == 0);
1393 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width
/ 2.0f
);
1395 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_CNTL
, 1);
1396 tu_cs_emit(cs
, gras_su_cntl
);
1400 tu6_emit_depth_bias(struct tu_cs
*cs
,
1401 float constant_factor
,
1405 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1406 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
).value
);
1407 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
).value
);
1408 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
).value
);
1412 tu6_emit_alpha_control_disable(struct tu_cs
*cs
)
1414 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_ALPHA_CONTROL
, 1);
1419 tu6_emit_depth_control(struct tu_cs
*cs
,
1420 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1422 assert(!ds_info
->depthBoundsTestEnable
);
1424 uint32_t rb_depth_cntl
= 0;
1425 if (ds_info
->depthTestEnable
) {
1427 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1428 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1429 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1431 if (ds_info
->depthWriteEnable
)
1432 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1435 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1436 tu_cs_emit(cs
, rb_depth_cntl
);
1440 tu6_emit_stencil_control(struct tu_cs
*cs
,
1441 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1443 uint32_t rb_stencil_control
= 0;
1444 if (ds_info
->stencilTestEnable
) {
1445 const VkStencilOpState
*front
= &ds_info
->front
;
1446 const VkStencilOpState
*back
= &ds_info
->back
;
1447 rb_stencil_control
|=
1448 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1449 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1450 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1451 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1452 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1453 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1454 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1455 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1456 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1457 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1458 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1461 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1462 tu_cs_emit(cs
, rb_stencil_control
);
1466 tu6_emit_stencil_compare_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1468 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILMASK
, 1);
1470 cs
, A6XX_RB_STENCILMASK_MASK(front
) | A6XX_RB_STENCILMASK_BFMASK(back
));
1474 tu6_emit_stencil_write_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1476 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILWRMASK
, 1);
1477 tu_cs_emit(cs
, A6XX_RB_STENCILWRMASK_WRMASK(front
) |
1478 A6XX_RB_STENCILWRMASK_BFWRMASK(back
));
1482 tu6_emit_stencil_reference(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1484 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILREF
, 1);
1486 A6XX_RB_STENCILREF_REF(front
) | A6XX_RB_STENCILREF_BFREF(back
));
1490 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1493 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1494 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1495 has_alpha
? att
->srcColorBlendFactor
1496 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1497 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1498 has_alpha
? att
->dstColorBlendFactor
1499 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1500 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1501 const enum adreno_rb_blend_factor src_alpha_factor
=
1502 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1503 const enum adreno_rb_blend_factor dst_alpha_factor
=
1504 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1506 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1507 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1508 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1509 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1510 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1511 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1515 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1516 uint32_t rb_mrt_control_rop
,
1520 uint32_t rb_mrt_control
=
1521 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1523 /* ignore blending and logic op for integer attachments */
1525 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1526 return rb_mrt_control
;
1529 rb_mrt_control
|= rb_mrt_control_rop
;
1531 if (att
->blendEnable
) {
1532 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1535 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1538 return rb_mrt_control
;
1542 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1543 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1544 const VkFormat attachment_formats
[MAX_RTS
],
1545 uint32_t *blend_enable_mask
)
1547 *blend_enable_mask
= 0;
1549 bool rop_reads_dst
= false;
1550 uint32_t rb_mrt_control_rop
= 0;
1551 if (blend_info
->logicOpEnable
) {
1552 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1553 rb_mrt_control_rop
=
1554 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1555 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1558 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
1559 const VkPipelineColorBlendAttachmentState
*att
=
1560 &blend_info
->pAttachments
[i
];
1561 const VkFormat format
= attachment_formats
[i
];
1563 uint32_t rb_mrt_control
= 0;
1564 uint32_t rb_mrt_blend_control
= 0;
1565 if (format
!= VK_FORMAT_UNDEFINED
) {
1566 const bool is_int
= vk_format_is_int(format
);
1567 const bool has_alpha
= vk_format_has_alpha(format
);
1570 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
1571 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
1573 if (att
->blendEnable
|| rop_reads_dst
)
1574 *blend_enable_mask
|= 1 << i
;
1577 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1578 tu_cs_emit(cs
, rb_mrt_control
);
1579 tu_cs_emit(cs
, rb_mrt_blend_control
);
1584 tu6_emit_blend_control(struct tu_cs
*cs
,
1585 uint32_t blend_enable_mask
,
1586 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
1588 assert(!msaa_info
->alphaToOneEnable
);
1590 uint32_t sp_blend_cntl
= A6XX_SP_BLEND_CNTL_UNK8
;
1591 if (blend_enable_mask
)
1592 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ENABLED
;
1593 if (msaa_info
->alphaToCoverageEnable
)
1594 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1596 const uint32_t sample_mask
=
1597 msaa_info
->pSampleMask
? *msaa_info
->pSampleMask
1598 : ((1 << msaa_info
->rasterizationSamples
) - 1);
1600 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1601 uint32_t rb_blend_cntl
=
1602 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask
) |
1603 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND
|
1604 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask
);
1605 if (msaa_info
->alphaToCoverageEnable
)
1606 rb_blend_cntl
|= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1608 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_BLEND_CNTL
, 1);
1609 tu_cs_emit(cs
, sp_blend_cntl
);
1611 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_CNTL
, 1);
1612 tu_cs_emit(cs
, rb_blend_cntl
);
1616 tu6_emit_blend_constants(struct tu_cs
*cs
, const float constants
[4])
1618 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
1619 tu_cs_emit_array(cs
, (const uint32_t *) constants
, 4);
1623 tu_pipeline_create(struct tu_device
*dev
,
1624 const VkAllocationCallbacks
*pAllocator
,
1625 struct tu_pipeline
**out_pipeline
)
1627 struct tu_pipeline
*pipeline
=
1628 vk_zalloc2(&dev
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1629 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1631 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1633 tu_cs_init(&pipeline
->cs
, dev
, TU_CS_MODE_SUB_STREAM
, 2048);
1635 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1636 VkResult result
= tu_cs_reserve_space(&pipeline
->cs
, 2048);
1637 if (result
!= VK_SUCCESS
) {
1638 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
1642 *out_pipeline
= pipeline
;
1648 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
)
1650 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
1653 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1654 gl_shader_stage stage
=
1655 tu_shader_stage(builder
->create_info
->pStages
[i
].stage
);
1656 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
1659 struct tu_shader_compile_options options
;
1660 tu_shader_compile_options_init(&options
, builder
->create_info
);
1662 /* compile shaders in reverse order */
1663 struct tu_shader
*next_stage_shader
= NULL
;
1664 for (gl_shader_stage stage
= MESA_SHADER_STAGES
- 1;
1665 stage
> MESA_SHADER_NONE
; stage
--) {
1666 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
1670 struct tu_shader
*shader
=
1671 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->layout
,
1674 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1677 tu_shader_compile(builder
->device
, shader
, next_stage_shader
,
1678 &options
, builder
->alloc
);
1679 if (result
!= VK_SUCCESS
)
1682 builder
->shaders
[stage
] = shader
;
1683 builder
->shader_offsets
[stage
] = builder
->shader_total_size
;
1684 builder
->shader_total_size
+=
1685 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
;
1687 next_stage_shader
= shader
;
1690 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1691 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1692 const struct ir3_shader_variant
*variant
;
1694 if (vs
->ir3_shader
.stream_output
.num_outputs
)
1695 variant
= &vs
->variants
[0];
1697 variant
= &vs
->variants
[1];
1699 builder
->binning_vs_offset
= builder
->shader_total_size
;
1700 builder
->shader_total_size
+=
1701 sizeof(uint32_t) * variant
->info
.sizedwords
;
1708 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder
*builder
,
1709 struct tu_pipeline
*pipeline
)
1711 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
1714 tu_bo_init_new(builder
->device
, bo
, builder
->shader_total_size
);
1715 if (result
!= VK_SUCCESS
)
1718 result
= tu_bo_map(builder
->device
, bo
);
1719 if (result
!= VK_SUCCESS
)
1722 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1723 const struct tu_shader
*shader
= builder
->shaders
[i
];
1727 memcpy(bo
->map
+ builder
->shader_offsets
[i
], shader
->binary
,
1728 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
);
1731 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1732 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1733 const struct ir3_shader_variant
*variant
;
1736 if (vs
->ir3_shader
.stream_output
.num_outputs
) {
1737 variant
= &vs
->variants
[0];
1740 variant
= &vs
->variants
[1];
1741 bin
= vs
->binning_binary
;
1744 memcpy(bo
->map
+ builder
->binning_vs_offset
, bin
,
1745 sizeof(uint32_t) * variant
->info
.sizedwords
);
1752 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
1753 struct tu_pipeline
*pipeline
)
1755 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
1756 builder
->create_info
->pDynamicState
;
1761 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
1762 pipeline
->dynamic_state
.mask
|=
1763 tu_dynamic_state_bit(dynamic_info
->pDynamicStates
[i
]);
1768 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage
*link
,
1769 struct tu_shader
*shader
,
1770 struct ir3_shader_variant
*v
)
1772 link
->ubo_state
= v
->shader
->ubo_state
;
1773 link
->const_state
= v
->shader
->const_state
;
1774 link
->constlen
= v
->constlen
;
1775 link
->texture_map
= shader
->texture_map
;
1776 link
->sampler_map
= shader
->sampler_map
;
1777 link
->ubo_map
= shader
->ubo_map
;
1778 link
->ssbo_map
= shader
->ssbo_map
;
1779 link
->image_map
= shader
->image_map
;
1783 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
1784 struct tu_pipeline
*pipeline
)
1786 struct tu_cs prog_cs
;
1787 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
1788 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, false, &pipeline
->streamout
);
1789 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1791 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
1792 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, true, &pipeline
->streamout
);
1793 pipeline
->program
.binning_state_ib
=
1794 tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1796 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1797 if (!builder
->shaders
[i
])
1800 tu_pipeline_set_linkage(&pipeline
->program
.link
[i
],
1801 builder
->shaders
[i
],
1802 &builder
->shaders
[i
]->variants
[0]);
1807 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
1808 struct tu_pipeline
*pipeline
)
1810 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1811 builder
->create_info
->pVertexInputState
;
1812 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1815 tu_cs_begin_sub_stream(&pipeline
->cs
,
1816 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
1817 tu6_emit_vertex_input(&vi_cs
, &vs
->variants
[0], vi_info
,
1818 pipeline
->vi
.bindings
, pipeline
->vi
.strides
,
1819 pipeline
->vi
.offsets
, &pipeline
->vi
.count
);
1820 pipeline
->vi
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
1822 if (vs
->has_binning_pass
) {
1823 tu_cs_begin_sub_stream(&pipeline
->cs
,
1824 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
1825 tu6_emit_vertex_input(
1826 &vi_cs
, &vs
->variants
[1], vi_info
, pipeline
->vi
.binning_bindings
,
1827 pipeline
->vi
.binning_strides
, pipeline
->vi
.binning_offsets
,
1828 &pipeline
->vi
.binning_count
);
1829 pipeline
->vi
.binning_state_ib
=
1830 tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
1835 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
1836 struct tu_pipeline
*pipeline
)
1838 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1839 builder
->create_info
->pInputAssemblyState
;
1841 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
1842 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
1846 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
1847 struct tu_pipeline
*pipeline
)
1851 * pViewportState is a pointer to an instance of the
1852 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1853 * pipeline has rasterization disabled."
1855 * We leave the relevant registers stale in that case.
1857 if (builder
->rasterizer_discard
)
1860 const VkPipelineViewportStateCreateInfo
*vp_info
=
1861 builder
->create_info
->pViewportState
;
1864 tu_cs_begin_sub_stream(&pipeline
->cs
, 15, &vp_cs
);
1866 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
1867 assert(vp_info
->viewportCount
== 1);
1868 tu6_emit_viewport(&vp_cs
, vp_info
->pViewports
);
1871 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
1872 assert(vp_info
->scissorCount
== 1);
1873 tu6_emit_scissor(&vp_cs
, vp_info
->pScissors
);
1876 pipeline
->vp
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vp_cs
);
1880 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
1881 struct tu_pipeline
*pipeline
)
1883 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
1884 builder
->create_info
->pRasterizationState
;
1886 assert(!rast_info
->depthClampEnable
);
1887 assert(rast_info
->polygonMode
== VK_POLYGON_MODE_FILL
);
1889 struct tu_cs rast_cs
;
1890 tu_cs_begin_sub_stream(&pipeline
->cs
, 20, &rast_cs
);
1892 /* move to hw ctx init? */
1893 tu6_emit_gras_unknowns(&rast_cs
);
1894 tu6_emit_point_size(&rast_cs
);
1896 const uint32_t gras_su_cntl
=
1897 tu6_gras_su_cntl(rast_info
, builder
->samples
);
1899 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
))
1900 tu6_emit_gras_su_cntl(&rast_cs
, gras_su_cntl
, rast_info
->lineWidth
);
1902 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_DEPTH_BIAS
)) {
1903 tu6_emit_depth_bias(&rast_cs
, rast_info
->depthBiasConstantFactor
,
1904 rast_info
->depthBiasClamp
,
1905 rast_info
->depthBiasSlopeFactor
);
1908 pipeline
->rast
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &rast_cs
);
1910 pipeline
->rast
.gras_su_cntl
= gras_su_cntl
;
1914 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
1915 struct tu_pipeline
*pipeline
)
1919 * pDepthStencilState is a pointer to an instance of the
1920 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1921 * the pipeline has rasterization disabled or if the subpass of the
1922 * render pass the pipeline is created against does not use a
1923 * depth/stencil attachment.
1925 * We disable both depth and stenil tests in those cases.
1927 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
1928 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
1929 builder
->use_depth_stencil_attachment
1930 ? builder
->create_info
->pDepthStencilState
1934 tu_cs_begin_sub_stream(&pipeline
->cs
, 12, &ds_cs
);
1936 /* move to hw ctx init? */
1937 tu6_emit_alpha_control_disable(&ds_cs
);
1939 tu6_emit_depth_control(&ds_cs
, ds_info
);
1940 tu6_emit_stencil_control(&ds_cs
, ds_info
);
1942 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
1943 tu6_emit_stencil_compare_mask(&ds_cs
, ds_info
->front
.compareMask
,
1944 ds_info
->back
.compareMask
);
1946 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
1947 tu6_emit_stencil_write_mask(&ds_cs
, ds_info
->front
.writeMask
,
1948 ds_info
->back
.writeMask
);
1950 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
1951 tu6_emit_stencil_reference(&ds_cs
, ds_info
->front
.reference
,
1952 ds_info
->back
.reference
);
1955 pipeline
->ds
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &ds_cs
);
1959 tu_pipeline_builder_parse_multisample_and_color_blend(
1960 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
1964 * pMultisampleState is a pointer to an instance of the
1965 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1966 * has rasterization disabled.
1970 * pColorBlendState is a pointer to an instance of the
1971 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1972 * pipeline has rasterization disabled or if the subpass of the render
1973 * pass the pipeline is created against does not use any color
1976 * We leave the relevant registers stale when rasterization is disabled.
1978 if (builder
->rasterizer_discard
)
1981 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
1982 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
1983 builder
->create_info
->pMultisampleState
;
1984 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
1985 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
1986 : &dummy_blend_info
;
1988 struct tu_cs blend_cs
;
1989 tu_cs_begin_sub_stream(&pipeline
->cs
, MAX_RTS
* 3 + 9, &blend_cs
);
1991 uint32_t blend_enable_mask
;
1992 tu6_emit_rb_mrt_controls(&blend_cs
, blend_info
,
1993 builder
->color_attachment_formats
,
1994 &blend_enable_mask
);
1996 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_BLEND_CONSTANTS
))
1997 tu6_emit_blend_constants(&blend_cs
, blend_info
->blendConstants
);
1999 tu6_emit_blend_control(&blend_cs
, blend_enable_mask
, msaa_info
);
2001 pipeline
->blend
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &blend_cs
);
2005 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
2006 struct tu_device
*dev
,
2007 const VkAllocationCallbacks
*alloc
)
2009 tu_cs_finish(&pipeline
->cs
);
2011 if (pipeline
->program
.binary_bo
.gem_handle
)
2012 tu_bo_finish(dev
, &pipeline
->program
.binary_bo
);
2016 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
2017 struct tu_pipeline
**pipeline
)
2019 VkResult result
= tu_pipeline_create(builder
->device
, builder
->alloc
,
2021 if (result
!= VK_SUCCESS
)
2024 /* compile and upload shaders */
2025 result
= tu_pipeline_builder_compile_shaders(builder
);
2026 if (result
== VK_SUCCESS
)
2027 result
= tu_pipeline_builder_upload_shaders(builder
, *pipeline
);
2028 if (result
!= VK_SUCCESS
) {
2029 tu_pipeline_finish(*pipeline
, builder
->device
, builder
->alloc
);
2030 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
2031 *pipeline
= VK_NULL_HANDLE
;
2036 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
2037 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
2038 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
2039 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
2040 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
2041 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
2042 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
2043 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
2045 /* we should have reserved enough space upfront such that the CS never
2048 assert((*pipeline
)->cs
.bo_count
== 1);
2054 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
2056 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2057 if (!builder
->shaders
[i
])
2059 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
2064 tu_pipeline_builder_init_graphics(
2065 struct tu_pipeline_builder
*builder
,
2066 struct tu_device
*dev
,
2067 struct tu_pipeline_cache
*cache
,
2068 const VkGraphicsPipelineCreateInfo
*create_info
,
2069 const VkAllocationCallbacks
*alloc
)
2071 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, create_info
->layout
);
2073 *builder
= (struct tu_pipeline_builder
) {
2076 .create_info
= create_info
,
2081 builder
->rasterizer_discard
=
2082 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
2084 if (builder
->rasterizer_discard
) {
2085 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
2087 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
2089 const struct tu_render_pass
*pass
=
2090 tu_render_pass_from_handle(create_info
->renderPass
);
2091 const struct tu_subpass
*subpass
=
2092 &pass
->subpasses
[create_info
->subpass
];
2094 builder
->use_depth_stencil_attachment
=
2095 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
;
2097 assert(subpass
->color_count
== 0 ||
2098 !create_info
->pColorBlendState
||
2099 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
2100 builder
->color_attachment_count
= subpass
->color_count
;
2101 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
2102 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
2103 if (a
== VK_ATTACHMENT_UNUSED
)
2106 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
2107 builder
->use_color_attachments
= true;
2113 tu_graphics_pipeline_create(VkDevice device
,
2114 VkPipelineCache pipelineCache
,
2115 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2116 const VkAllocationCallbacks
*pAllocator
,
2117 VkPipeline
*pPipeline
)
2119 TU_FROM_HANDLE(tu_device
, dev
, device
);
2120 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
2122 struct tu_pipeline_builder builder
;
2123 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
2124 pCreateInfo
, pAllocator
);
2126 struct tu_pipeline
*pipeline
= NULL
;
2127 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
2128 tu_pipeline_builder_finish(&builder
);
2130 if (result
== VK_SUCCESS
)
2131 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2133 *pPipeline
= VK_NULL_HANDLE
;
2139 tu_CreateGraphicsPipelines(VkDevice device
,
2140 VkPipelineCache pipelineCache
,
2142 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
2143 const VkAllocationCallbacks
*pAllocator
,
2144 VkPipeline
*pPipelines
)
2146 VkResult final_result
= VK_SUCCESS
;
2148 for (uint32_t i
= 0; i
< count
; i
++) {
2149 VkResult result
= tu_graphics_pipeline_create(device
, pipelineCache
,
2150 &pCreateInfos
[i
], pAllocator
,
2153 if (result
!= VK_SUCCESS
)
2154 final_result
= result
;
2157 return final_result
;
2161 tu6_emit_compute_program(struct tu_cs
*cs
,
2162 struct tu_shader
*shader
,
2163 const struct tu_bo
*binary_bo
)
2165 const struct ir3_shader_variant
*v
= &shader
->variants
[0];
2167 tu6_emit_cs_config(cs
, shader
, v
);
2169 /* The compute program is the only one in the pipeline, so 0 offset. */
2170 tu6_emit_shader_object(cs
, MESA_SHADER_COMPUTE
, v
, binary_bo
, 0);
2172 tu6_emit_immediates(cs
, v
, CP_LOAD_STATE6_FRAG
, SB6_CS_SHADER
);
2176 tu_compute_upload_shader(VkDevice device
,
2177 struct tu_pipeline
*pipeline
,
2178 struct tu_shader
*shader
)
2180 TU_FROM_HANDLE(tu_device
, dev
, device
);
2181 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
2182 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2184 uint32_t shader_size
= sizeof(uint32_t) * v
->info
.sizedwords
;
2186 tu_bo_init_new(dev
, bo
, shader_size
);
2187 if (result
!= VK_SUCCESS
)
2190 result
= tu_bo_map(dev
, bo
);
2191 if (result
!= VK_SUCCESS
)
2194 memcpy(bo
->map
, shader
->binary
, shader_size
);
2201 tu_compute_pipeline_create(VkDevice device
,
2202 VkPipelineCache _cache
,
2203 const VkComputePipelineCreateInfo
*pCreateInfo
,
2204 const VkAllocationCallbacks
*pAllocator
,
2205 VkPipeline
*pPipeline
)
2207 TU_FROM_HANDLE(tu_device
, dev
, device
);
2208 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, pCreateInfo
->layout
);
2209 const VkPipelineShaderStageCreateInfo
*stage_info
= &pCreateInfo
->stage
;
2212 struct tu_pipeline
*pipeline
;
2214 *pPipeline
= VK_NULL_HANDLE
;
2216 result
= tu_pipeline_create(dev
, pAllocator
, &pipeline
);
2217 if (result
!= VK_SUCCESS
)
2220 pipeline
->layout
= layout
;
2222 struct tu_shader_compile_options options
;
2223 tu_shader_compile_options_init(&options
, NULL
);
2225 struct tu_shader
*shader
=
2226 tu_shader_create(dev
, MESA_SHADER_COMPUTE
, stage_info
, layout
, pAllocator
);
2228 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2232 result
= tu_shader_compile(dev
, shader
, NULL
, &options
, pAllocator
);
2233 if (result
!= VK_SUCCESS
)
2236 struct ir3_shader_variant
*v
= &shader
->variants
[0];
2238 tu_pipeline_set_linkage(&pipeline
->program
.link
[MESA_SHADER_COMPUTE
],
2241 result
= tu_compute_upload_shader(device
, pipeline
, shader
);
2242 if (result
!= VK_SUCCESS
)
2245 for (int i
= 0; i
< 3; i
++)
2246 pipeline
->compute
.local_size
[i
] = v
->shader
->nir
->info
.cs
.local_size
[i
];
2248 struct tu_cs prog_cs
;
2249 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2250 tu6_emit_compute_program(&prog_cs
, shader
, &pipeline
->program
.binary_bo
);
2251 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2253 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2258 tu_shader_destroy(dev
, shader
, pAllocator
);
2260 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2261 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
2267 tu_CreateComputePipelines(VkDevice device
,
2268 VkPipelineCache pipelineCache
,
2270 const VkComputePipelineCreateInfo
*pCreateInfos
,
2271 const VkAllocationCallbacks
*pAllocator
,
2272 VkPipeline
*pPipelines
)
2274 VkResult final_result
= VK_SUCCESS
;
2276 for (uint32_t i
= 0; i
< count
; i
++) {
2277 VkResult result
= tu_compute_pipeline_create(device
, pipelineCache
,
2279 pAllocator
, &pPipelines
[i
]);
2280 if (result
!= VK_SUCCESS
)
2281 final_result
= result
;
2284 return final_result
;
2288 tu_DestroyPipeline(VkDevice _device
,
2289 VkPipeline _pipeline
,
2290 const VkAllocationCallbacks
*pAllocator
)
2292 TU_FROM_HANDLE(tu_device
, dev
, _device
);
2293 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2298 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2299 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);