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tu: Switch to the bindless descriptor model
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 struct tu_pipeline_builder
44 {
45 struct tu_device *device;
46 struct tu_pipeline_cache *cache;
47 struct tu_pipeline_layout *layout;
48 const VkAllocationCallbacks *alloc;
49 const VkGraphicsPipelineCreateInfo *create_info;
50
51 struct tu_shader *shaders[MESA_SHADER_STAGES];
52 uint32_t shader_offsets[MESA_SHADER_STAGES];
53 uint32_t binning_vs_offset;
54 uint32_t shader_total_size;
55
56 bool rasterizer_discard;
57 /* these states are affectd by rasterizer_discard */
58 VkSampleCountFlagBits samples;
59 bool use_depth_stencil_attachment;
60 bool use_color_attachments;
61 uint32_t color_attachment_count;
62 VkFormat color_attachment_formats[MAX_RTS];
63 };
64
65 static enum tu_dynamic_state_bits
66 tu_dynamic_state_bit(VkDynamicState state)
67 {
68 switch (state) {
69 case VK_DYNAMIC_STATE_VIEWPORT:
70 return TU_DYNAMIC_VIEWPORT;
71 case VK_DYNAMIC_STATE_SCISSOR:
72 return TU_DYNAMIC_SCISSOR;
73 case VK_DYNAMIC_STATE_LINE_WIDTH:
74 return TU_DYNAMIC_LINE_WIDTH;
75 case VK_DYNAMIC_STATE_DEPTH_BIAS:
76 return TU_DYNAMIC_DEPTH_BIAS;
77 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
78 return TU_DYNAMIC_BLEND_CONSTANTS;
79 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
80 return TU_DYNAMIC_DEPTH_BOUNDS;
81 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
82 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
83 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
84 return TU_DYNAMIC_STENCIL_WRITE_MASK;
85 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
86 return TU_DYNAMIC_STENCIL_REFERENCE;
87 default:
88 unreachable("invalid dynamic state");
89 return 0;
90 }
91 }
92
93 static gl_shader_stage
94 tu_shader_stage(VkShaderStageFlagBits stage)
95 {
96 switch (stage) {
97 case VK_SHADER_STAGE_VERTEX_BIT:
98 return MESA_SHADER_VERTEX;
99 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
100 return MESA_SHADER_TESS_CTRL;
101 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
102 return MESA_SHADER_TESS_EVAL;
103 case VK_SHADER_STAGE_GEOMETRY_BIT:
104 return MESA_SHADER_GEOMETRY;
105 case VK_SHADER_STAGE_FRAGMENT_BIT:
106 return MESA_SHADER_FRAGMENT;
107 case VK_SHADER_STAGE_COMPUTE_BIT:
108 return MESA_SHADER_COMPUTE;
109 default:
110 unreachable("invalid VkShaderStageFlagBits");
111 return MESA_SHADER_NONE;
112 }
113 }
114
115 static bool
116 tu_logic_op_reads_dst(VkLogicOp op)
117 {
118 switch (op) {
119 case VK_LOGIC_OP_CLEAR:
120 case VK_LOGIC_OP_COPY:
121 case VK_LOGIC_OP_COPY_INVERTED:
122 case VK_LOGIC_OP_SET:
123 return false;
124 default:
125 return true;
126 }
127 }
128
129 static VkBlendFactor
130 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
131 {
132 /* treat dst alpha as 1.0 and avoid reading it */
133 switch (factor) {
134 case VK_BLEND_FACTOR_DST_ALPHA:
135 return VK_BLEND_FACTOR_ONE;
136 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
137 return VK_BLEND_FACTOR_ZERO;
138 default:
139 return factor;
140 }
141 }
142
143 static enum pc_di_primtype
144 tu6_primtype(VkPrimitiveTopology topology)
145 {
146 switch (topology) {
147 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
148 return DI_PT_POINTLIST;
149 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
150 return DI_PT_LINELIST;
151 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
152 return DI_PT_LINESTRIP;
153 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
154 return DI_PT_TRILIST;
155 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
156 return DI_PT_TRISTRIP;
157 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
158 return DI_PT_TRIFAN;
159 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
160 return DI_PT_LINE_ADJ;
161 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
162 return DI_PT_LINESTRIP_ADJ;
163 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
164 return DI_PT_TRI_ADJ;
165 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
166 return DI_PT_TRISTRIP_ADJ;
167 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
168 default:
169 unreachable("invalid primitive topology");
170 return DI_PT_NONE;
171 }
172 }
173
174 static enum adreno_compare_func
175 tu6_compare_func(VkCompareOp op)
176 {
177 switch (op) {
178 case VK_COMPARE_OP_NEVER:
179 return FUNC_NEVER;
180 case VK_COMPARE_OP_LESS:
181 return FUNC_LESS;
182 case VK_COMPARE_OP_EQUAL:
183 return FUNC_EQUAL;
184 case VK_COMPARE_OP_LESS_OR_EQUAL:
185 return FUNC_LEQUAL;
186 case VK_COMPARE_OP_GREATER:
187 return FUNC_GREATER;
188 case VK_COMPARE_OP_NOT_EQUAL:
189 return FUNC_NOTEQUAL;
190 case VK_COMPARE_OP_GREATER_OR_EQUAL:
191 return FUNC_GEQUAL;
192 case VK_COMPARE_OP_ALWAYS:
193 return FUNC_ALWAYS;
194 default:
195 unreachable("invalid VkCompareOp");
196 return FUNC_NEVER;
197 }
198 }
199
200 static enum adreno_stencil_op
201 tu6_stencil_op(VkStencilOp op)
202 {
203 switch (op) {
204 case VK_STENCIL_OP_KEEP:
205 return STENCIL_KEEP;
206 case VK_STENCIL_OP_ZERO:
207 return STENCIL_ZERO;
208 case VK_STENCIL_OP_REPLACE:
209 return STENCIL_REPLACE;
210 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
211 return STENCIL_INCR_CLAMP;
212 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
213 return STENCIL_DECR_CLAMP;
214 case VK_STENCIL_OP_INVERT:
215 return STENCIL_INVERT;
216 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
217 return STENCIL_INCR_WRAP;
218 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
219 return STENCIL_DECR_WRAP;
220 default:
221 unreachable("invalid VkStencilOp");
222 return STENCIL_KEEP;
223 }
224 }
225
226 static enum a3xx_rop_code
227 tu6_rop(VkLogicOp op)
228 {
229 switch (op) {
230 case VK_LOGIC_OP_CLEAR:
231 return ROP_CLEAR;
232 case VK_LOGIC_OP_AND:
233 return ROP_AND;
234 case VK_LOGIC_OP_AND_REVERSE:
235 return ROP_AND_REVERSE;
236 case VK_LOGIC_OP_COPY:
237 return ROP_COPY;
238 case VK_LOGIC_OP_AND_INVERTED:
239 return ROP_AND_INVERTED;
240 case VK_LOGIC_OP_NO_OP:
241 return ROP_NOOP;
242 case VK_LOGIC_OP_XOR:
243 return ROP_XOR;
244 case VK_LOGIC_OP_OR:
245 return ROP_OR;
246 case VK_LOGIC_OP_NOR:
247 return ROP_NOR;
248 case VK_LOGIC_OP_EQUIVALENT:
249 return ROP_EQUIV;
250 case VK_LOGIC_OP_INVERT:
251 return ROP_INVERT;
252 case VK_LOGIC_OP_OR_REVERSE:
253 return ROP_OR_REVERSE;
254 case VK_LOGIC_OP_COPY_INVERTED:
255 return ROP_COPY_INVERTED;
256 case VK_LOGIC_OP_OR_INVERTED:
257 return ROP_OR_INVERTED;
258 case VK_LOGIC_OP_NAND:
259 return ROP_NAND;
260 case VK_LOGIC_OP_SET:
261 return ROP_SET;
262 default:
263 unreachable("invalid VkLogicOp");
264 return ROP_NOOP;
265 }
266 }
267
268 static enum adreno_rb_blend_factor
269 tu6_blend_factor(VkBlendFactor factor)
270 {
271 switch (factor) {
272 case VK_BLEND_FACTOR_ZERO:
273 return FACTOR_ZERO;
274 case VK_BLEND_FACTOR_ONE:
275 return FACTOR_ONE;
276 case VK_BLEND_FACTOR_SRC_COLOR:
277 return FACTOR_SRC_COLOR;
278 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
279 return FACTOR_ONE_MINUS_SRC_COLOR;
280 case VK_BLEND_FACTOR_DST_COLOR:
281 return FACTOR_DST_COLOR;
282 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
283 return FACTOR_ONE_MINUS_DST_COLOR;
284 case VK_BLEND_FACTOR_SRC_ALPHA:
285 return FACTOR_SRC_ALPHA;
286 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
287 return FACTOR_ONE_MINUS_SRC_ALPHA;
288 case VK_BLEND_FACTOR_DST_ALPHA:
289 return FACTOR_DST_ALPHA;
290 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
291 return FACTOR_ONE_MINUS_DST_ALPHA;
292 case VK_BLEND_FACTOR_CONSTANT_COLOR:
293 return FACTOR_CONSTANT_COLOR;
294 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
295 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
296 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
297 return FACTOR_CONSTANT_ALPHA;
298 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
299 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
300 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
301 return FACTOR_SRC_ALPHA_SATURATE;
302 case VK_BLEND_FACTOR_SRC1_COLOR:
303 return FACTOR_SRC1_COLOR;
304 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
305 return FACTOR_ONE_MINUS_SRC1_COLOR;
306 case VK_BLEND_FACTOR_SRC1_ALPHA:
307 return FACTOR_SRC1_ALPHA;
308 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
309 return FACTOR_ONE_MINUS_SRC1_ALPHA;
310 default:
311 unreachable("invalid VkBlendFactor");
312 return FACTOR_ZERO;
313 }
314 }
315
316 static enum a3xx_rb_blend_opcode
317 tu6_blend_op(VkBlendOp op)
318 {
319 switch (op) {
320 case VK_BLEND_OP_ADD:
321 return BLEND_DST_PLUS_SRC;
322 case VK_BLEND_OP_SUBTRACT:
323 return BLEND_SRC_MINUS_DST;
324 case VK_BLEND_OP_REVERSE_SUBTRACT:
325 return BLEND_DST_MINUS_SRC;
326 case VK_BLEND_OP_MIN:
327 return BLEND_MIN_DST_SRC;
328 case VK_BLEND_OP_MAX:
329 return BLEND_MAX_DST_SRC;
330 default:
331 unreachable("invalid VkBlendOp");
332 return BLEND_DST_PLUS_SRC;
333 }
334 }
335
336 static uint32_t
337 emit_xs_config(const struct ir3_shader_variant *sh)
338 {
339 if (sh->instrlen) {
340 return A6XX_SP_VS_CONFIG_ENABLED |
341 COND(sh->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
342 COND(sh->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
343 COND(sh->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
344 COND(sh->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO);
345 } else {
346 return 0;
347 }
348 }
349
350 static void
351 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
352 const struct ir3_shader_variant *vs)
353 {
354 uint32_t sp_vs_ctrl =
355 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
356 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
357 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
358 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
359 if (vs->need_pixlod)
360 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
361 if (vs->need_fine_derivatives)
362 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_DIFF_FINE;
363
364 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
365 tu_cs_emit(cs, sp_vs_ctrl);
366
367 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
368 tu_cs_emit(cs, emit_xs_config(vs));
369 tu_cs_emit(cs, vs->instrlen);
370
371 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
372 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
373 A6XX_HLSQ_VS_CNTL_ENABLED);
374 }
375
376 static void
377 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
378 const struct ir3_shader_variant *hs)
379 {
380 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
381 tu_cs_emit(cs, 0);
382
383 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
384 tu_cs_emit(cs, emit_xs_config(hs));
385 tu_cs_emit(cs, hs->instrlen);
386
387 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
388 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
389 }
390
391 static void
392 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
393 const struct ir3_shader_variant *ds)
394 {
395 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
396 tu_cs_emit(cs, emit_xs_config(ds));
397 tu_cs_emit(cs, ds->instrlen);
398
399 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
400 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
401 }
402
403 static void
404 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
405 const struct ir3_shader_variant *gs)
406 {
407 bool has_gs = gs->type != MESA_SHADER_NONE;
408 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
409 tu_cs_emit(cs, 0);
410
411 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
412 tu_cs_emit(cs, emit_xs_config(gs));
413 tu_cs_emit(cs, gs->instrlen);
414
415 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
416 tu_cs_emit(cs, COND(has_gs, A6XX_HLSQ_GS_CNTL_ENABLED) |
417 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
418 }
419
420 static void
421 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
422 const struct ir3_shader_variant *fs)
423 {
424 uint32_t sp_fs_ctrl =
425 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
426 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
427 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
428 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
429 if (fs->total_in > 0)
430 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
431 if (fs->need_pixlod)
432 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
433 if (fs->need_fine_derivatives)
434 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_DIFF_FINE;
435
436 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
437 tu_cs_emit(cs, sp_fs_ctrl);
438
439 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
440 tu_cs_emit(cs, emit_xs_config(fs));
441 tu_cs_emit(cs, fs->instrlen);
442
443 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
444 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
445 A6XX_HLSQ_FS_CNTL_ENABLED);
446 }
447
448 static void
449 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
450 const struct ir3_shader_variant *v)
451 {
452 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
453 tu_cs_emit(cs, 0xff);
454
455 unsigned constlen = align(v->constlen, 4);
456 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
457 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
458 A6XX_HLSQ_CS_CNTL_ENABLED);
459
460 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
461 tu_cs_emit(cs, emit_xs_config(v));
462 tu_cs_emit(cs, v->instrlen);
463
464 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
465 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
466 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
467 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
468 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
469 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE) |
470 COND(v->need_fine_derivatives, A6XX_SP_CS_CTRL_REG0_DIFF_FINE));
471
472 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
473 tu_cs_emit(cs, 0x41);
474
475 uint32_t local_invocation_id =
476 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
477 uint32_t work_group_id =
478 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
479
480 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
481 tu_cs_emit(cs,
482 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
483 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
484 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
485 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
486 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
487 }
488
489 static void
490 tu6_emit_vs_system_values(struct tu_cs *cs,
491 const struct ir3_shader_variant *vs,
492 const struct ir3_shader_variant *gs)
493 {
494 const uint32_t vertexid_regid =
495 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
496 const uint32_t instanceid_regid =
497 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
498 const uint32_t primitiveid_regid = gs->type != MESA_SHADER_NONE ?
499 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
500 regid(63, 0);
501 const uint32_t gsheader_regid = gs->type != MESA_SHADER_NONE ?
502 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
503 regid(63, 0);
504
505 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
506 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
507 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
508 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
509 0xfc000000);
510 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
511 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
512 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
513 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
514 0xfc00); /* VFD_CONTROL_5 */
515 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
516 }
517
518 /* Add any missing varyings needed for stream-out. Otherwise varyings not
519 * used by fragment shader will be stripped out.
520 */
521 static void
522 tu6_link_streamout(struct ir3_shader_linkage *l,
523 const struct ir3_shader_variant *v)
524 {
525 const struct ir3_stream_output_info *info = &v->shader->stream_output;
526
527 /*
528 * First, any stream-out varyings not already in linkage map (ie. also
529 * consumed by frag shader) need to be added:
530 */
531 for (unsigned i = 0; i < info->num_outputs; i++) {
532 const struct ir3_stream_output *out = &info->output[i];
533 unsigned compmask =
534 (1 << (out->num_components + out->start_component)) - 1;
535 unsigned k = out->register_index;
536 unsigned idx, nextloc = 0;
537
538 /* psize/pos need to be the last entries in linkage map, and will
539 * get added link_stream_out, so skip over them:
540 */
541 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
542 v->outputs[k].slot == VARYING_SLOT_POS)
543 continue;
544
545 for (idx = 0; idx < l->cnt; idx++) {
546 if (l->var[idx].regid == v->outputs[k].regid)
547 break;
548 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
549 }
550
551 /* add if not already in linkage map: */
552 if (idx == l->cnt)
553 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
554
555 /* expand component-mask if needed, ie streaming out all components
556 * but frag shader doesn't consume all components:
557 */
558 if (compmask & ~l->var[idx].compmask) {
559 l->var[idx].compmask |= compmask;
560 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
561 util_last_bit(l->var[idx].compmask));
562 }
563 }
564 }
565
566 static void
567 tu6_setup_streamout(const struct ir3_shader_variant *v,
568 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
569 {
570 const struct ir3_stream_output_info *info = &v->shader->stream_output;
571
572 memset(tf, 0, sizeof(*tf));
573
574 tf->prog_count = align(l->max_loc, 2) / 2;
575
576 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
577
578 /* set stride info to the streamout state */
579 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
580 tf->stride[i] = info->stride[i];
581
582 for (unsigned i = 0; i < info->num_outputs; i++) {
583 const struct ir3_stream_output *out = &info->output[i];
584 unsigned k = out->register_index;
585 unsigned idx;
586
587 tf->ncomp[out->output_buffer] += out->num_components;
588
589 /* linkage map sorted by order frag shader wants things, so
590 * a bit less ideal here..
591 */
592 for (idx = 0; idx < l->cnt; idx++)
593 if (l->var[idx].regid == v->outputs[k].regid)
594 break;
595
596 debug_assert(idx < l->cnt);
597
598 for (unsigned j = 0; j < out->num_components; j++) {
599 unsigned c = j + out->start_component;
600 unsigned loc = l->var[idx].loc + c;
601 unsigned off = j + out->dst_offset; /* in dwords */
602
603 if (loc & 1) {
604 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
605 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
606 A6XX_VPC_SO_PROG_B_OFF(off * 4);
607 } else {
608 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
609 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
610 A6XX_VPC_SO_PROG_A_OFF(off * 4);
611 }
612 }
613 }
614
615 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
616 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
617 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
618 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
619 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
620 }
621
622 static void
623 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
624 enum a6xx_state_block block, uint32_t offset,
625 uint32_t size, uint32_t *dwords) {
626 assert(size % 4 == 0);
627
628 tu_cs_emit_pkt7(cs, opcode, 3 + size);
629 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
630 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
631 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
632 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
633 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
634
635 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
636 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
637 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
638
639 tu_cs_emit_array(cs, dwords, size);
640 }
641
642 static void
643 tu6_emit_link_map(struct tu_cs *cs,
644 const struct ir3_shader_variant *producer,
645 const struct ir3_shader_variant *consumer) {
646 const struct ir3_const_state *const_state = &consumer->shader->const_state;
647 uint32_t base = const_state->offsets.primitive_map;
648 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
649 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
650 int size = DIV_ROUND_UP(num_loc, 4);
651
652 size = (MIN2(size + base, consumer->constlen) - base) * 4;
653
654 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
655 patch_locs);
656 }
657
658 static uint16_t
659 gl_primitive_to_tess(uint16_t primitive) {
660 switch (primitive) {
661 case GL_POINTS:
662 return TESS_POINTS;
663 case GL_LINE_STRIP:
664 return TESS_LINES;
665 case GL_TRIANGLE_STRIP:
666 return TESS_CW_TRIS;
667 default:
668 unreachable("");
669 }
670 }
671
672 static void
673 tu6_emit_vpc(struct tu_cs *cs,
674 const struct ir3_shader_variant *vs,
675 const struct ir3_shader_variant *gs,
676 const struct ir3_shader_variant *fs,
677 bool binning_pass,
678 struct tu_streamout_state *tf)
679 {
680 bool has_gs = gs->type != MESA_SHADER_NONE;
681 const struct ir3_shader_variant *last_shader = has_gs ? gs : vs;
682 struct ir3_shader_linkage linkage = { 0 };
683 ir3_link_shaders(&linkage, last_shader, fs);
684
685 if (last_shader->shader->stream_output.num_outputs)
686 tu6_link_streamout(&linkage, last_shader);
687
688 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
689 for (uint32_t i = 0; i < linkage.cnt; i++) {
690 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
691 for (uint32_t j = 0; j < comp_count; j++)
692 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
693 }
694
695 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
696 tu_cs_emit(cs, ~vpc_var_enables[0]);
697 tu_cs_emit(cs, ~vpc_var_enables[1]);
698 tu_cs_emit(cs, ~vpc_var_enables[2]);
699 tu_cs_emit(cs, ~vpc_var_enables[3]);
700
701 /* a6xx finds position/pointsize at the end */
702 const uint32_t position_regid =
703 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
704 const uint32_t pointsize_regid =
705 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
706 const uint32_t layer_regid = has_gs ?
707 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
708
709 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
710 if (layer_regid != regid(63, 0)) {
711 layer_loc = linkage.max_loc;
712 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
713 }
714 if (position_regid != regid(63, 0)) {
715 position_loc = linkage.max_loc;
716 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
717 }
718 if (pointsize_regid != regid(63, 0)) {
719 pointsize_loc = linkage.max_loc;
720 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
721 }
722
723 if (last_shader->shader->stream_output.num_outputs)
724 tu6_setup_streamout(last_shader, &linkage, tf);
725
726 /* map outputs of the last shader to VPC */
727 assert(linkage.cnt <= 32);
728 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
729 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
730 uint32_t sp_out[16];
731 uint32_t sp_vpc_dst[8];
732 for (uint32_t i = 0; i < linkage.cnt; i++) {
733 ((uint16_t *) sp_out)[i] =
734 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
735 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
736 ((uint8_t *) sp_vpc_dst)[i] =
737 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
738 }
739
740 if (has_gs)
741 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
742 else
743 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
744 tu_cs_emit_array(cs, sp_out, sp_out_count);
745
746 if (has_gs)
747 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
748 else
749 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
750 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
751
752 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
753 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
754 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
755 0xff00ff00);
756
757 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
758 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
759 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
760 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
761
762 if (has_gs) {
763 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
764 tu_cs_emit(cs, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
765 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
766 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
767 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
768
769 tu6_emit_link_map(cs, vs, gs);
770
771 uint32_t primitive_regid =
772 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
773 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
774 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
775 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
776 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
777
778 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
779 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
780
781 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
782 tu_cs_emit(cs, CONDREG(layer_regid,
783 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
784
785 uint32_t flags_regid = ir3_find_output_regid(gs,
786 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
787
788 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
789 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
790 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
791
792 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
793 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
794 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
795 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
796 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
797
798 uint32_t vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
799 uint16_t output =
800 gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
801 uint32_t invocations = gs->shader->nir->info.gs.invocations - 1;
802 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
803 tu_cs_emit(cs,
804 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
805 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
806 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
807
808 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
809 tu_cs_emit(cs, 0);
810
811 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
812 tu_cs_emit(cs, 0);
813
814 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
815 tu_cs_emit(cs, 0xff);
816
817 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
818 tu_cs_emit(cs, 0xffff00);
819
820 /* Size of per-primitive alloction in ldlw memory in vec4s. */
821 uint32_t vec4_size =
822 gs->shader->nir->info.gs.vertices_in *
823 DIV_ROUND_UP(vs->shader->output_size, 4);
824 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
825 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
826
827 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
828 tu_cs_emit(cs, 0);
829
830 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
831 tu_cs_emit(cs, vs->shader->output_size);
832 }
833
834 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
835 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
836
837 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
838 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
839 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
840 }
841
842 static int
843 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
844 uint32_t index,
845 uint8_t *interp_mode,
846 uint8_t *ps_repl_mode)
847 {
848 enum
849 {
850 INTERP_SMOOTH = 0,
851 INTERP_FLAT = 1,
852 INTERP_ZERO = 2,
853 INTERP_ONE = 3,
854 };
855 enum
856 {
857 PS_REPL_NONE = 0,
858 PS_REPL_S = 1,
859 PS_REPL_T = 2,
860 PS_REPL_ONE_MINUS_T = 3,
861 };
862
863 const uint32_t compmask = fs->inputs[index].compmask;
864
865 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
866 * fourth component occupy three consecutive varying slots
867 */
868 int shift = 0;
869 *interp_mode = 0;
870 *ps_repl_mode = 0;
871 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
872 if (compmask & 0x1) {
873 *ps_repl_mode |= PS_REPL_S << shift;
874 shift += 2;
875 }
876 if (compmask & 0x2) {
877 *ps_repl_mode |= PS_REPL_T << shift;
878 shift += 2;
879 }
880 if (compmask & 0x4) {
881 *interp_mode |= INTERP_ZERO << shift;
882 shift += 2;
883 }
884 if (compmask & 0x8) {
885 *interp_mode |= INTERP_ONE << 6;
886 shift += 2;
887 }
888 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
889 fs->inputs[index].rasterflat) {
890 for (int i = 0; i < 4; i++) {
891 if (compmask & (1 << i)) {
892 *interp_mode |= INTERP_FLAT << shift;
893 shift += 2;
894 }
895 }
896 }
897
898 return shift;
899 }
900
901 static void
902 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
903 const struct ir3_shader_variant *fs,
904 bool binning_pass)
905 {
906 uint32_t interp_modes[8] = { 0 };
907 uint32_t ps_repl_modes[8] = { 0 };
908
909 if (!binning_pass) {
910 for (int i = -1;
911 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
912
913 /* get the mode for input i */
914 uint8_t interp_mode;
915 uint8_t ps_repl_mode;
916 const int bits =
917 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
918
919 /* OR the mode into the array */
920 const uint32_t inloc = fs->inputs[i].inloc * 2;
921 uint32_t n = inloc / 32;
922 uint32_t shift = inloc % 32;
923 interp_modes[n] |= interp_mode << shift;
924 ps_repl_modes[n] |= ps_repl_mode << shift;
925 if (shift + bits > 32) {
926 n++;
927 shift = 32 - shift;
928
929 interp_modes[n] |= interp_mode >> shift;
930 ps_repl_modes[n] |= ps_repl_mode >> shift;
931 }
932 }
933 }
934
935 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
936 tu_cs_emit_array(cs, interp_modes, 8);
937
938 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
939 tu_cs_emit_array(cs, ps_repl_modes, 8);
940 }
941
942 static void
943 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
944 {
945 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
946 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
947 uint32_t smask_in_regid;
948
949 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
950 bool enable_varyings = fs->total_in > 0;
951
952 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
953 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
954 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
955 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
956 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
957 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
958 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
959 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
960 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
961
962 if (fs->num_sampler_prefetch > 0) {
963 assert(VALIDREG(ij_pix_regid));
964 /* also, it seems like ij_pix is *required* to be r0.x */
965 assert(ij_pix_regid == regid(0, 0));
966 }
967
968 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
969 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
970 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
971 0x7000); // XXX);
972 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
973 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
974 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
975 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
976 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
977 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
978 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
979 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
980 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
981 }
982
983 if (fs->num_sampler_prefetch > 0) {
984 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
985 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
986 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
987 tu_cs_emit(cs,
988 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
989 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
990 }
991 }
992
993 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
994 tu_cs_emit(cs, 0x7);
995 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
996 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
997 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
998 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
999 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1000 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1001 0xfc00fc00);
1002 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1003 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1004 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1005 0x0000fc00);
1006 tu_cs_emit(cs, 0xfc);
1007
1008 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1009 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1010
1011 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1012 tu_cs_emit(cs, 0xff); /* XXX */
1013
1014 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1015 tu_cs_emit(cs,
1016 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1017 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1018 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1019 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1020 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1021 COND(fs->frag_coord,
1022 A6XX_GRAS_CNTL_SIZE |
1023 A6XX_GRAS_CNTL_XCOORD |
1024 A6XX_GRAS_CNTL_YCOORD |
1025 A6XX_GRAS_CNTL_ZCOORD |
1026 A6XX_GRAS_CNTL_WCOORD) |
1027 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1028
1029 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1030 tu_cs_emit(cs,
1031 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1032 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1033 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1034 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1035 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1036 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1037 COND(fs->frag_coord,
1038 A6XX_RB_RENDER_CONTROL0_SIZE |
1039 A6XX_RB_RENDER_CONTROL0_XCOORD |
1040 A6XX_RB_RENDER_CONTROL0_YCOORD |
1041 A6XX_RB_RENDER_CONTROL0_ZCOORD |
1042 A6XX_RB_RENDER_CONTROL0_WCOORD) |
1043 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1044 tu_cs_emit(cs,
1045 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1046 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1047 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1048 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1049
1050 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1051 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1052
1053 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1054 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1055
1056 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1057 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1058 }
1059
1060 static void
1061 tu6_emit_fs_outputs(struct tu_cs *cs,
1062 const struct ir3_shader_variant *fs,
1063 uint32_t mrt_count)
1064 {
1065 uint32_t smask_regid, posz_regid;
1066
1067 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1068 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1069
1070 uint32_t fragdata_regid[8];
1071 if (fs->color0_mrt) {
1072 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1073 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1074 fragdata_regid[i] = fragdata_regid[0];
1075 } else {
1076 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1077 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1078 }
1079
1080 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1081 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1082 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1083 0xfc000000);
1084 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1085
1086 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1087 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1088 // TODO we could have a mix of half and full precision outputs,
1089 // we really need to figure out half-precision from IR3_REG_HALF
1090 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1091 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1092 }
1093
1094 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1095 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1096 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
1097 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1098
1099 uint32_t gras_su_depth_plane_cntl = 0;
1100 uint32_t rb_depth_plane_cntl = 0;
1101 if (fs->no_earlyz || fs->writes_pos) {
1102 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1103 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1104 }
1105
1106 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1107 tu_cs_emit(cs, gras_su_depth_plane_cntl);
1108
1109 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1110 tu_cs_emit(cs, rb_depth_plane_cntl);
1111 }
1112
1113 static void
1114 tu6_emit_shader_object(struct tu_cs *cs,
1115 gl_shader_stage stage,
1116 const struct ir3_shader_variant *variant,
1117 const struct tu_bo *binary_bo,
1118 uint32_t binary_offset)
1119 {
1120 uint16_t reg;
1121 uint8_t opcode;
1122 enum a6xx_state_block sb;
1123 switch (stage) {
1124 case MESA_SHADER_VERTEX:
1125 reg = REG_A6XX_SP_VS_OBJ_START_LO;
1126 opcode = CP_LOAD_STATE6_GEOM;
1127 sb = SB6_VS_SHADER;
1128 break;
1129 case MESA_SHADER_TESS_CTRL:
1130 reg = REG_A6XX_SP_HS_OBJ_START_LO;
1131 opcode = CP_LOAD_STATE6_GEOM;
1132 sb = SB6_HS_SHADER;
1133 break;
1134 case MESA_SHADER_TESS_EVAL:
1135 reg = REG_A6XX_SP_DS_OBJ_START_LO;
1136 opcode = CP_LOAD_STATE6_GEOM;
1137 sb = SB6_DS_SHADER;
1138 break;
1139 case MESA_SHADER_GEOMETRY:
1140 reg = REG_A6XX_SP_GS_OBJ_START_LO;
1141 opcode = CP_LOAD_STATE6_GEOM;
1142 sb = SB6_GS_SHADER;
1143 break;
1144 case MESA_SHADER_FRAGMENT:
1145 reg = REG_A6XX_SP_FS_OBJ_START_LO;
1146 opcode = CP_LOAD_STATE6_FRAG;
1147 sb = SB6_FS_SHADER;
1148 break;
1149 case MESA_SHADER_COMPUTE:
1150 reg = REG_A6XX_SP_CS_OBJ_START_LO;
1151 opcode = CP_LOAD_STATE6_FRAG;
1152 sb = SB6_CS_SHADER;
1153 break;
1154 default:
1155 unreachable("invalid gl_shader_stage");
1156 opcode = CP_LOAD_STATE6_GEOM;
1157 sb = SB6_VS_SHADER;
1158 break;
1159 }
1160
1161 if (!variant->instrlen) {
1162 tu_cs_emit_pkt4(cs, reg, 2);
1163 tu_cs_emit_qw(cs, 0);
1164 return;
1165 }
1166
1167 assert(variant->type == stage);
1168
1169 const uint64_t binary_iova = binary_bo->iova + binary_offset;
1170 assert((binary_iova & 0xf) == 0);
1171 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1172 * of the shader. this could be a potential source of problems at some point
1173 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1174 */
1175
1176 tu_cs_emit_pkt4(cs, reg, 2);
1177 tu_cs_emit_qw(cs, binary_iova);
1178
1179 /* always indirect */
1180 const bool indirect = true;
1181 if (indirect) {
1182 tu_cs_emit_pkt7(cs, opcode, 3);
1183 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1184 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1185 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1186 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1187 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1188 tu_cs_emit_qw(cs, binary_iova);
1189 } else {
1190 const void *binary = binary_bo->map + binary_offset;
1191
1192 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
1193 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1194 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1195 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1196 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1197 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1198 tu_cs_emit_qw(cs, 0);
1199 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
1200 }
1201 }
1202
1203 static void
1204 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
1205 uint32_t opcode, enum a6xx_state_block block)
1206 {
1207 /* dummy variant */
1208 if (!v->shader)
1209 return;
1210
1211 const struct ir3_const_state *const_state = &v->shader->const_state;
1212 uint32_t base = const_state->offsets.immediate;
1213 int size = const_state->immediates_count;
1214
1215 /* truncate size to avoid writing constants that shader
1216 * does not use:
1217 */
1218 size = MIN2(size + base, v->constlen) - base;
1219
1220 if (size <= 0)
1221 return;
1222
1223 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1224 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1225 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1226 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1227 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1228 CP_LOAD_STATE6_0_NUM_UNIT(size));
1229 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1230 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1231
1232 for (unsigned i = 0; i < size; i++) {
1233 tu_cs_emit(cs, const_state->immediates[i].val[0]);
1234 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1235 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1236 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1237 }
1238 }
1239
1240 static void
1241 tu6_emit_geometry_consts(struct tu_cs *cs,
1242 const struct ir3_shader_variant *vs,
1243 const struct ir3_shader_variant *gs) {
1244 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1245
1246 uint32_t params[4] = {
1247 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1248 vs->shader->output_size * 4, /* vertex stride */
1249 0,
1250 0,
1251 };
1252 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1253 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1254 ARRAY_SIZE(params), params);
1255
1256 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1257 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1258 ARRAY_SIZE(params), params);
1259 }
1260
1261 static void
1262 tu6_emit_program(struct tu_cs *cs,
1263 const struct tu_pipeline_builder *builder,
1264 const struct tu_bo *binary_bo,
1265 bool binning_pass,
1266 struct tu_streamout_state *tf)
1267 {
1268 static const struct ir3_shader_variant dummy_variant = {
1269 .type = MESA_SHADER_NONE
1270 };
1271 assert(builder->shaders[MESA_SHADER_VERTEX]);
1272 const struct ir3_shader_variant *vs =
1273 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1274 const struct ir3_shader_variant *hs =
1275 builder->shaders[MESA_SHADER_TESS_CTRL]
1276 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1277 : &dummy_variant;
1278 const struct ir3_shader_variant *ds =
1279 builder->shaders[MESA_SHADER_TESS_EVAL]
1280 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1281 : &dummy_variant;
1282 const struct ir3_shader_variant *gs =
1283 builder->shaders[MESA_SHADER_GEOMETRY]
1284 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1285 : &dummy_variant;
1286 const struct ir3_shader_variant *fs =
1287 builder->shaders[MESA_SHADER_FRAGMENT]
1288 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1289 : &dummy_variant;
1290 bool has_gs = gs->type != MESA_SHADER_NONE;
1291
1292 if (binning_pass) {
1293 /* if we have streamout, use full VS in binning pass, as the
1294 * binning pass VS will have outputs on other than position/psize
1295 * stripped out:
1296 */
1297 if (vs->shader->stream_output.num_outputs == 0)
1298 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1299 fs = &dummy_variant;
1300 }
1301
1302 tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1303 tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1304 tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1305 tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1306 tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1307
1308 tu6_emit_vs_system_values(cs, vs, gs);
1309 tu6_emit_vpc(cs, vs, gs, fs, binning_pass, tf);
1310 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1311 tu6_emit_fs_inputs(cs, fs);
1312 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1313
1314 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1315 binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1316 if (has_gs)
1317 tu6_emit_shader_object(cs, MESA_SHADER_GEOMETRY, gs, binary_bo,
1318 builder->shader_offsets[MESA_SHADER_GEOMETRY]);
1319 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1320 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1321
1322 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1323 if (has_gs) {
1324 tu6_emit_immediates(cs, gs, CP_LOAD_STATE6_GEOM, SB6_GS_SHADER);
1325 tu6_emit_geometry_consts(cs, vs, gs);
1326 }
1327 if (!binning_pass)
1328 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1329 }
1330
1331 static void
1332 tu6_emit_vertex_input(struct tu_cs *cs,
1333 const struct ir3_shader_variant *vs,
1334 const VkPipelineVertexInputStateCreateInfo *info,
1335 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1336 uint32_t *count)
1337 {
1338 uint32_t vfd_fetch_idx = 0;
1339 uint32_t vfd_decode_idx = 0;
1340 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1341
1342 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1343 const VkVertexInputBindingDescription *binding =
1344 &info->pVertexBindingDescriptions[i];
1345
1346 tu_cs_emit_regs(cs,
1347 A6XX_VFD_FETCH_STRIDE(vfd_fetch_idx, binding->stride));
1348
1349 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1350 binding_instanced |= 1 << binding->binding;
1351
1352 bindings[vfd_fetch_idx] = binding->binding;
1353 vfd_fetch_idx++;
1354 }
1355
1356 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1357
1358 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1359 const VkVertexInputAttributeDescription *attr =
1360 &info->pVertexAttributeDescriptions[i];
1361 uint32_t binding_idx, input_idx;
1362
1363 for (binding_idx = 0; binding_idx < vfd_fetch_idx; binding_idx++) {
1364 if (bindings[binding_idx] == attr->binding)
1365 break;
1366 }
1367 assert(binding_idx < vfd_fetch_idx);
1368
1369 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1370 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1371 break;
1372 }
1373
1374 /* attribute not used, skip it */
1375 if (input_idx == vs->inputs_count)
1376 continue;
1377
1378 const struct tu_native_format format = tu6_format_vtx(attr->format);
1379 tu_cs_emit_regs(cs,
1380 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1381 .idx = binding_idx,
1382 .offset = attr->offset,
1383 .instanced = binding_instanced & (1 << attr->binding),
1384 .format = format.fmt,
1385 .swap = format.swap,
1386 .unk30 = 1,
1387 ._float = !vk_format_is_int(attr->format)),
1388 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1389
1390 tu_cs_emit_regs(cs,
1391 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1392 .writemask = vs->inputs[input_idx].compmask,
1393 .regid = vs->inputs[input_idx].regid));
1394
1395 vfd_decode_idx++;
1396 }
1397
1398 tu_cs_emit_regs(cs,
1399 A6XX_VFD_CONTROL_0(
1400 .fetch_cnt = vfd_fetch_idx,
1401 .decode_cnt = vfd_decode_idx));
1402
1403 *count = vfd_fetch_idx;
1404 }
1405
1406 static uint32_t
1407 tu6_guardband_adj(uint32_t v)
1408 {
1409 if (v > 256)
1410 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1411 else
1412 return 511;
1413 }
1414
1415 void
1416 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1417 {
1418 float offsets[3];
1419 float scales[3];
1420 scales[0] = viewport->width / 2.0f;
1421 scales[1] = viewport->height / 2.0f;
1422 scales[2] = viewport->maxDepth - viewport->minDepth;
1423 offsets[0] = viewport->x + scales[0];
1424 offsets[1] = viewport->y + scales[1];
1425 offsets[2] = viewport->minDepth;
1426
1427 VkOffset2D min;
1428 VkOffset2D max;
1429 min.x = (int32_t) viewport->x;
1430 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1431 if (viewport->height >= 0.0f) {
1432 min.y = (int32_t) viewport->y;
1433 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1434 } else {
1435 min.y = (int32_t)(viewport->y + viewport->height);
1436 max.y = (int32_t) ceilf(viewport->y);
1437 }
1438 /* the spec allows viewport->height to be 0.0f */
1439 if (min.y == max.y)
1440 max.y++;
1441 assert(min.x >= 0 && min.x < max.x);
1442 assert(min.y >= 0 && min.y < max.y);
1443
1444 VkExtent2D guardband_adj;
1445 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1446 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1447
1448 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1449 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1450 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1451 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1452 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1453 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1454 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1455
1456 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1457 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1458 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1459 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1460 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1461
1462 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1463 tu_cs_emit(cs,
1464 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1465 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1466
1467 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1468 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1469
1470 tu_cs_emit_regs(cs,
1471 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1472 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1473
1474 tu_cs_emit_regs(cs,
1475 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1476 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1477 }
1478
1479 void
1480 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1481 {
1482 const VkOffset2D min = scissor->offset;
1483 const VkOffset2D max = {
1484 scissor->offset.x + scissor->extent.width,
1485 scissor->offset.y + scissor->extent.height,
1486 };
1487
1488 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1489 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1490 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1491 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1492 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1493 }
1494
1495 static void
1496 tu6_emit_gras_unknowns(struct tu_cs *cs)
1497 {
1498 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1499 tu_cs_emit(cs, 0x0);
1500 }
1501
1502 static void
1503 tu6_emit_point_size(struct tu_cs *cs)
1504 {
1505 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1506 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1507 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1508 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1509 }
1510
1511 static uint32_t
1512 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1513 VkSampleCountFlagBits samples)
1514 {
1515 uint32_t gras_su_cntl = 0;
1516
1517 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1518 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1519 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1520 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1521
1522 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1523 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1524
1525 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1526
1527 if (rast_info->depthBiasEnable)
1528 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1529
1530 if (samples > VK_SAMPLE_COUNT_1_BIT)
1531 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1532
1533 return gras_su_cntl;
1534 }
1535
1536 void
1537 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1538 uint32_t gras_su_cntl,
1539 float line_width)
1540 {
1541 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1542 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1543
1544 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1545 tu_cs_emit(cs, gras_su_cntl);
1546 }
1547
1548 void
1549 tu6_emit_depth_bias(struct tu_cs *cs,
1550 float constant_factor,
1551 float clamp,
1552 float slope_factor)
1553 {
1554 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1555 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1556 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1557 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1558 }
1559
1560 static void
1561 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1562 {
1563 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1564 tu_cs_emit(cs, 0);
1565 }
1566
1567 static void
1568 tu6_emit_depth_control(struct tu_cs *cs,
1569 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1570 const VkPipelineRasterizationStateCreateInfo *rast_info)
1571 {
1572 assert(!ds_info->depthBoundsTestEnable);
1573
1574 uint32_t rb_depth_cntl = 0;
1575 if (ds_info->depthTestEnable) {
1576 rb_depth_cntl |=
1577 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1578 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1579 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1580
1581 if (rast_info->depthClampEnable)
1582 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1583
1584 if (ds_info->depthWriteEnable)
1585 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1586 }
1587
1588 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1589 tu_cs_emit(cs, rb_depth_cntl);
1590 }
1591
1592 static void
1593 tu6_emit_stencil_control(struct tu_cs *cs,
1594 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1595 {
1596 uint32_t rb_stencil_control = 0;
1597 if (ds_info->stencilTestEnable) {
1598 const VkStencilOpState *front = &ds_info->front;
1599 const VkStencilOpState *back = &ds_info->back;
1600 rb_stencil_control |=
1601 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1602 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1603 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1604 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1605 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1606 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1607 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1608 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1609 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1610 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1611 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1612 }
1613
1614 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1615 tu_cs_emit(cs, rb_stencil_control);
1616 }
1617
1618 void
1619 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1620 {
1621 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1622 tu_cs_emit(
1623 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1624 }
1625
1626 void
1627 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1628 {
1629 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1630 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1631 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1632 }
1633
1634 void
1635 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1636 {
1637 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1638 tu_cs_emit(cs,
1639 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1640 }
1641
1642 static uint32_t
1643 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1644 bool has_alpha)
1645 {
1646 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1647 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1648 has_alpha ? att->srcColorBlendFactor
1649 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1650 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1651 has_alpha ? att->dstColorBlendFactor
1652 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1653 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1654 const enum adreno_rb_blend_factor src_alpha_factor =
1655 tu6_blend_factor(att->srcAlphaBlendFactor);
1656 const enum adreno_rb_blend_factor dst_alpha_factor =
1657 tu6_blend_factor(att->dstAlphaBlendFactor);
1658
1659 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1660 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1661 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1662 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1663 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1664 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1665 }
1666
1667 static uint32_t
1668 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1669 uint32_t rb_mrt_control_rop,
1670 bool is_int,
1671 bool has_alpha)
1672 {
1673 uint32_t rb_mrt_control =
1674 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1675
1676 /* ignore blending and logic op for integer attachments */
1677 if (is_int) {
1678 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1679 return rb_mrt_control;
1680 }
1681
1682 rb_mrt_control |= rb_mrt_control_rop;
1683
1684 if (att->blendEnable) {
1685 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1686
1687 if (has_alpha)
1688 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1689 }
1690
1691 return rb_mrt_control;
1692 }
1693
1694 static void
1695 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1696 const VkPipelineColorBlendStateCreateInfo *blend_info,
1697 const VkFormat attachment_formats[MAX_RTS],
1698 uint32_t *blend_enable_mask)
1699 {
1700 *blend_enable_mask = 0;
1701
1702 bool rop_reads_dst = false;
1703 uint32_t rb_mrt_control_rop = 0;
1704 if (blend_info->logicOpEnable) {
1705 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1706 rb_mrt_control_rop =
1707 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1708 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1709 }
1710
1711 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1712 const VkPipelineColorBlendAttachmentState *att =
1713 &blend_info->pAttachments[i];
1714 const VkFormat format = attachment_formats[i];
1715
1716 uint32_t rb_mrt_control = 0;
1717 uint32_t rb_mrt_blend_control = 0;
1718 if (format != VK_FORMAT_UNDEFINED) {
1719 const bool is_int = vk_format_is_int(format);
1720 const bool has_alpha = vk_format_has_alpha(format);
1721
1722 rb_mrt_control =
1723 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1724 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1725
1726 if (att->blendEnable || rop_reads_dst)
1727 *blend_enable_mask |= 1 << i;
1728 }
1729
1730 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1731 tu_cs_emit(cs, rb_mrt_control);
1732 tu_cs_emit(cs, rb_mrt_blend_control);
1733 }
1734 }
1735
1736 static void
1737 tu6_emit_blend_control(struct tu_cs *cs,
1738 uint32_t blend_enable_mask,
1739 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1740 {
1741 assert(!msaa_info->alphaToOneEnable);
1742
1743 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1744 if (blend_enable_mask)
1745 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1746 if (msaa_info->alphaToCoverageEnable)
1747 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1748
1749 const uint32_t sample_mask =
1750 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1751 : ((1 << msaa_info->rasterizationSamples) - 1);
1752
1753 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1754 uint32_t rb_blend_cntl =
1755 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1756 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1757 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1758 if (msaa_info->alphaToCoverageEnable)
1759 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1760
1761 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1762 tu_cs_emit(cs, sp_blend_cntl);
1763
1764 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1765 tu_cs_emit(cs, rb_blend_cntl);
1766 }
1767
1768 void
1769 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1770 {
1771 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1772 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1773 }
1774
1775 static VkResult
1776 tu_pipeline_create(struct tu_device *dev,
1777 const VkAllocationCallbacks *pAllocator,
1778 struct tu_pipeline **out_pipeline)
1779 {
1780 struct tu_pipeline *pipeline =
1781 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
1782 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1783 if (!pipeline)
1784 return VK_ERROR_OUT_OF_HOST_MEMORY;
1785
1786 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
1787
1788 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1789 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048);
1790 if (result != VK_SUCCESS) {
1791 vk_free2(&dev->alloc, pAllocator, pipeline);
1792 return result;
1793 }
1794
1795 *out_pipeline = pipeline;
1796
1797 return VK_SUCCESS;
1798 }
1799
1800 static VkResult
1801 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1802 {
1803 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1804 NULL
1805 };
1806 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1807 gl_shader_stage stage =
1808 tu_shader_stage(builder->create_info->pStages[i].stage);
1809 stage_infos[stage] = &builder->create_info->pStages[i];
1810 }
1811
1812 struct tu_shader_compile_options options;
1813 tu_shader_compile_options_init(&options, builder->create_info);
1814
1815 /* compile shaders in reverse order */
1816 struct tu_shader *next_stage_shader = NULL;
1817 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1818 stage > MESA_SHADER_NONE; stage--) {
1819 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1820 if (!stage_info)
1821 continue;
1822
1823 struct tu_shader *shader =
1824 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1825 builder->alloc);
1826 if (!shader)
1827 return VK_ERROR_OUT_OF_HOST_MEMORY;
1828
1829 VkResult result =
1830 tu_shader_compile(builder->device, shader, next_stage_shader,
1831 &options, builder->alloc);
1832 if (result != VK_SUCCESS)
1833 return result;
1834
1835 builder->shaders[stage] = shader;
1836 builder->shader_offsets[stage] = builder->shader_total_size;
1837 builder->shader_total_size +=
1838 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1839
1840 next_stage_shader = shader;
1841 }
1842
1843 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1844 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1845 const struct ir3_shader_variant *variant;
1846
1847 if (vs->ir3_shader.stream_output.num_outputs)
1848 variant = &vs->variants[0];
1849 else
1850 variant = &vs->variants[1];
1851
1852 builder->binning_vs_offset = builder->shader_total_size;
1853 builder->shader_total_size +=
1854 sizeof(uint32_t) * variant->info.sizedwords;
1855 }
1856
1857 return VK_SUCCESS;
1858 }
1859
1860 static VkResult
1861 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1862 struct tu_pipeline *pipeline)
1863 {
1864 struct tu_bo *bo = &pipeline->program.binary_bo;
1865
1866 VkResult result =
1867 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1868 if (result != VK_SUCCESS)
1869 return result;
1870
1871 result = tu_bo_map(builder->device, bo);
1872 if (result != VK_SUCCESS)
1873 return result;
1874
1875 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1876 const struct tu_shader *shader = builder->shaders[i];
1877 if (!shader)
1878 continue;
1879
1880 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1881 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1882 }
1883
1884 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1885 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1886 const struct ir3_shader_variant *variant;
1887 void *bin;
1888
1889 if (vs->ir3_shader.stream_output.num_outputs) {
1890 variant = &vs->variants[0];
1891 bin = vs->binary;
1892 } else {
1893 variant = &vs->variants[1];
1894 bin = vs->binning_binary;
1895 }
1896
1897 memcpy(bo->map + builder->binning_vs_offset, bin,
1898 sizeof(uint32_t) * variant->info.sizedwords);
1899 }
1900
1901 return VK_SUCCESS;
1902 }
1903
1904 static void
1905 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1906 struct tu_pipeline *pipeline)
1907 {
1908 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1909 builder->create_info->pDynamicState;
1910
1911 if (!dynamic_info)
1912 return;
1913
1914 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1915 pipeline->dynamic_state.mask |=
1916 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1917 }
1918 }
1919
1920 static void
1921 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
1922 struct tu_shader *shader,
1923 struct ir3_shader_variant *v)
1924 {
1925 link->ubo_state = v->shader->ubo_state;
1926 link->const_state = v->shader->const_state;
1927 link->constlen = v->constlen;
1928 link->push_consts = shader->push_consts;
1929 }
1930
1931 static void
1932 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1933 struct tu_pipeline *pipeline)
1934 {
1935 struct tu_cs prog_cs;
1936 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
1937 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
1938 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1939
1940 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
1941 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
1942 pipeline->program.binning_state_ib =
1943 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1944
1945 VkShaderStageFlags stages = 0;
1946 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
1947 stages |= builder->create_info->pStages[i].stage;
1948 }
1949 pipeline->active_stages = stages;
1950
1951 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1952 if (!builder->shaders[i])
1953 continue;
1954
1955 tu_pipeline_set_linkage(&pipeline->program.link[i],
1956 builder->shaders[i],
1957 &builder->shaders[i]->variants[0]);
1958 }
1959
1960 if (builder->shaders[MESA_SHADER_FRAGMENT]) {
1961 memcpy(pipeline->program.input_attachment_idx,
1962 builder->shaders[MESA_SHADER_FRAGMENT]->attachment_idx,
1963 sizeof(pipeline->program.input_attachment_idx));
1964 }
1965 }
1966
1967 static void
1968 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1969 struct tu_pipeline *pipeline)
1970 {
1971 const VkPipelineVertexInputStateCreateInfo *vi_info =
1972 builder->create_info->pVertexInputState;
1973 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1974
1975 struct tu_cs vi_cs;
1976 tu_cs_begin_sub_stream(&pipeline->cs,
1977 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
1978 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1979 pipeline->vi.bindings, &pipeline->vi.count);
1980 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1981
1982 if (vs->has_binning_pass) {
1983 tu_cs_begin_sub_stream(&pipeline->cs,
1984 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
1985 tu6_emit_vertex_input(
1986 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1987 &pipeline->vi.binning_count);
1988 pipeline->vi.binning_state_ib =
1989 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1990 }
1991 }
1992
1993 static void
1994 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1995 struct tu_pipeline *pipeline)
1996 {
1997 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1998 builder->create_info->pInputAssemblyState;
1999
2000 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2001 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2002 }
2003
2004 static void
2005 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2006 struct tu_pipeline *pipeline)
2007 {
2008 /* The spec says:
2009 *
2010 * pViewportState is a pointer to an instance of the
2011 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2012 * pipeline has rasterization disabled."
2013 *
2014 * We leave the relevant registers stale in that case.
2015 */
2016 if (builder->rasterizer_discard)
2017 return;
2018
2019 const VkPipelineViewportStateCreateInfo *vp_info =
2020 builder->create_info->pViewportState;
2021
2022 struct tu_cs vp_cs;
2023 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
2024
2025 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2026 assert(vp_info->viewportCount == 1);
2027 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
2028 }
2029
2030 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2031 assert(vp_info->scissorCount == 1);
2032 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
2033 }
2034
2035 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
2036 }
2037
2038 static void
2039 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2040 struct tu_pipeline *pipeline)
2041 {
2042 const VkPipelineRasterizationStateCreateInfo *rast_info =
2043 builder->create_info->pRasterizationState;
2044
2045 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2046
2047 struct tu_cs rast_cs;
2048 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
2049
2050
2051 tu_cs_emit_regs(&rast_cs,
2052 A6XX_GRAS_CL_CNTL(
2053 .znear_clip_disable = rast_info->depthClampEnable,
2054 .zfar_clip_disable = rast_info->depthClampEnable,
2055 .unk5 = rast_info->depthClampEnable,
2056 .zero_gb_scale_z = 1,
2057 .vp_clip_code_ignore = 1));
2058 /* move to hw ctx init? */
2059 tu6_emit_gras_unknowns(&rast_cs);
2060 tu6_emit_point_size(&rast_cs);
2061
2062 const uint32_t gras_su_cntl =
2063 tu6_gras_su_cntl(rast_info, builder->samples);
2064
2065 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
2066 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
2067
2068 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
2069 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
2070 rast_info->depthBiasClamp,
2071 rast_info->depthBiasSlopeFactor);
2072 }
2073
2074 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
2075
2076 pipeline->rast.gras_su_cntl = gras_su_cntl;
2077 }
2078
2079 static void
2080 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2081 struct tu_pipeline *pipeline)
2082 {
2083 /* The spec says:
2084 *
2085 * pDepthStencilState is a pointer to an instance of the
2086 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2087 * the pipeline has rasterization disabled or if the subpass of the
2088 * render pass the pipeline is created against does not use a
2089 * depth/stencil attachment.
2090 *
2091 * We disable both depth and stenil tests in those cases.
2092 */
2093 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2094 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2095 builder->use_depth_stencil_attachment
2096 ? builder->create_info->pDepthStencilState
2097 : &dummy_ds_info;
2098
2099 struct tu_cs ds_cs;
2100 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2101
2102 /* move to hw ctx init? */
2103 tu6_emit_alpha_control_disable(&ds_cs);
2104
2105 tu6_emit_depth_control(&ds_cs, ds_info, builder->create_info->pRasterizationState);
2106 tu6_emit_stencil_control(&ds_cs, ds_info);
2107
2108 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2109 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2110 ds_info->back.compareMask);
2111 }
2112 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2113 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2114 ds_info->back.writeMask);
2115 }
2116 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2117 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2118 ds_info->back.reference);
2119 }
2120
2121 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2122 }
2123
2124 static void
2125 tu_pipeline_builder_parse_multisample_and_color_blend(
2126 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2127 {
2128 /* The spec says:
2129 *
2130 * pMultisampleState is a pointer to an instance of the
2131 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2132 * has rasterization disabled.
2133 *
2134 * Also,
2135 *
2136 * pColorBlendState is a pointer to an instance of the
2137 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2138 * pipeline has rasterization disabled or if the subpass of the render
2139 * pass the pipeline is created against does not use any color
2140 * attachments.
2141 *
2142 * We leave the relevant registers stale when rasterization is disabled.
2143 */
2144 if (builder->rasterizer_discard)
2145 return;
2146
2147 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2148 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2149 builder->create_info->pMultisampleState;
2150 const VkPipelineColorBlendStateCreateInfo *blend_info =
2151 builder->use_color_attachments ? builder->create_info->pColorBlendState
2152 : &dummy_blend_info;
2153
2154 struct tu_cs blend_cs;
2155 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 9, &blend_cs);
2156
2157 uint32_t blend_enable_mask;
2158 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2159 builder->color_attachment_formats,
2160 &blend_enable_mask);
2161
2162 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2163 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2164
2165 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
2166
2167 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2168 }
2169
2170 static void
2171 tu_pipeline_finish(struct tu_pipeline *pipeline,
2172 struct tu_device *dev,
2173 const VkAllocationCallbacks *alloc)
2174 {
2175 tu_cs_finish(&pipeline->cs);
2176
2177 if (pipeline->program.binary_bo.gem_handle)
2178 tu_bo_finish(dev, &pipeline->program.binary_bo);
2179 }
2180
2181 static VkResult
2182 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2183 struct tu_pipeline **pipeline)
2184 {
2185 VkResult result = tu_pipeline_create(builder->device, builder->alloc,
2186 pipeline);
2187 if (result != VK_SUCCESS)
2188 return result;
2189
2190 (*pipeline)->layout = builder->layout;
2191
2192 /* compile and upload shaders */
2193 result = tu_pipeline_builder_compile_shaders(builder);
2194 if (result == VK_SUCCESS)
2195 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2196 if (result != VK_SUCCESS) {
2197 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2198 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2199 *pipeline = VK_NULL_HANDLE;
2200
2201 return result;
2202 }
2203
2204 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2205 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2206 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2207 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2208 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2209 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2210 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2211 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2212
2213 /* we should have reserved enough space upfront such that the CS never
2214 * grows
2215 */
2216 assert((*pipeline)->cs.bo_count == 1);
2217
2218 return VK_SUCCESS;
2219 }
2220
2221 static void
2222 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2223 {
2224 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2225 if (!builder->shaders[i])
2226 continue;
2227 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2228 }
2229 }
2230
2231 static void
2232 tu_pipeline_builder_init_graphics(
2233 struct tu_pipeline_builder *builder,
2234 struct tu_device *dev,
2235 struct tu_pipeline_cache *cache,
2236 const VkGraphicsPipelineCreateInfo *create_info,
2237 const VkAllocationCallbacks *alloc)
2238 {
2239 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2240
2241 *builder = (struct tu_pipeline_builder) {
2242 .device = dev,
2243 .cache = cache,
2244 .create_info = create_info,
2245 .alloc = alloc,
2246 .layout = layout,
2247 };
2248
2249 builder->rasterizer_discard =
2250 create_info->pRasterizationState->rasterizerDiscardEnable;
2251
2252 if (builder->rasterizer_discard) {
2253 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2254 } else {
2255 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2256
2257 const struct tu_render_pass *pass =
2258 tu_render_pass_from_handle(create_info->renderPass);
2259 const struct tu_subpass *subpass =
2260 &pass->subpasses[create_info->subpass];
2261
2262 builder->use_depth_stencil_attachment =
2263 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
2264
2265 assert(subpass->color_count == 0 ||
2266 !create_info->pColorBlendState ||
2267 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2268 builder->color_attachment_count = subpass->color_count;
2269 for (uint32_t i = 0; i < subpass->color_count; i++) {
2270 const uint32_t a = subpass->color_attachments[i].attachment;
2271 if (a == VK_ATTACHMENT_UNUSED)
2272 continue;
2273
2274 builder->color_attachment_formats[i] = pass->attachments[a].format;
2275 builder->use_color_attachments = true;
2276 }
2277 }
2278 }
2279
2280 static VkResult
2281 tu_graphics_pipeline_create(VkDevice device,
2282 VkPipelineCache pipelineCache,
2283 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2284 const VkAllocationCallbacks *pAllocator,
2285 VkPipeline *pPipeline)
2286 {
2287 TU_FROM_HANDLE(tu_device, dev, device);
2288 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2289
2290 struct tu_pipeline_builder builder;
2291 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2292 pCreateInfo, pAllocator);
2293
2294 struct tu_pipeline *pipeline = NULL;
2295 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2296 tu_pipeline_builder_finish(&builder);
2297
2298 if (result == VK_SUCCESS)
2299 *pPipeline = tu_pipeline_to_handle(pipeline);
2300 else
2301 *pPipeline = VK_NULL_HANDLE;
2302
2303 return result;
2304 }
2305
2306 VkResult
2307 tu_CreateGraphicsPipelines(VkDevice device,
2308 VkPipelineCache pipelineCache,
2309 uint32_t count,
2310 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2311 const VkAllocationCallbacks *pAllocator,
2312 VkPipeline *pPipelines)
2313 {
2314 VkResult final_result = VK_SUCCESS;
2315
2316 for (uint32_t i = 0; i < count; i++) {
2317 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2318 &pCreateInfos[i], pAllocator,
2319 &pPipelines[i]);
2320
2321 if (result != VK_SUCCESS)
2322 final_result = result;
2323 }
2324
2325 return final_result;
2326 }
2327
2328 static void
2329 tu6_emit_compute_program(struct tu_cs *cs,
2330 struct tu_shader *shader,
2331 const struct tu_bo *binary_bo)
2332 {
2333 const struct ir3_shader_variant *v = &shader->variants[0];
2334
2335 tu6_emit_cs_config(cs, shader, v);
2336
2337 /* The compute program is the only one in the pipeline, so 0 offset. */
2338 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2339
2340 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2341 }
2342
2343 static VkResult
2344 tu_compute_upload_shader(VkDevice device,
2345 struct tu_pipeline *pipeline,
2346 struct tu_shader *shader)
2347 {
2348 TU_FROM_HANDLE(tu_device, dev, device);
2349 struct tu_bo *bo = &pipeline->program.binary_bo;
2350 struct ir3_shader_variant *v = &shader->variants[0];
2351
2352 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2353 VkResult result =
2354 tu_bo_init_new(dev, bo, shader_size);
2355 if (result != VK_SUCCESS)
2356 return result;
2357
2358 result = tu_bo_map(dev, bo);
2359 if (result != VK_SUCCESS)
2360 return result;
2361
2362 memcpy(bo->map, shader->binary, shader_size);
2363
2364 return VK_SUCCESS;
2365 }
2366
2367
2368 static VkResult
2369 tu_compute_pipeline_create(VkDevice device,
2370 VkPipelineCache _cache,
2371 const VkComputePipelineCreateInfo *pCreateInfo,
2372 const VkAllocationCallbacks *pAllocator,
2373 VkPipeline *pPipeline)
2374 {
2375 TU_FROM_HANDLE(tu_device, dev, device);
2376 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2377 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2378 VkResult result;
2379
2380 struct tu_pipeline *pipeline;
2381
2382 *pPipeline = VK_NULL_HANDLE;
2383
2384 result = tu_pipeline_create(dev, pAllocator, &pipeline);
2385 if (result != VK_SUCCESS)
2386 return result;
2387
2388 pipeline->layout = layout;
2389
2390 struct tu_shader_compile_options options;
2391 tu_shader_compile_options_init(&options, NULL);
2392
2393 struct tu_shader *shader =
2394 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2395 if (!shader) {
2396 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2397 goto fail;
2398 }
2399
2400 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2401 if (result != VK_SUCCESS)
2402 goto fail;
2403
2404 struct ir3_shader_variant *v = &shader->variants[0];
2405
2406 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2407 shader, v);
2408
2409 result = tu_compute_upload_shader(device, pipeline, shader);
2410 if (result != VK_SUCCESS)
2411 goto fail;
2412
2413 for (int i = 0; i < 3; i++)
2414 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2415
2416 struct tu_cs prog_cs;
2417 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2418 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2419 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2420
2421 *pPipeline = tu_pipeline_to_handle(pipeline);
2422 return VK_SUCCESS;
2423
2424 fail:
2425 if (shader)
2426 tu_shader_destroy(dev, shader, pAllocator);
2427
2428 tu_pipeline_finish(pipeline, dev, pAllocator);
2429 vk_free2(&dev->alloc, pAllocator, pipeline);
2430
2431 return result;
2432 }
2433
2434 VkResult
2435 tu_CreateComputePipelines(VkDevice device,
2436 VkPipelineCache pipelineCache,
2437 uint32_t count,
2438 const VkComputePipelineCreateInfo *pCreateInfos,
2439 const VkAllocationCallbacks *pAllocator,
2440 VkPipeline *pPipelines)
2441 {
2442 VkResult final_result = VK_SUCCESS;
2443
2444 for (uint32_t i = 0; i < count; i++) {
2445 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2446 &pCreateInfos[i],
2447 pAllocator, &pPipelines[i]);
2448 if (result != VK_SUCCESS)
2449 final_result = result;
2450 }
2451
2452 return final_result;
2453 }
2454
2455 void
2456 tu_DestroyPipeline(VkDevice _device,
2457 VkPipeline _pipeline,
2458 const VkAllocationCallbacks *pAllocator)
2459 {
2460 TU_FROM_HANDLE(tu_device, dev, _device);
2461 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2462
2463 if (!_pipeline)
2464 return;
2465
2466 tu_pipeline_finish(pipeline, dev, pAllocator);
2467 vk_free2(&dev->alloc, pAllocator, pipeline);
2468 }