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[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 uint32_t
44 tu6_stage2opcode(gl_shader_stage stage)
45 {
46 if (stage == MESA_SHADER_FRAGMENT || stage == MESA_SHADER_COMPUTE)
47 return CP_LOAD_STATE6_FRAG;
48 return CP_LOAD_STATE6_GEOM;
49 }
50
51 static enum a6xx_state_block
52 tu6_stage2texsb(gl_shader_stage stage)
53 {
54 return SB6_VS_TEX + stage;
55 }
56
57 enum a6xx_state_block
58 tu6_stage2shadersb(gl_shader_stage stage)
59 {
60 return SB6_VS_SHADER + stage;
61 }
62
63 /* Emit IB that preloads the descriptors that the shader uses */
64
65 static void
66 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
67 enum a6xx_state_block sb, unsigned base, unsigned offset,
68 unsigned count)
69 {
70 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
71 * clear if emitting more packets will even help anything. Presumably the
72 * descriptor cache is relatively small, and these packets stop doing
73 * anything when there are too many descriptors.
74 */
75 tu_cs_emit_pkt7(cs, opcode, 3);
76 tu_cs_emit(cs,
77 CP_LOAD_STATE6_0_STATE_TYPE(st) |
78 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
79 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
80 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
81 tu_cs_emit_qw(cs, offset | (base << 28));
82 }
83
84 static unsigned
85 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
86 {
87 const unsigned load_state_size = 4;
88 unsigned size = 0;
89 for (unsigned i = 0; i < layout->num_sets; i++) {
90 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
91 for (unsigned j = 0; j < set_layout->binding_count; j++) {
92 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
93 unsigned count = 0;
94 /* Note: some users, like amber for example, pass in
95 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
96 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
97 */
98 VkShaderStageFlags stages = compute ?
99 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
100 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
101 unsigned stage_count = util_bitcount(stages);
102 switch (binding->type) {
103 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
104 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
105 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
106 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
107 /* IBO-backed resources only need one packet for all graphics stages */
108 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
109 count += 1;
110 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
111 count += 1;
112 break;
113 case VK_DESCRIPTOR_TYPE_SAMPLER:
114 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
115 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
116 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
117 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
118 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
119 /* Textures and UBO's needs a packet for each stage */
120 count = stage_count;
121 break;
122 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
123 /* Because of how we pack combined images and samplers, we
124 * currently can't use one packet for the whole array.
125 */
126 count = stage_count * binding->array_size * 2;
127 break;
128 default:
129 unreachable("bad descriptor type");
130 }
131 size += count * load_state_size;
132 }
133 }
134 return size;
135 }
136
137 static void
138 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
139 {
140 unsigned size = tu6_load_state_size(pipeline->layout, compute);
141 if (size == 0)
142 return;
143
144 struct tu_cs cs;
145 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
146
147 struct tu_pipeline_layout *layout = pipeline->layout;
148 for (unsigned i = 0; i < layout->num_sets; i++) {
149 /* From 13.2.7. Descriptor Set Binding:
150 *
151 * A compatible descriptor set must be bound for all set numbers that
152 * any shaders in a pipeline access, at the time that a draw or
153 * dispatch command is recorded to execute using that pipeline.
154 * However, if none of the shaders in a pipeline statically use any
155 * bindings with a particular set number, then no descriptor set need
156 * be bound for that set number, even if the pipeline layout includes
157 * a non-trivial descriptor set layout for that set number.
158 *
159 * This means that descriptor sets unused by the pipeline may have a
160 * garbage or 0 BINDLESS_BASE register, which will cause context faults
161 * when prefetching descriptors from these sets. Skip prefetching for
162 * descriptors from them to avoid this. This is also an optimization,
163 * since these prefetches would be useless.
164 */
165 if (!(pipeline->active_desc_sets & (1u << i)))
166 continue;
167
168 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
169 for (unsigned j = 0; j < set_layout->binding_count; j++) {
170 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
171 unsigned base = i;
172 unsigned offset = binding->offset / 4;
173 /* Note: some users, like amber for example, pass in
174 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
175 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
176 */
177 VkShaderStageFlags stages = compute ?
178 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
179 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
180 unsigned count = binding->array_size;
181 if (count == 0 || stages == 0)
182 continue;
183 switch (binding->type) {
184 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
185 base = MAX_SETS;
186 offset = (layout->set[i].dynamic_offset_start +
187 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
188 /* fallthrough */
189 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
190 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
191 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
192 /* IBO-backed resources only need one packet for all graphics stages */
193 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
194 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
195 base, offset, count);
196 }
197 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
198 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
199 base, offset, count);
200 }
201 break;
202 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
203 /* nothing - input attachment doesn't use bindless */
204 break;
205 case VK_DESCRIPTOR_TYPE_SAMPLER:
206 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
207 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
208 tu_foreach_stage(stage, stages) {
209 emit_load_state(&cs, tu6_stage2opcode(stage),
210 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
211 ST6_SHADER : ST6_CONSTANTS,
212 tu6_stage2texsb(stage), base, offset, count);
213 }
214 break;
215 }
216 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
217 base = MAX_SETS;
218 offset = (layout->set[i].dynamic_offset_start +
219 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
220 /* fallthrough */
221 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
222 tu_foreach_stage(stage, stages) {
223 emit_load_state(&cs, tu6_stage2opcode(stage), ST6_UBO,
224 tu6_stage2shadersb(stage), base, offset, count);
225 }
226 break;
227 }
228 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
229 tu_foreach_stage(stage, stages) {
230 /* TODO: We could emit less CP_LOAD_STATE6 if we used
231 * struct-of-arrays instead of array-of-structs.
232 */
233 for (unsigned i = 0; i < count; i++) {
234 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
235 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
236 emit_load_state(&cs, tu6_stage2opcode(stage),
237 ST6_CONSTANTS, tu6_stage2texsb(stage),
238 base, tex_offset, 1);
239 emit_load_state(&cs, tu6_stage2opcode(stage),
240 ST6_SHADER, tu6_stage2texsb(stage),
241 base, sam_offset, 1);
242 }
243 }
244 break;
245 }
246 default:
247 unreachable("bad descriptor type");
248 }
249 }
250 }
251
252 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
253 }
254
255 struct tu_pipeline_builder
256 {
257 struct tu_device *device;
258 struct tu_pipeline_cache *cache;
259 struct tu_pipeline_layout *layout;
260 const VkAllocationCallbacks *alloc;
261 const VkGraphicsPipelineCreateInfo *create_info;
262
263 struct tu_shader *shaders[MESA_SHADER_STAGES];
264 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
265 struct ir3_shader_variant *binning_variant;
266 uint32_t shader_offsets[MESA_SHADER_STAGES];
267 uint32_t binning_vs_offset;
268 uint32_t shader_total_size;
269
270 bool rasterizer_discard;
271 /* these states are affectd by rasterizer_discard */
272 VkSampleCountFlagBits samples;
273 bool use_color_attachments;
274 bool use_dual_src_blend;
275 uint32_t color_attachment_count;
276 VkFormat color_attachment_formats[MAX_RTS];
277 VkFormat depth_attachment_format;
278 uint32_t render_components;
279 };
280
281 static bool
282 tu_logic_op_reads_dst(VkLogicOp op)
283 {
284 switch (op) {
285 case VK_LOGIC_OP_CLEAR:
286 case VK_LOGIC_OP_COPY:
287 case VK_LOGIC_OP_COPY_INVERTED:
288 case VK_LOGIC_OP_SET:
289 return false;
290 default:
291 return true;
292 }
293 }
294
295 static VkBlendFactor
296 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
297 {
298 /* treat dst alpha as 1.0 and avoid reading it */
299 switch (factor) {
300 case VK_BLEND_FACTOR_DST_ALPHA:
301 return VK_BLEND_FACTOR_ONE;
302 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
303 return VK_BLEND_FACTOR_ZERO;
304 default:
305 return factor;
306 }
307 }
308
309 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
310 {
311 switch (factor) {
312 case VK_BLEND_FACTOR_SRC1_COLOR:
313 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
314 case VK_BLEND_FACTOR_SRC1_ALPHA:
315 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
316 return true;
317 default:
318 return false;
319 }
320 }
321
322 static bool
323 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
324 {
325 if (!info)
326 return false;
327
328 for (unsigned i = 0; i < info->attachmentCount; i++) {
329 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
330 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
331 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
332 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
333 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
334 return true;
335 }
336
337 return false;
338 }
339
340 static enum pc_di_primtype
341 tu6_primtype(VkPrimitiveTopology topology)
342 {
343 switch (topology) {
344 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
345 return DI_PT_POINTLIST;
346 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
347 return DI_PT_LINELIST;
348 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
349 return DI_PT_LINESTRIP;
350 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
351 return DI_PT_TRILIST;
352 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
353 return DI_PT_TRISTRIP;
354 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
355 return DI_PT_TRIFAN;
356 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
357 return DI_PT_LINE_ADJ;
358 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
359 return DI_PT_LINESTRIP_ADJ;
360 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
361 return DI_PT_TRI_ADJ;
362 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
363 return DI_PT_TRISTRIP_ADJ;
364 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
365 default:
366 unreachable("invalid primitive topology");
367 return DI_PT_NONE;
368 }
369 }
370
371 static enum adreno_compare_func
372 tu6_compare_func(VkCompareOp op)
373 {
374 switch (op) {
375 case VK_COMPARE_OP_NEVER:
376 return FUNC_NEVER;
377 case VK_COMPARE_OP_LESS:
378 return FUNC_LESS;
379 case VK_COMPARE_OP_EQUAL:
380 return FUNC_EQUAL;
381 case VK_COMPARE_OP_LESS_OR_EQUAL:
382 return FUNC_LEQUAL;
383 case VK_COMPARE_OP_GREATER:
384 return FUNC_GREATER;
385 case VK_COMPARE_OP_NOT_EQUAL:
386 return FUNC_NOTEQUAL;
387 case VK_COMPARE_OP_GREATER_OR_EQUAL:
388 return FUNC_GEQUAL;
389 case VK_COMPARE_OP_ALWAYS:
390 return FUNC_ALWAYS;
391 default:
392 unreachable("invalid VkCompareOp");
393 return FUNC_NEVER;
394 }
395 }
396
397 static enum adreno_stencil_op
398 tu6_stencil_op(VkStencilOp op)
399 {
400 switch (op) {
401 case VK_STENCIL_OP_KEEP:
402 return STENCIL_KEEP;
403 case VK_STENCIL_OP_ZERO:
404 return STENCIL_ZERO;
405 case VK_STENCIL_OP_REPLACE:
406 return STENCIL_REPLACE;
407 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
408 return STENCIL_INCR_CLAMP;
409 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
410 return STENCIL_DECR_CLAMP;
411 case VK_STENCIL_OP_INVERT:
412 return STENCIL_INVERT;
413 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
414 return STENCIL_INCR_WRAP;
415 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
416 return STENCIL_DECR_WRAP;
417 default:
418 unreachable("invalid VkStencilOp");
419 return STENCIL_KEEP;
420 }
421 }
422
423 static enum a3xx_rop_code
424 tu6_rop(VkLogicOp op)
425 {
426 switch (op) {
427 case VK_LOGIC_OP_CLEAR:
428 return ROP_CLEAR;
429 case VK_LOGIC_OP_AND:
430 return ROP_AND;
431 case VK_LOGIC_OP_AND_REVERSE:
432 return ROP_AND_REVERSE;
433 case VK_LOGIC_OP_COPY:
434 return ROP_COPY;
435 case VK_LOGIC_OP_AND_INVERTED:
436 return ROP_AND_INVERTED;
437 case VK_LOGIC_OP_NO_OP:
438 return ROP_NOOP;
439 case VK_LOGIC_OP_XOR:
440 return ROP_XOR;
441 case VK_LOGIC_OP_OR:
442 return ROP_OR;
443 case VK_LOGIC_OP_NOR:
444 return ROP_NOR;
445 case VK_LOGIC_OP_EQUIVALENT:
446 return ROP_EQUIV;
447 case VK_LOGIC_OP_INVERT:
448 return ROP_INVERT;
449 case VK_LOGIC_OP_OR_REVERSE:
450 return ROP_OR_REVERSE;
451 case VK_LOGIC_OP_COPY_INVERTED:
452 return ROP_COPY_INVERTED;
453 case VK_LOGIC_OP_OR_INVERTED:
454 return ROP_OR_INVERTED;
455 case VK_LOGIC_OP_NAND:
456 return ROP_NAND;
457 case VK_LOGIC_OP_SET:
458 return ROP_SET;
459 default:
460 unreachable("invalid VkLogicOp");
461 return ROP_NOOP;
462 }
463 }
464
465 static enum adreno_rb_blend_factor
466 tu6_blend_factor(VkBlendFactor factor)
467 {
468 switch (factor) {
469 case VK_BLEND_FACTOR_ZERO:
470 return FACTOR_ZERO;
471 case VK_BLEND_FACTOR_ONE:
472 return FACTOR_ONE;
473 case VK_BLEND_FACTOR_SRC_COLOR:
474 return FACTOR_SRC_COLOR;
475 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
476 return FACTOR_ONE_MINUS_SRC_COLOR;
477 case VK_BLEND_FACTOR_DST_COLOR:
478 return FACTOR_DST_COLOR;
479 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
480 return FACTOR_ONE_MINUS_DST_COLOR;
481 case VK_BLEND_FACTOR_SRC_ALPHA:
482 return FACTOR_SRC_ALPHA;
483 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
484 return FACTOR_ONE_MINUS_SRC_ALPHA;
485 case VK_BLEND_FACTOR_DST_ALPHA:
486 return FACTOR_DST_ALPHA;
487 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
488 return FACTOR_ONE_MINUS_DST_ALPHA;
489 case VK_BLEND_FACTOR_CONSTANT_COLOR:
490 return FACTOR_CONSTANT_COLOR;
491 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
492 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
493 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
494 return FACTOR_CONSTANT_ALPHA;
495 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
496 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
497 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
498 return FACTOR_SRC_ALPHA_SATURATE;
499 case VK_BLEND_FACTOR_SRC1_COLOR:
500 return FACTOR_SRC1_COLOR;
501 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
502 return FACTOR_ONE_MINUS_SRC1_COLOR;
503 case VK_BLEND_FACTOR_SRC1_ALPHA:
504 return FACTOR_SRC1_ALPHA;
505 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
506 return FACTOR_ONE_MINUS_SRC1_ALPHA;
507 default:
508 unreachable("invalid VkBlendFactor");
509 return FACTOR_ZERO;
510 }
511 }
512
513 static enum a3xx_rb_blend_opcode
514 tu6_blend_op(VkBlendOp op)
515 {
516 switch (op) {
517 case VK_BLEND_OP_ADD:
518 return BLEND_DST_PLUS_SRC;
519 case VK_BLEND_OP_SUBTRACT:
520 return BLEND_SRC_MINUS_DST;
521 case VK_BLEND_OP_REVERSE_SUBTRACT:
522 return BLEND_DST_MINUS_SRC;
523 case VK_BLEND_OP_MIN:
524 return BLEND_MIN_DST_SRC;
525 case VK_BLEND_OP_MAX:
526 return BLEND_MAX_DST_SRC;
527 default:
528 unreachable("invalid VkBlendOp");
529 return BLEND_DST_PLUS_SRC;
530 }
531 }
532
533 void
534 tu6_emit_xs_config(struct tu_cs *cs,
535 gl_shader_stage stage, /* xs->type, but xs may be NULL */
536 const struct ir3_shader_variant *xs,
537 uint64_t binary_iova)
538 {
539 static const struct xs_config {
540 uint16_t reg_sp_xs_ctrl;
541 uint16_t reg_sp_xs_config;
542 uint16_t reg_hlsq_xs_ctrl;
543 uint16_t reg_sp_vs_obj_start;
544 } xs_config[] = {
545 [MESA_SHADER_VERTEX] = {
546 REG_A6XX_SP_VS_CTRL_REG0,
547 REG_A6XX_SP_VS_CONFIG,
548 REG_A6XX_HLSQ_VS_CNTL,
549 REG_A6XX_SP_VS_OBJ_START_LO,
550 },
551 [MESA_SHADER_TESS_CTRL] = {
552 REG_A6XX_SP_HS_CTRL_REG0,
553 REG_A6XX_SP_HS_CONFIG,
554 REG_A6XX_HLSQ_HS_CNTL,
555 REG_A6XX_SP_HS_OBJ_START_LO,
556 },
557 [MESA_SHADER_TESS_EVAL] = {
558 REG_A6XX_SP_DS_CTRL_REG0,
559 REG_A6XX_SP_DS_CONFIG,
560 REG_A6XX_HLSQ_DS_CNTL,
561 REG_A6XX_SP_DS_OBJ_START_LO,
562 },
563 [MESA_SHADER_GEOMETRY] = {
564 REG_A6XX_SP_GS_CTRL_REG0,
565 REG_A6XX_SP_GS_CONFIG,
566 REG_A6XX_HLSQ_GS_CNTL,
567 REG_A6XX_SP_GS_OBJ_START_LO,
568 },
569 [MESA_SHADER_FRAGMENT] = {
570 REG_A6XX_SP_FS_CTRL_REG0,
571 REG_A6XX_SP_FS_CONFIG,
572 REG_A6XX_HLSQ_FS_CNTL,
573 REG_A6XX_SP_FS_OBJ_START_LO,
574 },
575 [MESA_SHADER_COMPUTE] = {
576 REG_A6XX_SP_CS_CTRL_REG0,
577 REG_A6XX_SP_CS_CONFIG,
578 REG_A6XX_HLSQ_CS_CNTL,
579 REG_A6XX_SP_CS_OBJ_START_LO,
580 },
581 };
582 const struct xs_config *cfg = &xs_config[stage];
583
584 if (!xs) {
585 /* shader stage disabled */
586 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
587 tu_cs_emit(cs, 0);
588
589 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
590 tu_cs_emit(cs, 0);
591 return;
592 }
593
594 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
595 enum a3xx_threadsize threadsize = FOUR_QUADS;
596
597 /* TODO:
598 * the "threadsize" field may have nothing to do with threadsize,
599 * use a value that matches the blob until it is figured out
600 */
601 if (xs->type == MESA_SHADER_GEOMETRY)
602 threadsize = TWO_QUADS;
603
604 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
605 tu_cs_emit(cs,
606 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
607 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
608 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs->info.max_half_reg + 1) |
609 COND(xs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
610 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
611 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
612 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
613 /* only fragment shader sets VARYING bit */
614 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
615 /* unknown bit, seems unnecessary */
616 COND(is_fs, 0x1000000));
617
618 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
619 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
620 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
621 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
622 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
623 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
624 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
625 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
626 tu_cs_emit(cs, xs->instrlen);
627
628 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
629 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(xs->constlen, 4)) |
630 A6XX_HLSQ_VS_CNTL_ENABLED);
631
632 /* emit program binary
633 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
634 */
635
636 assert((binary_iova & 0x7f) == 0);
637
638 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
639 tu_cs_emit_qw(cs, binary_iova);
640
641 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
642 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
643 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
644 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
645 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
646 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
647 tu_cs_emit_qw(cs, binary_iova);
648
649 /* emit immediates */
650
651 const struct ir3_const_state *const_state = &xs->shader->const_state;
652 uint32_t base = const_state->offsets.immediate;
653 int size = const_state->immediates_count;
654
655 /* truncate size to avoid writing constants that shader
656 * does not use:
657 */
658 size = MIN2(size + base, xs->constlen) - base;
659
660 if (size <= 0)
661 return;
662
663 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + size * 4);
664 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
665 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
666 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
667 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
668 CP_LOAD_STATE6_0_NUM_UNIT(size));
669 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
670 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
671
672 for (unsigned i = 0; i < size; i++) {
673 tu_cs_emit(cs, const_state->immediates[i].val[0]);
674 tu_cs_emit(cs, const_state->immediates[i].val[1]);
675 tu_cs_emit(cs, const_state->immediates[i].val[2]);
676 tu_cs_emit(cs, const_state->immediates[i].val[3]);
677 }
678 }
679
680 static void
681 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
682 const struct ir3_shader_variant *v,
683 uint32_t binary_iova)
684 {
685 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
686 tu_cs_emit(cs, 0xff);
687
688 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
689
690 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
691 tu_cs_emit(cs, 0x41);
692
693 uint32_t local_invocation_id =
694 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
695 uint32_t work_group_id =
696 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
697
698 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
699 tu_cs_emit(cs,
700 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
701 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
702 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
703 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
704 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
705 }
706
707 static void
708 tu6_emit_vs_system_values(struct tu_cs *cs,
709 const struct ir3_shader_variant *vs,
710 const struct ir3_shader_variant *gs,
711 bool primid_passthru)
712 {
713 const uint32_t vertexid_regid =
714 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
715 const uint32_t instanceid_regid =
716 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
717 const uint32_t primitiveid_regid = gs ?
718 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
719 regid(63, 0);
720 const uint32_t gsheader_regid = gs ?
721 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
722 regid(63, 0);
723
724 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
725 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
726 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
727 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
728 0xfc000000);
729 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
730 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
731 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
732 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
733 0xfc00); /* VFD_CONTROL_5 */
734 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
735 }
736
737 /* Add any missing varyings needed for stream-out. Otherwise varyings not
738 * used by fragment shader will be stripped out.
739 */
740 static void
741 tu6_link_streamout(struct ir3_shader_linkage *l,
742 const struct ir3_shader_variant *v)
743 {
744 const struct ir3_stream_output_info *info = &v->shader->stream_output;
745
746 /*
747 * First, any stream-out varyings not already in linkage map (ie. also
748 * consumed by frag shader) need to be added:
749 */
750 for (unsigned i = 0; i < info->num_outputs; i++) {
751 const struct ir3_stream_output *out = &info->output[i];
752 unsigned compmask =
753 (1 << (out->num_components + out->start_component)) - 1;
754 unsigned k = out->register_index;
755 unsigned idx, nextloc = 0;
756
757 /* psize/pos need to be the last entries in linkage map, and will
758 * get added link_stream_out, so skip over them:
759 */
760 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
761 v->outputs[k].slot == VARYING_SLOT_POS)
762 continue;
763
764 for (idx = 0; idx < l->cnt; idx++) {
765 if (l->var[idx].regid == v->outputs[k].regid)
766 break;
767 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
768 }
769
770 /* add if not already in linkage map: */
771 if (idx == l->cnt)
772 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
773
774 /* expand component-mask if needed, ie streaming out all components
775 * but frag shader doesn't consume all components:
776 */
777 if (compmask & ~l->var[idx].compmask) {
778 l->var[idx].compmask |= compmask;
779 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
780 util_last_bit(l->var[idx].compmask));
781 }
782 }
783 }
784
785 static void
786 tu6_setup_streamout(const struct ir3_shader_variant *v,
787 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
788 {
789 const struct ir3_stream_output_info *info = &v->shader->stream_output;
790
791 memset(tf, 0, sizeof(*tf));
792
793 tf->prog_count = align(l->max_loc, 2) / 2;
794
795 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
796
797 /* set stride info to the streamout state */
798 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
799 tf->stride[i] = info->stride[i];
800
801 for (unsigned i = 0; i < info->num_outputs; i++) {
802 const struct ir3_stream_output *out = &info->output[i];
803 unsigned k = out->register_index;
804 unsigned idx;
805
806 /* Skip it, if there's an unused reg in the middle of outputs. */
807 if (v->outputs[k].regid == INVALID_REG)
808 continue;
809
810 tf->ncomp[out->output_buffer] += out->num_components;
811
812 /* linkage map sorted by order frag shader wants things, so
813 * a bit less ideal here..
814 */
815 for (idx = 0; idx < l->cnt; idx++)
816 if (l->var[idx].regid == v->outputs[k].regid)
817 break;
818
819 debug_assert(idx < l->cnt);
820
821 for (unsigned j = 0; j < out->num_components; j++) {
822 unsigned c = j + out->start_component;
823 unsigned loc = l->var[idx].loc + c;
824 unsigned off = j + out->dst_offset; /* in dwords */
825
826 if (loc & 1) {
827 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
828 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
829 A6XX_VPC_SO_PROG_B_OFF(off * 4);
830 } else {
831 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
832 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
833 A6XX_VPC_SO_PROG_A_OFF(off * 4);
834 }
835 }
836 }
837
838 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
839 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
840 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
841 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
842 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
843 }
844
845 static void
846 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
847 enum a6xx_state_block block, uint32_t offset,
848 uint32_t size, uint32_t *dwords) {
849 assert(size % 4 == 0);
850
851 tu_cs_emit_pkt7(cs, opcode, 3 + size);
852 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
853 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
854 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
855 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
856 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
857
858 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
859 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
860 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
861
862 tu_cs_emit_array(cs, dwords, size);
863 }
864
865 static void
866 tu6_emit_link_map(struct tu_cs *cs,
867 const struct ir3_shader_variant *producer,
868 const struct ir3_shader_variant *consumer) {
869 const struct ir3_const_state *const_state = &consumer->shader->const_state;
870 uint32_t base = const_state->offsets.primitive_map;
871 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
872 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
873 int size = DIV_ROUND_UP(num_loc, 4);
874
875 size = (MIN2(size + base, consumer->constlen) - base) * 4;
876 if (size <= 0)
877 return;
878
879 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
880 patch_locs);
881 }
882
883 static uint16_t
884 gl_primitive_to_tess(uint16_t primitive) {
885 switch (primitive) {
886 case GL_POINTS:
887 return TESS_POINTS;
888 case GL_LINE_STRIP:
889 return TESS_LINES;
890 case GL_TRIANGLE_STRIP:
891 return TESS_CW_TRIS;
892 default:
893 unreachable("");
894 }
895 }
896
897 void
898 tu6_emit_vpc(struct tu_cs *cs,
899 const struct ir3_shader_variant *vs,
900 const struct ir3_shader_variant *gs,
901 const struct ir3_shader_variant *fs,
902 struct tu_streamout_state *tf)
903 {
904 const struct ir3_shader_variant *last_shader = gs ?: vs;
905 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
906 if (fs)
907 ir3_link_shaders(&linkage, last_shader, fs, true);
908
909 if (last_shader->shader->stream_output.num_outputs)
910 tu6_link_streamout(&linkage, last_shader);
911
912 /* We do this after linking shaders in order to know whether PrimID
913 * passthrough needs to be enabled.
914 */
915 bool primid_passthru = linkage.primid_loc != 0xff;
916 tu6_emit_vs_system_values(cs, vs, gs, primid_passthru);
917
918 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
919 tu_cs_emit(cs, ~linkage.varmask[0]);
920 tu_cs_emit(cs, ~linkage.varmask[1]);
921 tu_cs_emit(cs, ~linkage.varmask[2]);
922 tu_cs_emit(cs, ~linkage.varmask[3]);
923
924 /* a6xx finds position/pointsize at the end */
925 const uint32_t position_regid =
926 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
927 const uint32_t pointsize_regid =
928 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
929 const uint32_t layer_regid = gs ?
930 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
931
932 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
933 if (layer_regid != regid(63, 0)) {
934 layer_loc = linkage.max_loc;
935 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
936 }
937 if (position_regid != regid(63, 0)) {
938 position_loc = linkage.max_loc;
939 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
940 }
941 if (pointsize_regid != regid(63, 0)) {
942 pointsize_loc = linkage.max_loc;
943 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
944 }
945
946 if (last_shader->shader->stream_output.num_outputs)
947 tu6_setup_streamout(last_shader, &linkage, tf);
948
949 /* map outputs of the last shader to VPC */
950 assert(linkage.cnt <= 32);
951 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
952 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
953 uint32_t sp_out[16];
954 uint32_t sp_vpc_dst[8];
955 for (uint32_t i = 0; i < linkage.cnt; i++) {
956 ((uint16_t *) sp_out)[i] =
957 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
958 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
959 ((uint8_t *) sp_vpc_dst)[i] =
960 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
961 }
962
963 if (gs)
964 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
965 else
966 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
967 tu_cs_emit_array(cs, sp_out, sp_out_count);
968
969 if (gs)
970 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
971 else
972 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
973 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
974
975 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
976 tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
977
978 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
979 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
980 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
981 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
982 A6XX_VPC_CNTL_0_UNKLOC(0xff));
983
984 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
985 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
986 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
987 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
988
989 if (gs) {
990 uint32_t vertices_out, invocations, output, vec4_size;
991 /* this detects the tu_clear_blit path, which doesn't set ->nir */
992 if (gs->shader->nir) {
993 tu6_emit_link_map(cs, vs, gs);
994 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
995 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
996 invocations = gs->shader->nir->info.gs.invocations - 1;
997 /* Size of per-primitive alloction in ldlw memory in vec4s. */
998 vec4_size = gs->shader->nir->info.gs.vertices_in *
999 DIV_ROUND_UP(vs->shader->output_size, 4);
1000 } else {
1001 vertices_out = 3;
1002 output = TESS_CW_TRIS;
1003 invocations = 0;
1004 vec4_size = 0;
1005 }
1006
1007 uint32_t primitive_regid =
1008 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
1009 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
1010 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
1011 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
1012 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
1013
1014 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
1015 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
1016
1017 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
1018 tu_cs_emit(cs, CONDREG(layer_regid,
1019 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
1020
1021 uint32_t flags_regid = ir3_find_output_regid(gs,
1022 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
1023
1024 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
1025 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
1026 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
1027
1028 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
1029 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
1030 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
1031 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
1032 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
1033
1034 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1035 tu_cs_emit(cs,
1036 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1037 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1038 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1039
1040 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1041 tu_cs_emit(cs, 0);
1042
1043 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
1044 tu_cs_emit(cs, 0);
1045
1046 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1047 tu_cs_emit(cs, 0xff);
1048
1049 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
1050 tu_cs_emit(cs, 0xffff00);
1051
1052 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1053 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1054
1055 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
1056 tu_cs_emit(cs, 0);
1057
1058 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1059 tu_cs_emit(cs, vs->shader->output_size);
1060 }
1061
1062 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
1063 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
1064
1065 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
1066 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
1067 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
1068 }
1069
1070 static int
1071 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1072 uint32_t index,
1073 uint8_t *interp_mode,
1074 uint8_t *ps_repl_mode)
1075 {
1076 enum
1077 {
1078 INTERP_SMOOTH = 0,
1079 INTERP_FLAT = 1,
1080 INTERP_ZERO = 2,
1081 INTERP_ONE = 3,
1082 };
1083 enum
1084 {
1085 PS_REPL_NONE = 0,
1086 PS_REPL_S = 1,
1087 PS_REPL_T = 2,
1088 PS_REPL_ONE_MINUS_T = 3,
1089 };
1090
1091 const uint32_t compmask = fs->inputs[index].compmask;
1092
1093 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1094 * fourth component occupy three consecutive varying slots
1095 */
1096 int shift = 0;
1097 *interp_mode = 0;
1098 *ps_repl_mode = 0;
1099 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1100 if (compmask & 0x1) {
1101 *ps_repl_mode |= PS_REPL_S << shift;
1102 shift += 2;
1103 }
1104 if (compmask & 0x2) {
1105 *ps_repl_mode |= PS_REPL_T << shift;
1106 shift += 2;
1107 }
1108 if (compmask & 0x4) {
1109 *interp_mode |= INTERP_ZERO << shift;
1110 shift += 2;
1111 }
1112 if (compmask & 0x8) {
1113 *interp_mode |= INTERP_ONE << 6;
1114 shift += 2;
1115 }
1116 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1117 fs->inputs[index].rasterflat) {
1118 for (int i = 0; i < 4; i++) {
1119 if (compmask & (1 << i)) {
1120 *interp_mode |= INTERP_FLAT << shift;
1121 shift += 2;
1122 }
1123 }
1124 }
1125
1126 return shift;
1127 }
1128
1129 static void
1130 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1131 const struct ir3_shader_variant *fs)
1132 {
1133 uint32_t interp_modes[8] = { 0 };
1134 uint32_t ps_repl_modes[8] = { 0 };
1135
1136 if (fs) {
1137 for (int i = -1;
1138 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1139
1140 /* get the mode for input i */
1141 uint8_t interp_mode;
1142 uint8_t ps_repl_mode;
1143 const int bits =
1144 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1145
1146 /* OR the mode into the array */
1147 const uint32_t inloc = fs->inputs[i].inloc * 2;
1148 uint32_t n = inloc / 32;
1149 uint32_t shift = inloc % 32;
1150 interp_modes[n] |= interp_mode << shift;
1151 ps_repl_modes[n] |= ps_repl_mode << shift;
1152 if (shift + bits > 32) {
1153 n++;
1154 shift = 32 - shift;
1155
1156 interp_modes[n] |= interp_mode >> shift;
1157 ps_repl_modes[n] |= ps_repl_mode >> shift;
1158 }
1159 }
1160 }
1161
1162 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1163 tu_cs_emit_array(cs, interp_modes, 8);
1164
1165 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1166 tu_cs_emit_array(cs, ps_repl_modes, 8);
1167 }
1168
1169 void
1170 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1171 {
1172 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1173 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
1174 uint32_t smask_in_regid;
1175
1176 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
1177 bool enable_varyings = fs->total_in > 0;
1178
1179 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1180 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1181 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1182 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1183 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1184 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1185 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1186 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1187 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1188
1189 if (fs->num_sampler_prefetch > 0) {
1190 assert(VALIDREG(ij_pix_regid));
1191 /* also, it seems like ij_pix is *required* to be r0.x */
1192 assert(ij_pix_regid == regid(0, 0));
1193 }
1194
1195 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1196 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1197 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1198 0x7000); // XXX);
1199 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1200 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1201 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1202 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1203 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1204 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1205 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1206 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1207 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1208 }
1209
1210 if (fs->num_sampler_prefetch > 0) {
1211 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1212 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1213 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1214 tu_cs_emit(cs,
1215 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1216 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1217 }
1218 }
1219
1220 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1221 tu_cs_emit(cs, 0x7);
1222 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1223 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1224 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1225 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1226 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1227 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1228 0xfc00fc00);
1229 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1230 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1231 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1232 0x0000fc00);
1233 tu_cs_emit(cs, 0xfc);
1234
1235 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1236 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1237
1238 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1239 tu_cs_emit(cs,
1240 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1241 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1242 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1243 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1244 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1245 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
1246 A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
1247 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1248
1249 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1250 tu_cs_emit(cs,
1251 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1252 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1253 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1254 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1255 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1256 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1257 COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
1258 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
1259 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1260 tu_cs_emit(cs,
1261 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1262 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1263 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1264 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1265
1266 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1267 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1268
1269 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1270 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1271
1272 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1273 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1274 }
1275
1276 static void
1277 tu6_emit_fs_outputs(struct tu_cs *cs,
1278 const struct ir3_shader_variant *fs,
1279 uint32_t mrt_count, bool dual_src_blend,
1280 uint32_t render_components)
1281 {
1282 uint32_t smask_regid, posz_regid;
1283
1284 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1285 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1286
1287 uint32_t fragdata_regid[8];
1288 if (fs->color0_mrt) {
1289 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1290 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1291 fragdata_regid[i] = fragdata_regid[0];
1292 } else {
1293 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1294 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1295 }
1296
1297 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1298 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1299 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1300 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
1301 0xfc000000);
1302 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1303
1304 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1305 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1306 // TODO we could have a mix of half and full precision outputs,
1307 // we really need to figure out half-precision from IR3_REG_HALF
1308 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1309 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1310 }
1311
1312 tu_cs_emit_regs(cs,
1313 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1314
1315 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1316 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1317 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1318 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1319 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1320
1321 tu_cs_emit_regs(cs,
1322 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1323
1324 enum a6xx_ztest_mode zmode;
1325
1326 if (fs->no_earlyz || fs->has_kill || fs->writes_pos) {
1327 zmode = A6XX_LATE_Z;
1328 } else {
1329 zmode = A6XX_EARLY_Z;
1330 }
1331
1332 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1333 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1334
1335 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1336 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1337 }
1338
1339 static void
1340 tu6_emit_geometry_consts(struct tu_cs *cs,
1341 const struct ir3_shader_variant *vs,
1342 const struct ir3_shader_variant *gs) {
1343 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1344
1345 uint32_t params[4] = {
1346 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1347 vs->shader->output_size * 4, /* vertex stride */
1348 0,
1349 0,
1350 };
1351 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1352 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1353 ARRAY_SIZE(params), params);
1354
1355 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1356 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1357 ARRAY_SIZE(params), params);
1358 }
1359
1360 static void
1361 tu6_emit_program(struct tu_cs *cs,
1362 struct tu_pipeline_builder *builder,
1363 const struct tu_bo *binary_bo,
1364 bool binning_pass,
1365 struct tu_streamout_state *tf)
1366 {
1367 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
1368 const struct ir3_shader_variant *bs = builder->binning_variant;
1369 const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
1370 const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
1371 gl_shader_stage stage = MESA_SHADER_VERTEX;
1372
1373 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1374
1375 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1376 tu_cs_emit(cs, 0xff); /* XXX */
1377
1378 /* Don't use the binning pass variant when GS is present because we don't
1379 * support compiling correct binning pass variants with GS.
1380 */
1381 if (binning_pass && !gs) {
1382 vs = bs;
1383 tu6_emit_xs_config(cs, stage, bs,
1384 binary_bo->iova + builder->binning_vs_offset);
1385 stage++;
1386 }
1387
1388 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1389 const struct ir3_shader_variant *xs = builder->variants[stage];
1390
1391 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1392 fs = xs = NULL;
1393
1394 tu6_emit_xs_config(cs, stage, xs,
1395 binary_bo->iova + builder->shader_offsets[stage]);
1396 }
1397
1398 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1399 tu_cs_emit(cs, 0);
1400
1401 tu6_emit_vpc(cs, vs, gs, fs, tf);
1402 tu6_emit_vpc_varying_modes(cs, fs);
1403
1404 if (fs) {
1405 tu6_emit_fs_inputs(cs, fs);
1406 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1407 builder->use_dual_src_blend,
1408 builder->render_components);
1409 } else {
1410 /* TODO: check if these can be skipped if fs is disabled */
1411 struct ir3_shader_variant dummy_variant = {};
1412 tu6_emit_fs_inputs(cs, &dummy_variant);
1413 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1414 builder->use_dual_src_blend,
1415 builder->render_components);
1416 }
1417
1418 if (gs)
1419 tu6_emit_geometry_consts(cs, vs, gs);
1420 }
1421
1422 static void
1423 tu6_emit_vertex_input(struct tu_cs *cs,
1424 const struct ir3_shader_variant *vs,
1425 const VkPipelineVertexInputStateCreateInfo *info,
1426 uint32_t *bindings_used)
1427 {
1428 uint32_t vfd_decode_idx = 0;
1429 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1430
1431 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1432 const VkVertexInputBindingDescription *binding =
1433 &info->pVertexBindingDescriptions[i];
1434
1435 tu_cs_emit_regs(cs,
1436 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1437
1438 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1439 binding_instanced |= 1 << binding->binding;
1440
1441 *bindings_used |= 1 << binding->binding;
1442 }
1443
1444 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1445
1446 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1447 const VkVertexInputAttributeDescription *attr =
1448 &info->pVertexAttributeDescriptions[i];
1449 uint32_t input_idx;
1450
1451 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1452 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1453 break;
1454 }
1455
1456 /* attribute not used, skip it */
1457 if (input_idx == vs->inputs_count)
1458 continue;
1459
1460 const struct tu_native_format format = tu6_format_vtx(attr->format);
1461 tu_cs_emit_regs(cs,
1462 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1463 .idx = attr->binding,
1464 .offset = attr->offset,
1465 .instanced = binding_instanced & (1 << attr->binding),
1466 .format = format.fmt,
1467 .swap = format.swap,
1468 .unk30 = 1,
1469 ._float = !vk_format_is_int(attr->format)),
1470 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1471
1472 tu_cs_emit_regs(cs,
1473 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1474 .writemask = vs->inputs[input_idx].compmask,
1475 .regid = vs->inputs[input_idx].regid));
1476
1477 vfd_decode_idx++;
1478 }
1479
1480 tu_cs_emit_regs(cs,
1481 A6XX_VFD_CONTROL_0(
1482 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1483 .decode_cnt = vfd_decode_idx));
1484 }
1485
1486 static uint32_t
1487 tu6_guardband_adj(uint32_t v)
1488 {
1489 if (v > 256)
1490 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1491 else
1492 return 511;
1493 }
1494
1495 void
1496 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1497 {
1498 float offsets[3];
1499 float scales[3];
1500 scales[0] = viewport->width / 2.0f;
1501 scales[1] = viewport->height / 2.0f;
1502 scales[2] = viewport->maxDepth - viewport->minDepth;
1503 offsets[0] = viewport->x + scales[0];
1504 offsets[1] = viewport->y + scales[1];
1505 offsets[2] = viewport->minDepth;
1506
1507 VkOffset2D min;
1508 VkOffset2D max;
1509 min.x = (int32_t) viewport->x;
1510 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1511 if (viewport->height >= 0.0f) {
1512 min.y = (int32_t) viewport->y;
1513 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1514 } else {
1515 min.y = (int32_t)(viewport->y + viewport->height);
1516 max.y = (int32_t) ceilf(viewport->y);
1517 }
1518 /* the spec allows viewport->height to be 0.0f */
1519 if (min.y == max.y)
1520 max.y++;
1521 assert(min.x >= 0 && min.x < max.x);
1522 assert(min.y >= 0 && min.y < max.y);
1523
1524 VkExtent2D guardband_adj;
1525 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1526 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1527
1528 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1529 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1530 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1531 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1532 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1533 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1534 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1535
1536 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1537 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1538 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1539 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1540 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1541
1542 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1543 tu_cs_emit(cs,
1544 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1545 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1546
1547 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1548 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1549
1550 tu_cs_emit_regs(cs,
1551 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1552 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1553
1554 tu_cs_emit_regs(cs,
1555 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1556 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1557 }
1558
1559 void
1560 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1561 {
1562 const VkOffset2D min = scissor->offset;
1563 const VkOffset2D max = {
1564 scissor->offset.x + scissor->extent.width,
1565 scissor->offset.y + scissor->extent.height,
1566 };
1567
1568 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1569 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1570 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1571 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1572 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1573 }
1574
1575 void
1576 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1577 {
1578 if (!samp_loc) {
1579 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1580 tu_cs_emit(cs, 0);
1581
1582 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1583 tu_cs_emit(cs, 0);
1584
1585 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1586 tu_cs_emit(cs, 0);
1587 return;
1588 }
1589
1590 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1591 assert(samp_loc->sampleLocationGridSize.width == 1);
1592 assert(samp_loc->sampleLocationGridSize.height == 1);
1593
1594 uint32_t sample_config =
1595 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1596 uint32_t sample_locations = 0;
1597 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1598 sample_locations |=
1599 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1600 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1601 }
1602
1603 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1604 tu_cs_emit(cs, sample_config);
1605 tu_cs_emit(cs, sample_locations);
1606
1607 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1608 tu_cs_emit(cs, sample_config);
1609 tu_cs_emit(cs, sample_locations);
1610
1611 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1612 tu_cs_emit(cs, sample_config);
1613 tu_cs_emit(cs, sample_locations);
1614 }
1615
1616 static uint32_t
1617 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1618 VkSampleCountFlagBits samples)
1619 {
1620 uint32_t gras_su_cntl = 0;
1621
1622 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1623 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1624 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1625 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1626
1627 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1628 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1629
1630 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1631
1632 if (rast_info->depthBiasEnable)
1633 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1634
1635 if (samples > VK_SAMPLE_COUNT_1_BIT)
1636 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1637
1638 return gras_su_cntl;
1639 }
1640
1641 void
1642 tu6_emit_depth_bias(struct tu_cs *cs,
1643 float constant_factor,
1644 float clamp,
1645 float slope_factor)
1646 {
1647 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1648 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1649 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1650 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1651 }
1652
1653 static void
1654 tu6_emit_depth_control(struct tu_cs *cs,
1655 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1656 const VkPipelineRasterizationStateCreateInfo *rast_info)
1657 {
1658 assert(!ds_info->depthBoundsTestEnable);
1659
1660 uint32_t rb_depth_cntl = 0;
1661 if (ds_info->depthTestEnable) {
1662 rb_depth_cntl |=
1663 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1664 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1665 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1666
1667 if (rast_info->depthClampEnable)
1668 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1669
1670 if (ds_info->depthWriteEnable)
1671 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1672 }
1673
1674 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1675 tu_cs_emit(cs, rb_depth_cntl);
1676 }
1677
1678 static void
1679 tu6_emit_stencil_control(struct tu_cs *cs,
1680 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1681 {
1682 uint32_t rb_stencil_control = 0;
1683 if (ds_info->stencilTestEnable) {
1684 const VkStencilOpState *front = &ds_info->front;
1685 const VkStencilOpState *back = &ds_info->back;
1686 rb_stencil_control |=
1687 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1688 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1689 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1690 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1691 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1692 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1693 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1694 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1695 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1696 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1697 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1698 }
1699
1700 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1701 tu_cs_emit(cs, rb_stencil_control);
1702 }
1703
1704 static uint32_t
1705 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1706 bool has_alpha)
1707 {
1708 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1709 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1710 has_alpha ? att->srcColorBlendFactor
1711 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1712 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1713 has_alpha ? att->dstColorBlendFactor
1714 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1715 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1716 const enum adreno_rb_blend_factor src_alpha_factor =
1717 tu6_blend_factor(att->srcAlphaBlendFactor);
1718 const enum adreno_rb_blend_factor dst_alpha_factor =
1719 tu6_blend_factor(att->dstAlphaBlendFactor);
1720
1721 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1722 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1723 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1724 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1725 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1726 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1727 }
1728
1729 static uint32_t
1730 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1731 uint32_t rb_mrt_control_rop,
1732 bool is_int,
1733 bool has_alpha)
1734 {
1735 uint32_t rb_mrt_control =
1736 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1737
1738 /* ignore blending and logic op for integer attachments */
1739 if (is_int) {
1740 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1741 return rb_mrt_control;
1742 }
1743
1744 rb_mrt_control |= rb_mrt_control_rop;
1745
1746 if (att->blendEnable) {
1747 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1748
1749 if (has_alpha)
1750 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1751 }
1752
1753 return rb_mrt_control;
1754 }
1755
1756 static void
1757 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1758 const VkPipelineColorBlendStateCreateInfo *blend_info,
1759 const VkFormat attachment_formats[MAX_RTS],
1760 uint32_t *blend_enable_mask)
1761 {
1762 *blend_enable_mask = 0;
1763
1764 bool rop_reads_dst = false;
1765 uint32_t rb_mrt_control_rop = 0;
1766 if (blend_info->logicOpEnable) {
1767 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1768 rb_mrt_control_rop =
1769 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1770 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1771 }
1772
1773 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1774 const VkPipelineColorBlendAttachmentState *att =
1775 &blend_info->pAttachments[i];
1776 const VkFormat format = attachment_formats[i];
1777
1778 uint32_t rb_mrt_control = 0;
1779 uint32_t rb_mrt_blend_control = 0;
1780 if (format != VK_FORMAT_UNDEFINED) {
1781 const bool is_int = vk_format_is_int(format);
1782 const bool has_alpha = vk_format_has_alpha(format);
1783
1784 rb_mrt_control =
1785 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1786 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1787
1788 if (att->blendEnable || rop_reads_dst)
1789 *blend_enable_mask |= 1 << i;
1790 }
1791
1792 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1793 tu_cs_emit(cs, rb_mrt_control);
1794 tu_cs_emit(cs, rb_mrt_blend_control);
1795 }
1796 }
1797
1798 static void
1799 tu6_emit_blend_control(struct tu_cs *cs,
1800 uint32_t blend_enable_mask,
1801 bool dual_src_blend,
1802 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1803 {
1804 const uint32_t sample_mask =
1805 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1806 : ((1 << msaa_info->rasterizationSamples) - 1);
1807
1808 tu_cs_emit_regs(cs,
1809 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1810 .dual_color_in_enable = dual_src_blend,
1811 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1812 .unk8 = true));
1813
1814 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1815 tu_cs_emit_regs(cs,
1816 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1817 .independent_blend = true,
1818 .sample_mask = sample_mask,
1819 .dual_color_in_enable = dual_src_blend,
1820 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1821 .alpha_to_one = msaa_info->alphaToOneEnable));
1822 }
1823
1824 static VkResult
1825 tu_pipeline_create(struct tu_device *dev,
1826 struct tu_pipeline_layout *layout,
1827 bool compute,
1828 const VkAllocationCallbacks *pAllocator,
1829 struct tu_pipeline **out_pipeline)
1830 {
1831 struct tu_pipeline *pipeline =
1832 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
1833 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1834 if (!pipeline)
1835 return VK_ERROR_OUT_OF_HOST_MEMORY;
1836
1837 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
1838
1839 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1840 * that LOAD_STATE can potentially take up a large amount of space so we
1841 * calculate its size explicitly.
1842 */
1843 unsigned load_state_size = tu6_load_state_size(layout, compute);
1844 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size);
1845 if (result != VK_SUCCESS) {
1846 vk_free2(&dev->alloc, pAllocator, pipeline);
1847 return result;
1848 }
1849
1850 *out_pipeline = pipeline;
1851
1852 return VK_SUCCESS;
1853 }
1854
1855 static void
1856 tu_pipeline_shader_key_init(struct ir3_shader_key *key,
1857 const VkGraphicsPipelineCreateInfo *pipeline_info)
1858 {
1859 bool has_gs = false;
1860 bool msaa = false;
1861 if (pipeline_info) {
1862 for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
1863 if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
1864 has_gs = true;
1865 break;
1866 }
1867 }
1868
1869 const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
1870 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
1871 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1872 if (!pipeline_info->pRasterizationState->rasterizerDiscardEnable &&
1873 (msaa_info->rasterizationSamples > 1 ||
1874 /* also set msaa key when sample location is not the default
1875 * since this affects varying interpolation */
1876 (sample_locations && sample_locations->sampleLocationsEnable))) {
1877 msaa = true;
1878 }
1879 }
1880
1881 /* TODO: Populate the remaining fields of ir3_shader_key. */
1882 *key = (struct ir3_shader_key) {
1883 .has_gs = has_gs,
1884 .msaa = msaa,
1885 };
1886 }
1887
1888 static VkResult
1889 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1890 {
1891 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1892 NULL
1893 };
1894 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1895 gl_shader_stage stage =
1896 vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage);
1897 stage_infos[stage] = &builder->create_info->pStages[i];
1898 }
1899
1900 struct ir3_shader_key key;
1901 tu_pipeline_shader_key_init(&key, builder->create_info);
1902
1903 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1904 stage < MESA_SHADER_STAGES; stage++) {
1905 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1906 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
1907 continue;
1908
1909 struct tu_shader *shader =
1910 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1911 builder->alloc);
1912 if (!shader)
1913 return VK_ERROR_OUT_OF_HOST_MEMORY;
1914
1915 builder->shaders[stage] = shader;
1916 }
1917
1918 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1919 stage > MESA_SHADER_NONE; stage--) {
1920 if (!builder->shaders[stage])
1921 continue;
1922
1923 bool created;
1924 builder->variants[stage] =
1925 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
1926 &key, false, &created);
1927 if (!builder->variants[stage])
1928 return VK_ERROR_OUT_OF_HOST_MEMORY;
1929
1930 builder->shader_offsets[stage] = builder->shader_total_size;
1931 builder->shader_total_size +=
1932 sizeof(uint32_t) * builder->variants[stage]->info.sizedwords;
1933 }
1934
1935 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1936 struct ir3_shader_variant *variant;
1937
1938 if (vs->ir3_shader->stream_output.num_outputs) {
1939 variant = builder->variants[MESA_SHADER_VERTEX];
1940 } else {
1941 bool created;
1942 variant = ir3_shader_get_variant(vs->ir3_shader, &key,
1943 true, &created);
1944 if (!variant)
1945 return VK_ERROR_OUT_OF_HOST_MEMORY;
1946 }
1947
1948 builder->binning_vs_offset = builder->shader_total_size;
1949 builder->shader_total_size +=
1950 sizeof(uint32_t) * variant->info.sizedwords;
1951 builder->binning_variant = variant;
1952
1953 return VK_SUCCESS;
1954 }
1955
1956 static VkResult
1957 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1958 struct tu_pipeline *pipeline)
1959 {
1960 struct tu_bo *bo = &pipeline->program.binary_bo;
1961
1962 VkResult result =
1963 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1964 if (result != VK_SUCCESS)
1965 return result;
1966
1967 result = tu_bo_map(builder->device, bo);
1968 if (result != VK_SUCCESS)
1969 return result;
1970
1971 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1972 const struct ir3_shader_variant *variant = builder->variants[i];
1973 if (!variant)
1974 continue;
1975
1976 memcpy(bo->map + builder->shader_offsets[i], variant->bin,
1977 sizeof(uint32_t) * variant->info.sizedwords);
1978 }
1979
1980 if (builder->binning_variant) {
1981 const struct ir3_shader_variant *variant = builder->binning_variant;
1982 memcpy(bo->map + builder->binning_vs_offset, variant->bin,
1983 sizeof(uint32_t) * variant->info.sizedwords);
1984 }
1985
1986 return VK_SUCCESS;
1987 }
1988
1989 static void
1990 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1991 struct tu_pipeline *pipeline)
1992 {
1993 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1994 builder->create_info->pDynamicState;
1995
1996 if (!dynamic_info)
1997 return;
1998
1999 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2000 VkDynamicState state = dynamic_info->pDynamicStates[i];
2001 switch (state) {
2002 case VK_DYNAMIC_STATE_VIEWPORT ... VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2003 pipeline->dynamic_state_mask |= BIT(state);
2004 break;
2005 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
2006 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS);
2007 break;
2008 default:
2009 assert(!"unsupported dynamic state");
2010 break;
2011 }
2012 }
2013 }
2014
2015 static void
2016 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2017 struct tu_shader *shader,
2018 struct ir3_shader_variant *v)
2019 {
2020 link->ubo_state = v->shader->ubo_state;
2021 link->const_state = v->shader->const_state;
2022 link->constlen = v->constlen;
2023 link->push_consts = shader->push_consts;
2024 }
2025
2026 static void
2027 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2028 struct tu_pipeline *pipeline)
2029 {
2030 struct tu_cs prog_cs;
2031 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2032 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
2033 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2034
2035 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2036 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
2037 pipeline->program.binning_state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2038
2039 VkShaderStageFlags stages = 0;
2040 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2041 stages |= builder->create_info->pStages[i].stage;
2042 }
2043 pipeline->active_stages = stages;
2044
2045 uint32_t desc_sets = 0;
2046 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2047 if (!builder->shaders[i])
2048 continue;
2049
2050 tu_pipeline_set_linkage(&pipeline->program.link[i],
2051 builder->shaders[i],
2052 builder->variants[i]);
2053 desc_sets |= builder->shaders[i]->active_desc_sets;
2054 }
2055 pipeline->active_desc_sets = desc_sets;
2056 }
2057
2058 static void
2059 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2060 struct tu_pipeline *pipeline)
2061 {
2062 const VkPipelineVertexInputStateCreateInfo *vi_info =
2063 builder->create_info->pVertexInputState;
2064 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
2065 const struct ir3_shader_variant *bs = builder->binning_variant;
2066
2067 struct tu_cs vi_cs;
2068 tu_cs_begin_sub_stream(&pipeline->cs,
2069 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2070 tu6_emit_vertex_input(&vi_cs, vs, vi_info,
2071 &pipeline->vi.bindings_used);
2072 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2073
2074 if (bs) {
2075 tu_cs_begin_sub_stream(&pipeline->cs,
2076 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2077 tu6_emit_vertex_input(
2078 &vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
2079 pipeline->vi.binning_state_ib =
2080 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2081 }
2082 }
2083
2084 static void
2085 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2086 struct tu_pipeline *pipeline)
2087 {
2088 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2089 builder->create_info->pInputAssemblyState;
2090
2091 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2092 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2093 }
2094
2095 static bool
2096 tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs,
2097 uint32_t id, uint32_t size)
2098 {
2099 struct ts_cs_memory memory;
2100
2101 if (pipeline->dynamic_state_mask & BIT(id))
2102 return false;
2103
2104 /* TODO: share this logc with tu_cmd_dynamic_state */
2105 tu_cs_alloc(&pipeline->cs, size, 1, &memory);
2106 tu_cs_init_external(cs, memory.map, memory.map + size);
2107 tu_cs_begin(cs);
2108 tu_cs_reserve_space(cs, size);
2109
2110 assert(id < ARRAY_SIZE(pipeline->dynamic_state));
2111 pipeline->dynamic_state[id].iova = memory.iova;
2112 pipeline->dynamic_state[id].size = size;
2113 return true;
2114 }
2115
2116 static void
2117 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2118 struct tu_pipeline *pipeline)
2119 {
2120 /* The spec says:
2121 *
2122 * pViewportState is a pointer to an instance of the
2123 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2124 * pipeline has rasterization disabled."
2125 *
2126 * We leave the relevant registers stale in that case.
2127 */
2128 if (builder->rasterizer_discard)
2129 return;
2130
2131 const VkPipelineViewportStateCreateInfo *vp_info =
2132 builder->create_info->pViewportState;
2133
2134 struct tu_cs cs;
2135
2136 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_VIEWPORT, 18))
2137 tu6_emit_viewport(&cs, vp_info->pViewports);
2138
2139 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_SCISSOR, 3))
2140 tu6_emit_scissor(&cs, vp_info->pScissors);
2141 }
2142
2143 static void
2144 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2145 struct tu_pipeline *pipeline)
2146 {
2147 const VkPipelineRasterizationStateCreateInfo *rast_info =
2148 builder->create_info->pRasterizationState;
2149
2150 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2151
2152 struct tu_cs cs;
2153 tu_cs_begin_sub_stream(&pipeline->cs, 7, &cs);
2154
2155 tu_cs_emit_regs(&cs,
2156 A6XX_GRAS_CL_CNTL(
2157 .znear_clip_disable = rast_info->depthClampEnable,
2158 .zfar_clip_disable = rast_info->depthClampEnable,
2159 .unk5 = rast_info->depthClampEnable,
2160 .zero_gb_scale_z = 1,
2161 .vp_clip_code_ignore = 1));
2162 /* move to hw ctx init? */
2163 tu_cs_emit_regs(&cs, A6XX_GRAS_UNKNOWN_8001());
2164 tu_cs_emit_regs(&cs,
2165 A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
2166 A6XX_GRAS_SU_POINT_SIZE(1.0f));
2167
2168 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2169
2170 pipeline->gras_su_cntl =
2171 tu6_gras_su_cntl(rast_info, builder->samples);
2172
2173 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_LINE_WIDTH, 2)) {
2174 pipeline->gras_su_cntl |=
2175 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info->lineWidth / 2.0f);
2176 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = pipeline->gras_su_cntl));
2177 }
2178
2179 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BIAS, 4)) {
2180 tu6_emit_depth_bias(&cs, rast_info->depthBiasConstantFactor,
2181 rast_info->depthBiasClamp,
2182 rast_info->depthBiasSlopeFactor);
2183 }
2184
2185 }
2186
2187 static void
2188 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2189 struct tu_pipeline *pipeline)
2190 {
2191 /* The spec says:
2192 *
2193 * pDepthStencilState is a pointer to an instance of the
2194 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2195 * the pipeline has rasterization disabled or if the subpass of the
2196 * render pass the pipeline is created against does not use a
2197 * depth/stencil attachment.
2198 *
2199 * Disable both depth and stencil tests if there is no ds attachment,
2200 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2201 * only the separate stencil attachment
2202 */
2203 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2204 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2205 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2206 ? builder->create_info->pDepthStencilState
2207 : &dummy_ds_info;
2208 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2209 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2210 ? ds_info : &dummy_ds_info;
2211
2212 struct tu_cs cs;
2213 tu_cs_begin_sub_stream(&pipeline->cs, 6, &cs);
2214
2215 /* move to hw ctx init? */
2216 tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
2217 tu6_emit_depth_control(&cs, ds_info_depth,
2218 builder->create_info->pRasterizationState);
2219 tu6_emit_stencil_control(&cs, ds_info);
2220
2221 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2222
2223 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
2224 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
2225 .bfmask = ds_info->back.compareMask & 0xff));
2226 }
2227
2228 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2)) {
2229 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.wrmask = ds_info->front.writeMask & 0xff,
2230 .bfwrmask = ds_info->back.writeMask & 0xff));
2231 }
2232
2233 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2)) {
2234 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.ref = ds_info->front.reference & 0xff,
2235 .bfref = ds_info->back.reference & 0xff));
2236 }
2237 }
2238
2239 static void
2240 tu_pipeline_builder_parse_multisample_and_color_blend(
2241 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2242 {
2243 /* The spec says:
2244 *
2245 * pMultisampleState is a pointer to an instance of the
2246 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2247 * has rasterization disabled.
2248 *
2249 * Also,
2250 *
2251 * pColorBlendState is a pointer to an instance of the
2252 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2253 * pipeline has rasterization disabled or if the subpass of the render
2254 * pass the pipeline is created against does not use any color
2255 * attachments.
2256 *
2257 * We leave the relevant registers stale when rasterization is disabled.
2258 */
2259 if (builder->rasterizer_discard)
2260 return;
2261
2262 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2263 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2264 builder->create_info->pMultisampleState;
2265 const VkPipelineColorBlendStateCreateInfo *blend_info =
2266 builder->use_color_attachments ? builder->create_info->pColorBlendState
2267 : &dummy_blend_info;
2268
2269 struct tu_cs cs;
2270 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 4, &cs);
2271
2272 uint32_t blend_enable_mask;
2273 tu6_emit_rb_mrt_controls(&cs, blend_info,
2274 builder->color_attachment_formats,
2275 &blend_enable_mask);
2276
2277 tu6_emit_blend_control(&cs, blend_enable_mask,
2278 builder->use_dual_src_blend, msaa_info);
2279
2280 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2281
2282 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5)) {
2283 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2284 tu_cs_emit_array(&cs, (const uint32_t *) blend_info->blendConstants, 4);
2285 }
2286
2287 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2288 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2289 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2290
2291 if (sample_locations && sample_locations->sampleLocationsEnable)
2292 samp_loc = &sample_locations->sampleLocationsInfo;
2293
2294 if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
2295 samp_loc ? 9 : 6)) {
2296 tu6_emit_sample_locations(&cs, samp_loc);
2297 }
2298 }
2299
2300 static void
2301 tu_pipeline_finish(struct tu_pipeline *pipeline,
2302 struct tu_device *dev,
2303 const VkAllocationCallbacks *alloc)
2304 {
2305 tu_cs_finish(&pipeline->cs);
2306
2307 if (pipeline->program.binary_bo.gem_handle)
2308 tu_bo_finish(dev, &pipeline->program.binary_bo);
2309 }
2310
2311 static VkResult
2312 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2313 struct tu_pipeline **pipeline)
2314 {
2315 VkResult result = tu_pipeline_create(builder->device, builder->layout,
2316 false, builder->alloc, pipeline);
2317 if (result != VK_SUCCESS)
2318 return result;
2319
2320 (*pipeline)->layout = builder->layout;
2321
2322 /* compile and upload shaders */
2323 result = tu_pipeline_builder_compile_shaders(builder);
2324 if (result == VK_SUCCESS)
2325 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2326 if (result != VK_SUCCESS) {
2327 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2328 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2329 *pipeline = VK_NULL_HANDLE;
2330
2331 return result;
2332 }
2333
2334 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2335 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2336 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2337 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2338 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2339 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2340 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2341 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2342 tu6_emit_load_state(*pipeline, false);
2343
2344 /* we should have reserved enough space upfront such that the CS never
2345 * grows
2346 */
2347 assert((*pipeline)->cs.bo_count == 1);
2348
2349 return VK_SUCCESS;
2350 }
2351
2352 static void
2353 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2354 {
2355 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2356 if (!builder->shaders[i])
2357 continue;
2358 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2359 }
2360 }
2361
2362 static void
2363 tu_pipeline_builder_init_graphics(
2364 struct tu_pipeline_builder *builder,
2365 struct tu_device *dev,
2366 struct tu_pipeline_cache *cache,
2367 const VkGraphicsPipelineCreateInfo *create_info,
2368 const VkAllocationCallbacks *alloc)
2369 {
2370 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2371
2372 *builder = (struct tu_pipeline_builder) {
2373 .device = dev,
2374 .cache = cache,
2375 .create_info = create_info,
2376 .alloc = alloc,
2377 .layout = layout,
2378 };
2379
2380 builder->rasterizer_discard =
2381 create_info->pRasterizationState->rasterizerDiscardEnable;
2382
2383 if (builder->rasterizer_discard) {
2384 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2385 } else {
2386 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2387
2388 const struct tu_render_pass *pass =
2389 tu_render_pass_from_handle(create_info->renderPass);
2390 const struct tu_subpass *subpass =
2391 &pass->subpasses[create_info->subpass];
2392
2393 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2394 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2395 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2396
2397 assert(subpass->color_count == 0 ||
2398 !create_info->pColorBlendState ||
2399 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2400 builder->color_attachment_count = subpass->color_count;
2401 for (uint32_t i = 0; i < subpass->color_count; i++) {
2402 const uint32_t a = subpass->color_attachments[i].attachment;
2403 if (a == VK_ATTACHMENT_UNUSED)
2404 continue;
2405
2406 builder->color_attachment_formats[i] = pass->attachments[a].format;
2407 builder->use_color_attachments = true;
2408 builder->render_components |= 0xf << (i * 4);
2409 }
2410
2411 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2412 builder->color_attachment_count++;
2413 builder->use_dual_src_blend = true;
2414 /* dual source blending has an extra fs output in the 2nd slot */
2415 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2416 builder->render_components |= 0xf << 4;
2417 }
2418 }
2419 }
2420
2421 static VkResult
2422 tu_graphics_pipeline_create(VkDevice device,
2423 VkPipelineCache pipelineCache,
2424 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2425 const VkAllocationCallbacks *pAllocator,
2426 VkPipeline *pPipeline)
2427 {
2428 TU_FROM_HANDLE(tu_device, dev, device);
2429 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2430
2431 struct tu_pipeline_builder builder;
2432 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2433 pCreateInfo, pAllocator);
2434
2435 struct tu_pipeline *pipeline = NULL;
2436 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2437 tu_pipeline_builder_finish(&builder);
2438
2439 if (result == VK_SUCCESS)
2440 *pPipeline = tu_pipeline_to_handle(pipeline);
2441 else
2442 *pPipeline = VK_NULL_HANDLE;
2443
2444 return result;
2445 }
2446
2447 VkResult
2448 tu_CreateGraphicsPipelines(VkDevice device,
2449 VkPipelineCache pipelineCache,
2450 uint32_t count,
2451 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2452 const VkAllocationCallbacks *pAllocator,
2453 VkPipeline *pPipelines)
2454 {
2455 VkResult final_result = VK_SUCCESS;
2456
2457 for (uint32_t i = 0; i < count; i++) {
2458 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2459 &pCreateInfos[i], pAllocator,
2460 &pPipelines[i]);
2461
2462 if (result != VK_SUCCESS)
2463 final_result = result;
2464 }
2465
2466 return final_result;
2467 }
2468
2469 static VkResult
2470 tu_compute_upload_shader(VkDevice device,
2471 struct tu_pipeline *pipeline,
2472 struct ir3_shader_variant *v)
2473 {
2474 TU_FROM_HANDLE(tu_device, dev, device);
2475 struct tu_bo *bo = &pipeline->program.binary_bo;
2476
2477 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2478 VkResult result =
2479 tu_bo_init_new(dev, bo, shader_size);
2480 if (result != VK_SUCCESS)
2481 return result;
2482
2483 result = tu_bo_map(dev, bo);
2484 if (result != VK_SUCCESS)
2485 return result;
2486
2487 memcpy(bo->map, v->bin, shader_size);
2488
2489 return VK_SUCCESS;
2490 }
2491
2492
2493 static VkResult
2494 tu_compute_pipeline_create(VkDevice device,
2495 VkPipelineCache _cache,
2496 const VkComputePipelineCreateInfo *pCreateInfo,
2497 const VkAllocationCallbacks *pAllocator,
2498 VkPipeline *pPipeline)
2499 {
2500 TU_FROM_HANDLE(tu_device, dev, device);
2501 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2502 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2503 VkResult result;
2504
2505 struct tu_pipeline *pipeline;
2506
2507 *pPipeline = VK_NULL_HANDLE;
2508
2509 result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline);
2510 if (result != VK_SUCCESS)
2511 return result;
2512
2513 pipeline->layout = layout;
2514
2515 struct ir3_shader_key key;
2516 tu_pipeline_shader_key_init(&key, NULL);
2517
2518 struct tu_shader *shader =
2519 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2520 if (!shader) {
2521 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2522 goto fail;
2523 }
2524
2525 bool created;
2526 struct ir3_shader_variant *v =
2527 ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
2528 if (!v)
2529 goto fail;
2530
2531 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2532 shader, v);
2533
2534 result = tu_compute_upload_shader(device, pipeline, v);
2535 if (result != VK_SUCCESS)
2536 goto fail;
2537
2538 for (int i = 0; i < 3; i++)
2539 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2540
2541 struct tu_cs prog_cs;
2542 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2543 tu6_emit_cs_config(&prog_cs, shader, v, pipeline->program.binary_bo.iova);
2544 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2545
2546 tu6_emit_load_state(pipeline, true);
2547
2548 *pPipeline = tu_pipeline_to_handle(pipeline);
2549 return VK_SUCCESS;
2550
2551 fail:
2552 if (shader)
2553 tu_shader_destroy(dev, shader, pAllocator);
2554
2555 tu_pipeline_finish(pipeline, dev, pAllocator);
2556 vk_free2(&dev->alloc, pAllocator, pipeline);
2557
2558 return result;
2559 }
2560
2561 VkResult
2562 tu_CreateComputePipelines(VkDevice device,
2563 VkPipelineCache pipelineCache,
2564 uint32_t count,
2565 const VkComputePipelineCreateInfo *pCreateInfos,
2566 const VkAllocationCallbacks *pAllocator,
2567 VkPipeline *pPipelines)
2568 {
2569 VkResult final_result = VK_SUCCESS;
2570
2571 for (uint32_t i = 0; i < count; i++) {
2572 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2573 &pCreateInfos[i],
2574 pAllocator, &pPipelines[i]);
2575 if (result != VK_SUCCESS)
2576 final_result = result;
2577 }
2578
2579 return final_result;
2580 }
2581
2582 void
2583 tu_DestroyPipeline(VkDevice _device,
2584 VkPipeline _pipeline,
2585 const VkAllocationCallbacks *pAllocator)
2586 {
2587 TU_FROM_HANDLE(tu_device, dev, _device);
2588 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2589
2590 if (!_pipeline)
2591 return;
2592
2593 tu_pipeline_finish(pipeline, dev, pAllocator);
2594 vk_free2(&dev->alloc, pAllocator, pipeline);
2595 }