projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
turnip: set missing bary sysvals
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static void
46 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
47 enum a6xx_state_block sb, unsigned base, unsigned offset,
48 unsigned count)
49 {
50 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
51 * clear if emitting more packets will even help anything. Presumably the
52 * descriptor cache is relatively small, and these packets stop doing
53 * anything when there are too many descriptors.
54 */
55 tu_cs_emit_pkt7(cs, opcode, 3);
56 tu_cs_emit(cs,
57 CP_LOAD_STATE6_0_STATE_TYPE(st) |
58 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
59 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
60 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
61 tu_cs_emit_qw(cs, offset | (base << 28));
62 }
63
64 static unsigned
65 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
66 {
67 const unsigned load_state_size = 4;
68 unsigned size = 0;
69 for (unsigned i = 0; i < layout->num_sets; i++) {
70 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
71 for (unsigned j = 0; j < set_layout->binding_count; j++) {
72 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
73 unsigned count = 0;
74 /* Note: some users, like amber for example, pass in
75 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
76 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
77 */
78 VkShaderStageFlags stages = compute ?
79 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
80 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
81 unsigned stage_count = util_bitcount(stages);
82 switch (binding->type) {
83 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
84 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
85 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
86 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
87 /* IBO-backed resources only need one packet for all graphics stages */
88 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
89 count += 1;
90 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
91 count += 1;
92 break;
93 case VK_DESCRIPTOR_TYPE_SAMPLER:
94 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
95 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
96 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
97 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
98 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
99 /* Textures and UBO's needs a packet for each stage */
100 count = stage_count;
101 break;
102 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
103 /* Because of how we pack combined images and samplers, we
104 * currently can't use one packet for the whole array.
105 */
106 count = stage_count * binding->array_size * 2;
107 break;
108 default:
109 unreachable("bad descriptor type");
110 }
111 size += count * load_state_size;
112 }
113 }
114 return size;
115 }
116
117 static void
118 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
119 {
120 unsigned size = tu6_load_state_size(pipeline->layout, compute);
121 if (size == 0)
122 return;
123
124 struct tu_cs cs;
125 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
126
127 struct tu_pipeline_layout *layout = pipeline->layout;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 /* From 13.2.7. Descriptor Set Binding:
130 *
131 * A compatible descriptor set must be bound for all set numbers that
132 * any shaders in a pipeline access, at the time that a draw or
133 * dispatch command is recorded to execute using that pipeline.
134 * However, if none of the shaders in a pipeline statically use any
135 * bindings with a particular set number, then no descriptor set need
136 * be bound for that set number, even if the pipeline layout includes
137 * a non-trivial descriptor set layout for that set number.
138 *
139 * This means that descriptor sets unused by the pipeline may have a
140 * garbage or 0 BINDLESS_BASE register, which will cause context faults
141 * when prefetching descriptors from these sets. Skip prefetching for
142 * descriptors from them to avoid this. This is also an optimization,
143 * since these prefetches would be useless.
144 */
145 if (!(pipeline->active_desc_sets & (1u << i)))
146 continue;
147
148 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
149 for (unsigned j = 0; j < set_layout->binding_count; j++) {
150 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
151 unsigned base = i;
152 unsigned offset = binding->offset / 4;
153 /* Note: some users, like amber for example, pass in
154 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
155 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
156 */
157 VkShaderStageFlags stages = compute ?
158 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
159 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
160 unsigned count = binding->array_size;
161 if (count == 0 || stages == 0)
162 continue;
163 switch (binding->type) {
164 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
165 base = MAX_SETS;
166 offset = (layout->set[i].dynamic_offset_start +
167 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
168 /* fallthrough */
169 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
170 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
171 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
172 /* IBO-backed resources only need one packet for all graphics stages */
173 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
174 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
175 base, offset, count);
176 }
177 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
178 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
179 base, offset, count);
180 }
181 break;
182 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
183 /* nothing - input attachment doesn't use bindless */
184 break;
185 case VK_DESCRIPTOR_TYPE_SAMPLER:
186 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
187 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
188 tu_foreach_stage(stage, stages) {
189 emit_load_state(&cs, tu6_stage2opcode(stage),
190 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
191 ST6_SHADER : ST6_CONSTANTS,
192 tu6_stage2texsb(stage), base, offset, count);
193 }
194 break;
195 }
196 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
197 base = MAX_SETS;
198 offset = (layout->set[i].dynamic_offset_start +
199 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
200 /* fallthrough */
201 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
202 tu_foreach_stage(stage, stages) {
203 emit_load_state(&cs, tu6_stage2opcode(stage), ST6_UBO,
204 tu6_stage2shadersb(stage), base, offset, count);
205 }
206 break;
207 }
208 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
209 tu_foreach_stage(stage, stages) {
210 /* TODO: We could emit less CP_LOAD_STATE6 if we used
211 * struct-of-arrays instead of array-of-structs.
212 */
213 for (unsigned i = 0; i < count; i++) {
214 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
215 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
216 emit_load_state(&cs, tu6_stage2opcode(stage),
217 ST6_CONSTANTS, tu6_stage2texsb(stage),
218 base, tex_offset, 1);
219 emit_load_state(&cs, tu6_stage2opcode(stage),
220 ST6_SHADER, tu6_stage2texsb(stage),
221 base, sam_offset, 1);
222 }
223 }
224 break;
225 }
226 default:
227 unreachable("bad descriptor type");
228 }
229 }
230 }
231
232 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
233 }
234
235 struct tu_pipeline_builder
236 {
237 struct tu_device *device;
238 struct tu_pipeline_cache *cache;
239 struct tu_pipeline_layout *layout;
240 const VkAllocationCallbacks *alloc;
241 const VkGraphicsPipelineCreateInfo *create_info;
242
243 struct tu_shader *shaders[MESA_SHADER_STAGES];
244 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
245 struct ir3_shader_variant *binning_variant;
246 uint64_t shader_iova[MESA_SHADER_STAGES];
247 uint64_t binning_vs_iova;
248
249 bool rasterizer_discard;
250 /* these states are affectd by rasterizer_discard */
251 VkSampleCountFlagBits samples;
252 bool use_color_attachments;
253 bool use_dual_src_blend;
254 uint32_t color_attachment_count;
255 VkFormat color_attachment_formats[MAX_RTS];
256 VkFormat depth_attachment_format;
257 uint32_t render_components;
258 };
259
260 static bool
261 tu_logic_op_reads_dst(VkLogicOp op)
262 {
263 switch (op) {
264 case VK_LOGIC_OP_CLEAR:
265 case VK_LOGIC_OP_COPY:
266 case VK_LOGIC_OP_COPY_INVERTED:
267 case VK_LOGIC_OP_SET:
268 return false;
269 default:
270 return true;
271 }
272 }
273
274 static VkBlendFactor
275 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
276 {
277 /* treat dst alpha as 1.0 and avoid reading it */
278 switch (factor) {
279 case VK_BLEND_FACTOR_DST_ALPHA:
280 return VK_BLEND_FACTOR_ONE;
281 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
282 return VK_BLEND_FACTOR_ZERO;
283 default:
284 return factor;
285 }
286 }
287
288 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
289 {
290 switch (factor) {
291 case VK_BLEND_FACTOR_SRC1_COLOR:
292 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
293 case VK_BLEND_FACTOR_SRC1_ALPHA:
294 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
295 return true;
296 default:
297 return false;
298 }
299 }
300
301 static bool
302 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
303 {
304 if (!info)
305 return false;
306
307 for (unsigned i = 0; i < info->attachmentCount; i++) {
308 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
309 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
310 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
311 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
312 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
313 return true;
314 }
315
316 return false;
317 }
318
319 void
320 tu6_emit_xs_config(struct tu_cs *cs,
321 gl_shader_stage stage, /* xs->type, but xs may be NULL */
322 const struct ir3_shader_variant *xs,
323 uint64_t binary_iova)
324 {
325 static const struct xs_config {
326 uint16_t reg_sp_xs_ctrl;
327 uint16_t reg_sp_xs_config;
328 uint16_t reg_hlsq_xs_ctrl;
329 uint16_t reg_sp_vs_obj_start;
330 } xs_config[] = {
331 [MESA_SHADER_VERTEX] = {
332 REG_A6XX_SP_VS_CTRL_REG0,
333 REG_A6XX_SP_VS_CONFIG,
334 REG_A6XX_HLSQ_VS_CNTL,
335 REG_A6XX_SP_VS_OBJ_START_LO,
336 },
337 [MESA_SHADER_TESS_CTRL] = {
338 REG_A6XX_SP_HS_CTRL_REG0,
339 REG_A6XX_SP_HS_CONFIG,
340 REG_A6XX_HLSQ_HS_CNTL,
341 REG_A6XX_SP_HS_OBJ_START_LO,
342 },
343 [MESA_SHADER_TESS_EVAL] = {
344 REG_A6XX_SP_DS_CTRL_REG0,
345 REG_A6XX_SP_DS_CONFIG,
346 REG_A6XX_HLSQ_DS_CNTL,
347 REG_A6XX_SP_DS_OBJ_START_LO,
348 },
349 [MESA_SHADER_GEOMETRY] = {
350 REG_A6XX_SP_GS_CTRL_REG0,
351 REG_A6XX_SP_GS_CONFIG,
352 REG_A6XX_HLSQ_GS_CNTL,
353 REG_A6XX_SP_GS_OBJ_START_LO,
354 },
355 [MESA_SHADER_FRAGMENT] = {
356 REG_A6XX_SP_FS_CTRL_REG0,
357 REG_A6XX_SP_FS_CONFIG,
358 REG_A6XX_HLSQ_FS_CNTL,
359 REG_A6XX_SP_FS_OBJ_START_LO,
360 },
361 [MESA_SHADER_COMPUTE] = {
362 REG_A6XX_SP_CS_CTRL_REG0,
363 REG_A6XX_SP_CS_CONFIG,
364 REG_A6XX_HLSQ_CS_CNTL,
365 REG_A6XX_SP_CS_OBJ_START_LO,
366 },
367 };
368 const struct xs_config *cfg = &xs_config[stage];
369
370 if (!xs) {
371 /* shader stage disabled */
372 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
373 tu_cs_emit(cs, 0);
374
375 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
376 tu_cs_emit(cs, 0);
377 return;
378 }
379
380 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
381 enum a3xx_threadsize threadsize = FOUR_QUADS;
382
383 /* TODO:
384 * the "threadsize" field may have nothing to do with threadsize,
385 * use a value that matches the blob until it is figured out
386 */
387 if (xs->type == MESA_SHADER_GEOMETRY)
388 threadsize = TWO_QUADS;
389
390 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
391 tu_cs_emit(cs,
392 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
393 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
394 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs->info.max_half_reg + 1) |
395 COND(xs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
396 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
397 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
398 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
399 /* only fragment shader sets VARYING bit */
400 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
401 /* unknown bit, seems unnecessary */
402 COND(is_fs, 0x1000000));
403
404 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
405 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
406 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
407 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
408 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
409 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
410 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
411 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
412 tu_cs_emit(cs, xs->instrlen);
413
414 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
415 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) |
416 A6XX_HLSQ_VS_CNTL_ENABLED);
417
418 /* emit program binary
419 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
420 */
421
422 assert((binary_iova & 0x7f) == 0);
423
424 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
425 tu_cs_emit_qw(cs, binary_iova);
426
427 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
428 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
429 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
430 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
431 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
432 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
433 tu_cs_emit_qw(cs, binary_iova);
434
435 /* emit immediates */
436
437 const struct ir3_const_state *const_state = ir3_const_state(xs);
438 uint32_t base = const_state->offsets.immediate;
439 int size = const_state->immediates_count;
440
441 /* truncate size to avoid writing constants that shader
442 * does not use:
443 */
444 size = MIN2(size + base, xs->constlen) - base;
445
446 if (size <= 0)
447 return;
448
449 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + size * 4);
450 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
451 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
452 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
453 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
454 CP_LOAD_STATE6_0_NUM_UNIT(size));
455 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
456 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
457
458 for (unsigned i = 0; i < size; i++) {
459 tu_cs_emit(cs, const_state->immediates[i].val[0]);
460 tu_cs_emit(cs, const_state->immediates[i].val[1]);
461 tu_cs_emit(cs, const_state->immediates[i].val[2]);
462 tu_cs_emit(cs, const_state->immediates[i].val[3]);
463 }
464 }
465
466 static void
467 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
468 const struct ir3_shader_variant *v,
469 uint32_t binary_iova)
470 {
471 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
472 tu_cs_emit(cs, 0xff);
473
474 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
475
476 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
477 tu_cs_emit(cs, 0x41);
478
479 uint32_t local_invocation_id =
480 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
481 uint32_t work_group_id =
482 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
483
484 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
485 tu_cs_emit(cs,
486 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
487 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
488 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
489 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
490 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
491 }
492
493 static void
494 tu6_emit_vs_system_values(struct tu_cs *cs,
495 const struct ir3_shader_variant *vs,
496 const struct ir3_shader_variant *hs,
497 const struct ir3_shader_variant *ds,
498 const struct ir3_shader_variant *gs,
499 bool primid_passthru)
500 {
501 const uint32_t vertexid_regid =
502 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
503 const uint32_t instanceid_regid =
504 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
505 const uint32_t tess_coord_x_regid = hs ?
506 ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD) :
507 regid(63, 0);
508 const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ?
509 tess_coord_x_regid + 1 :
510 regid(63, 0);
511 const uint32_t hs_patch_regid = hs ?
512 ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
513 regid(63, 0);
514 const uint32_t ds_patch_regid = hs ?
515 ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
516 regid(63, 0);
517 const uint32_t hs_invocation_regid = hs ?
518 ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) :
519 regid(63, 0);
520 const uint32_t primitiveid_regid = gs ?
521 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
522 regid(63, 0);
523 const uint32_t gsheader_regid = gs ?
524 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
525 regid(63, 0);
526
527 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
528 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
529 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
530 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
531 0xfc000000);
532 tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
533 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
534 tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
535 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
536 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
537 0xfc);
538 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
539 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
540 0xfc00); /* VFD_CONTROL_5 */
541 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
542 }
543
544 /* Add any missing varyings needed for stream-out. Otherwise varyings not
545 * used by fragment shader will be stripped out.
546 */
547 static void
548 tu6_link_streamout(struct ir3_shader_linkage *l,
549 const struct ir3_shader_variant *v)
550 {
551 const struct ir3_stream_output_info *info = &v->shader->stream_output;
552
553 /*
554 * First, any stream-out varyings not already in linkage map (ie. also
555 * consumed by frag shader) need to be added:
556 */
557 for (unsigned i = 0; i < info->num_outputs; i++) {
558 const struct ir3_stream_output *out = &info->output[i];
559 unsigned compmask =
560 (1 << (out->num_components + out->start_component)) - 1;
561 unsigned k = out->register_index;
562 unsigned idx, nextloc = 0;
563
564 /* psize/pos need to be the last entries in linkage map, and will
565 * get added link_stream_out, so skip over them:
566 */
567 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
568 v->outputs[k].slot == VARYING_SLOT_POS)
569 continue;
570
571 for (idx = 0; idx < l->cnt; idx++) {
572 if (l->var[idx].regid == v->outputs[k].regid)
573 break;
574 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
575 }
576
577 /* add if not already in linkage map: */
578 if (idx == l->cnt)
579 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
580
581 /* expand component-mask if needed, ie streaming out all components
582 * but frag shader doesn't consume all components:
583 */
584 if (compmask & ~l->var[idx].compmask) {
585 l->var[idx].compmask |= compmask;
586 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
587 util_last_bit(l->var[idx].compmask));
588 }
589 }
590 }
591
592 static void
593 tu6_setup_streamout(struct tu_cs *cs,
594 const struct ir3_shader_variant *v,
595 struct ir3_shader_linkage *l)
596 {
597 const struct ir3_stream_output_info *info = &v->shader->stream_output;
598 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2] = {};
599 uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {};
600 uint32_t prog_count = align(l->max_loc, 2) / 2;
601
602 /* TODO: streamout state should be in a non-GMEM draw state */
603
604 /* no streamout: */
605 if (info->num_outputs == 0) {
606 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
607 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
608 tu_cs_emit(cs, 0);
609 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
610 tu_cs_emit(cs, 0);
611 return;
612 }
613
614 /* is there something to do with info->stride[i]? */
615
616 for (unsigned i = 0; i < info->num_outputs; i++) {
617 const struct ir3_stream_output *out = &info->output[i];
618 unsigned k = out->register_index;
619 unsigned idx;
620
621 /* Skip it, if there's an unused reg in the middle of outputs. */
622 if (v->outputs[k].regid == INVALID_REG)
623 continue;
624
625 ncomp[out->output_buffer] += out->num_components;
626
627 /* linkage map sorted by order frag shader wants things, so
628 * a bit less ideal here..
629 */
630 for (idx = 0; idx < l->cnt; idx++)
631 if (l->var[idx].regid == v->outputs[k].regid)
632 break;
633
634 debug_assert(idx < l->cnt);
635
636 for (unsigned j = 0; j < out->num_components; j++) {
637 unsigned c = j + out->start_component;
638 unsigned loc = l->var[idx].loc + c;
639 unsigned off = j + out->dst_offset; /* in dwords */
640
641 if (loc & 1) {
642 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
643 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
644 A6XX_VPC_SO_PROG_B_OFF(off * 4);
645 } else {
646 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
647 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
648 A6XX_VPC_SO_PROG_A_OFF(off * 4);
649 }
650 }
651 }
652
653 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count);
654 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
655 tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE |
656 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
657 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
658 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
659 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
660 for (uint32_t i = 0; i < 4; i++) {
661 tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
662 tu_cs_emit(cs, ncomp[i]);
663 }
664 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
665 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
666 tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
667 for (uint32_t i = 0; i < prog_count; i++) {
668 tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
669 tu_cs_emit(cs, prog[i]);
670 }
671 }
672
673 static void
674 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
675 enum a6xx_state_block block, uint32_t offset,
676 uint32_t size, uint32_t *dwords) {
677 assert(size % 4 == 0);
678
679 tu_cs_emit_pkt7(cs, opcode, 3 + size);
680 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
681 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
682 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
683 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
684 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
685
686 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
687 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
688 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
689
690 tu_cs_emit_array(cs, dwords, size);
691 }
692
693 static void
694 tu6_emit_link_map(struct tu_cs *cs,
695 const struct ir3_shader_variant *producer,
696 const struct ir3_shader_variant *consumer,
697 enum a6xx_state_block sb)
698 {
699 const struct ir3_const_state *const_state = ir3_const_state(consumer);
700 uint32_t base = const_state->offsets.primitive_map;
701 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
702 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
703 int size = DIV_ROUND_UP(num_loc, 4);
704
705 size = (MIN2(size + base, consumer->constlen) - base) * 4;
706 if (size <= 0)
707 return;
708
709 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, sb, 0, size,
710 patch_locs);
711 }
712
713 static uint16_t
714 gl_primitive_to_tess(uint16_t primitive) {
715 switch (primitive) {
716 case GL_POINTS:
717 return TESS_POINTS;
718 case GL_LINE_STRIP:
719 return TESS_LINES;
720 case GL_TRIANGLE_STRIP:
721 return TESS_CW_TRIS;
722 default:
723 unreachable("");
724 }
725 }
726
727 void
728 tu6_emit_vpc(struct tu_cs *cs,
729 const struct ir3_shader_variant *vs,
730 const struct ir3_shader_variant *hs,
731 const struct ir3_shader_variant *ds,
732 const struct ir3_shader_variant *gs,
733 const struct ir3_shader_variant *fs)
734 {
735 const struct ir3_shader_variant *last_shader;
736 if (gs) {
737 last_shader = gs;
738 } else if (hs) {
739 last_shader = ds;
740 } else {
741 last_shader = vs;
742 }
743 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
744 if (fs)
745 ir3_link_shaders(&linkage, last_shader, fs, true);
746
747 if (last_shader->shader->stream_output.num_outputs)
748 tu6_link_streamout(&linkage, last_shader);
749
750 /* We do this after linking shaders in order to know whether PrimID
751 * passthrough needs to be enabled.
752 */
753 bool primid_passthru = linkage.primid_loc != 0xff;
754 tu6_emit_vs_system_values(cs, vs, hs, ds, gs, primid_passthru);
755
756 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
757 tu_cs_emit(cs, ~linkage.varmask[0]);
758 tu_cs_emit(cs, ~linkage.varmask[1]);
759 tu_cs_emit(cs, ~linkage.varmask[2]);
760 tu_cs_emit(cs, ~linkage.varmask[3]);
761
762 /* a6xx finds position/pointsize at the end */
763 const uint32_t position_regid =
764 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
765 const uint32_t pointsize_regid =
766 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
767 const uint32_t layer_regid = gs ?
768 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
769
770 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
771 if (layer_regid != regid(63, 0)) {
772 layer_loc = linkage.max_loc;
773 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
774 }
775 if (position_regid != regid(63, 0)) {
776 position_loc = linkage.max_loc;
777 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
778 }
779 if (pointsize_regid != regid(63, 0)) {
780 pointsize_loc = linkage.max_loc;
781 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
782 }
783
784 tu6_setup_streamout(cs, last_shader, &linkage);
785
786 /* map outputs of the last shader to VPC */
787 assert(linkage.cnt <= 32);
788 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
789 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
790 uint32_t sp_out[16];
791 uint32_t sp_vpc_dst[8];
792 for (uint32_t i = 0; i < linkage.cnt; i++) {
793 ((uint16_t *) sp_out)[i] =
794 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
795 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
796 ((uint8_t *) sp_vpc_dst)[i] =
797 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
798 }
799
800 if (gs)
801 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
802 else if (hs)
803 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_OUT_REG(0), sp_out_count);
804 else
805 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
806 tu_cs_emit_array(cs, sp_out, sp_out_count);
807
808 if (gs)
809 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
810 else if (hs)
811 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_VPC_DST_REG(0), sp_vpc_dst_count);
812 else
813 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
814 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
815
816 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
817 tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
818
819 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
820 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
821 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
822 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
823 A6XX_VPC_CNTL_0_UNKLOC(0xff));
824
825 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
826 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
827 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
828 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
829
830 if (hs) {
831 shader_info *hs_info = &hs->shader->nir->info;
832 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
833 tu_cs_emit(cs, hs_info->tess.tcs_vertices_out);
834
835 /* Total attribute slots in HS incoming patch. */
836 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9801, 1);
837 tu_cs_emit(cs,
838 hs_info->tess.tcs_vertices_out * vs->output_size / 4);
839
840 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
841 tu_cs_emit(cs, vs->output_size);
842 /* In SPIR-V generated from GLSL, the tessellation primitive params are
843 * are specified in the tess eval shader, but in SPIR-V generated from
844 * HLSL, they are specified in the tess control shader. */
845 shader_info *tess_info =
846 ds->shader->nir->info.tess.spacing == TESS_SPACING_UNSPECIFIED ?
847 &hs->shader->nir->info : &ds->shader->nir->info;
848 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_CNTL, 1);
849 uint32_t output;
850 if (tess_info->tess.point_mode)
851 output = TESS_POINTS;
852 else if (tess_info->tess.primitive_mode == GL_ISOLINES)
853 output = TESS_LINES;
854 else if (tess_info->tess.ccw)
855 output = TESS_CCW_TRIS;
856 else
857 output = TESS_CW_TRIS;
858
859 enum a6xx_tess_spacing spacing;
860 switch (tess_info->tess.spacing) {
861 case TESS_SPACING_EQUAL:
862 spacing = TESS_EQUAL;
863 break;
864 case TESS_SPACING_FRACTIONAL_ODD:
865 spacing = TESS_FRACTIONAL_ODD;
866 break;
867 case TESS_SPACING_FRACTIONAL_EVEN:
868 spacing = TESS_FRACTIONAL_EVEN;
869 break;
870 case TESS_SPACING_UNSPECIFIED:
871 default:
872 unreachable("invalid tess spacing");
873 }
874 tu_cs_emit(cs, A6XX_PC_TESS_CNTL_SPACING(spacing) |
875 A6XX_PC_TESS_CNTL_OUTPUT(output));
876
877 /* xxx: Misc tess unknowns: */
878 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9103, 1);
879 tu_cs_emit(cs, 0x00ffff00);
880
881 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9106, 1);
882 tu_cs_emit(cs, 0x0000ffff);
883
884 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809D, 1);
885 tu_cs_emit(cs, 0x0);
886
887 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8002, 1);
888 tu_cs_emit(cs, 0x0);
889
890 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
891 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
892 A6XX_VPC_PACK_PSIZELOC(255) |
893 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
894
895 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_3, 1);
896 tu_cs_emit(cs, A6XX_VPC_PACK_3_POSITIONLOC(position_loc) |
897 A6XX_VPC_PACK_3_PSIZELOC(pointsize_loc) |
898 A6XX_VPC_PACK_3_STRIDE_IN_VPC(linkage.max_loc));
899
900 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
901 tu_cs_emit(cs, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(linkage.cnt));
902
903 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1);
904 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(linkage.max_loc) |
905 CONDREG(pointsize_regid, 0x100));
906
907 tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
908 tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER);
909 }
910
911
912 if (gs) {
913 uint32_t vertices_out, invocations, output, vec4_size;
914 /* this detects the tu_clear_blit path, which doesn't set ->nir */
915 if (gs->shader->nir) {
916 if (hs) {
917 tu6_emit_link_map(cs, ds, gs, SB6_GS_SHADER);
918 } else {
919 tu6_emit_link_map(cs, vs, gs, SB6_GS_SHADER);
920 }
921 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
922 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
923 invocations = gs->shader->nir->info.gs.invocations - 1;
924 /* Size of per-primitive alloction in ldlw memory in vec4s. */
925 vec4_size = gs->shader->nir->info.gs.vertices_in *
926 DIV_ROUND_UP(vs->output_size, 4);
927 } else {
928 vertices_out = 3;
929 output = TESS_CW_TRIS;
930 invocations = 0;
931 vec4_size = 0;
932 }
933
934 uint32_t primitive_regid =
935 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
936 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
937 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
938 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
939 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
940
941 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
942 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
943
944 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
945 tu_cs_emit(cs, CONDREG(layer_regid,
946 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
947
948 uint32_t flags_regid = ir3_find_output_regid(gs,
949 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
950
951 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
952 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
953 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
954
955 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
956 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
957 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
958 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
959 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
960
961 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
962 tu_cs_emit(cs,
963 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
964 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
965 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
966
967 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
968 tu_cs_emit(cs, 0);
969
970 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
971 tu_cs_emit(cs, 0);
972
973 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
974 tu_cs_emit(cs, 0xff);
975
976 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
977 tu_cs_emit(cs, 0xffff00);
978
979 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
980 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
981
982 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
983 tu_cs_emit(cs, 0);
984
985 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
986 tu_cs_emit(cs, vs->output_size);
987 }
988
989 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
990 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
991
992 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
993 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
994 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
995 }
996
997 static int
998 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
999 uint32_t index,
1000 uint8_t *interp_mode,
1001 uint8_t *ps_repl_mode)
1002 {
1003 enum
1004 {
1005 INTERP_SMOOTH = 0,
1006 INTERP_FLAT = 1,
1007 INTERP_ZERO = 2,
1008 INTERP_ONE = 3,
1009 };
1010 enum
1011 {
1012 PS_REPL_NONE = 0,
1013 PS_REPL_S = 1,
1014 PS_REPL_T = 2,
1015 PS_REPL_ONE_MINUS_T = 3,
1016 };
1017
1018 const uint32_t compmask = fs->inputs[index].compmask;
1019
1020 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1021 * fourth component occupy three consecutive varying slots
1022 */
1023 int shift = 0;
1024 *interp_mode = 0;
1025 *ps_repl_mode = 0;
1026 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1027 if (compmask & 0x1) {
1028 *ps_repl_mode |= PS_REPL_S << shift;
1029 shift += 2;
1030 }
1031 if (compmask & 0x2) {
1032 *ps_repl_mode |= PS_REPL_T << shift;
1033 shift += 2;
1034 }
1035 if (compmask & 0x4) {
1036 *interp_mode |= INTERP_ZERO << shift;
1037 shift += 2;
1038 }
1039 if (compmask & 0x8) {
1040 *interp_mode |= INTERP_ONE << 6;
1041 shift += 2;
1042 }
1043 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1044 fs->inputs[index].rasterflat) {
1045 for (int i = 0; i < 4; i++) {
1046 if (compmask & (1 << i)) {
1047 *interp_mode |= INTERP_FLAT << shift;
1048 shift += 2;
1049 }
1050 }
1051 }
1052
1053 return shift;
1054 }
1055
1056 static void
1057 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1058 const struct ir3_shader_variant *fs)
1059 {
1060 uint32_t interp_modes[8] = { 0 };
1061 uint32_t ps_repl_modes[8] = { 0 };
1062
1063 if (fs) {
1064 for (int i = -1;
1065 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1066
1067 /* get the mode for input i */
1068 uint8_t interp_mode;
1069 uint8_t ps_repl_mode;
1070 const int bits =
1071 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1072
1073 /* OR the mode into the array */
1074 const uint32_t inloc = fs->inputs[i].inloc * 2;
1075 uint32_t n = inloc / 32;
1076 uint32_t shift = inloc % 32;
1077 interp_modes[n] |= interp_mode << shift;
1078 ps_repl_modes[n] |= ps_repl_mode << shift;
1079 if (shift + bits > 32) {
1080 n++;
1081 shift = 32 - shift;
1082
1083 interp_modes[n] |= interp_mode >> shift;
1084 ps_repl_modes[n] |= ps_repl_mode >> shift;
1085 }
1086 }
1087 }
1088
1089 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1090 tu_cs_emit_array(cs, interp_modes, 8);
1091
1092 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1093 tu_cs_emit_array(cs, ps_repl_modes, 8);
1094 }
1095
1096 void
1097 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1098 {
1099 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1100 uint32_t ij_regid[IJ_COUNT];
1101 uint32_t smask_in_regid;
1102
1103 bool sample_shading = fs->per_samp | fs->key.sample_shading;
1104 bool enable_varyings = fs->total_in > 0;
1105
1106 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1107 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1108 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1109 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1110 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1111 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
1112 ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
1113
1114 if (VALIDREG(ij_regid[IJ_LINEAR_SAMPLE]))
1115 tu_finishme("linear sample varying");
1116
1117 if (VALIDREG(ij_regid[IJ_LINEAR_CENTROID]))
1118 tu_finishme("linear centroid varying");
1119
1120 if (fs->num_sampler_prefetch > 0) {
1121 assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
1122 /* also, it seems like ij_pix is *required* to be r0.x */
1123 assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
1124 }
1125
1126 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1127 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1128 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1129 0x7000); // XXX);
1130 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1131 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1132 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1133 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1134 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1135 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1136 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1137 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1138 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1139 }
1140
1141 if (fs->num_sampler_prefetch > 0) {
1142 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1143 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1144 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1145 tu_cs_emit(cs,
1146 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1147 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1148 }
1149 }
1150
1151 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1152 tu_cs_emit(cs, 0x7);
1153 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1154 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1155 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1156 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
1157 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
1158 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
1159 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
1160 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
1161 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1162 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1163 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
1164 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
1165 tu_cs_emit(cs, 0xfc);
1166
1167 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1168 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1169
1170 bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
1171 bool need_size_persamp = false;
1172 if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
1173 if (sample_shading)
1174 need_size_persamp = true;
1175 else
1176 need_size = true;
1177 }
1178 if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
1179 need_size = true;
1180
1181 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1182 tu_cs_emit(cs,
1183 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
1184 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
1185 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
1186 COND(need_size, A6XX_GRAS_CNTL_SIZE) |
1187 COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1188 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
1189
1190 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1191 tu_cs_emit(cs,
1192 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
1193 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
1194 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
1195 COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
1196 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1197 COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1198 COND(fs->fragcoord_compmask != 0,
1199 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
1200 tu_cs_emit(cs,
1201 /* these two bits (UNK4/UNK5) relate to fragcoord
1202 * without them, fragcoord is the same for all samples
1203 */
1204 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) |
1205 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) |
1206 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1207 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1208 CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
1209 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1210
1211 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1212 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1213
1214 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1215 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1216
1217 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1218 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1219 }
1220
1221 static void
1222 tu6_emit_fs_outputs(struct tu_cs *cs,
1223 const struct ir3_shader_variant *fs,
1224 uint32_t mrt_count, bool dual_src_blend,
1225 uint32_t render_components,
1226 bool is_s8_uint)
1227 {
1228 uint32_t smask_regid, posz_regid;
1229
1230 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1231 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1232
1233 uint32_t fragdata_regid[8];
1234 if (fs->color0_mrt) {
1235 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1236 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1237 fragdata_regid[i] = fragdata_regid[0];
1238 } else {
1239 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1240 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1241 }
1242
1243 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1244 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1245 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1246 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
1247 0xfc000000);
1248 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1249
1250 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1251 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1252 // TODO we could have a mix of half and full precision outputs,
1253 // we really need to figure out half-precision from IR3_REG_HALF
1254 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1255 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1256 }
1257
1258 tu_cs_emit_regs(cs,
1259 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1260
1261 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1262 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1263 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1264 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1265 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1266
1267 tu_cs_emit_regs(cs,
1268 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1269
1270 enum a6xx_ztest_mode zmode;
1271
1272 if (fs->no_earlyz || fs->has_kill || fs->writes_pos || is_s8_uint) {
1273 zmode = A6XX_LATE_Z;
1274 } else {
1275 zmode = A6XX_EARLY_Z;
1276 }
1277
1278 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1279 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1280
1281 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1282 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1283 }
1284
1285 static void
1286 tu6_emit_geom_tess_consts(struct tu_cs *cs,
1287 const struct ir3_shader_variant *vs,
1288 const struct ir3_shader_variant *hs,
1289 const struct ir3_shader_variant *ds,
1290 const struct ir3_shader_variant *gs,
1291 uint32_t cps_per_patch)
1292 {
1293 uint32_t num_vertices =
1294 hs ? cps_per_patch : gs->shader->nir->info.gs.vertices_in;
1295
1296 uint32_t vs_params[4] = {
1297 vs->output_size * num_vertices * 4, /* vs primitive stride */
1298 vs->output_size * 4, /* vs vertex stride */
1299 0,
1300 0,
1301 };
1302 uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param;
1303 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1304 ARRAY_SIZE(vs_params), vs_params);
1305
1306 if (hs) {
1307 assert(ds->type != MESA_SHADER_NONE);
1308 uint32_t hs_params[4] = {
1309 vs->output_size * num_vertices * 4, /* hs primitive stride */
1310 vs->output_size * 4, /* hs vertex stride */
1311 hs->output_size,
1312 cps_per_patch,
1313 };
1314
1315 uint32_t hs_base = hs->const_state->offsets.primitive_param;
1316 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, hs_base, SB6_HS_SHADER, 0,
1317 ARRAY_SIZE(hs_params), hs_params);
1318 if (gs)
1319 num_vertices = gs->shader->nir->info.gs.vertices_in;
1320
1321 uint32_t ds_params[4] = {
1322 ds->output_size * num_vertices * 4, /* ds primitive stride */
1323 ds->output_size * 4, /* ds vertex stride */
1324 hs->output_size, /* hs vertex stride (dwords) */
1325 hs->shader->nir->info.tess.tcs_vertices_out
1326 };
1327
1328 uint32_t ds_base = ds->const_state->offsets.primitive_param;
1329 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, ds_base, SB6_DS_SHADER, 0,
1330 ARRAY_SIZE(ds_params), ds_params);
1331 }
1332
1333 if (gs) {
1334 const struct ir3_shader_variant *prev = ds ? ds : vs;
1335 uint32_t gs_params[4] = {
1336 prev->output_size * num_vertices * 4, /* gs primitive stride */
1337 prev->output_size * 4, /* gs vertex stride */
1338 0,
1339 0,
1340 };
1341 uint32_t gs_base = gs->const_state->offsets.primitive_param;
1342 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1343 ARRAY_SIZE(gs_params), gs_params);
1344 }
1345 }
1346
1347 static void
1348 tu6_emit_program(struct tu_cs *cs,
1349 struct tu_pipeline_builder *builder,
1350 bool binning_pass)
1351 {
1352 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
1353 const struct ir3_shader_variant *bs = builder->binning_variant;
1354 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
1355 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
1356 const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
1357 const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
1358 gl_shader_stage stage = MESA_SHADER_VERTEX;
1359
1360 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1361
1362 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1363 tu_cs_emit(cs, 0xff); /* XXX */
1364
1365 /* Don't use the binning pass variant when GS is present because we don't
1366 * support compiling correct binning pass variants with GS.
1367 */
1368 if (binning_pass && !gs) {
1369 vs = bs;
1370 tu6_emit_xs_config(cs, stage, bs, builder->binning_vs_iova);
1371 stage++;
1372 }
1373
1374 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1375 const struct ir3_shader_variant *xs = builder->variants[stage];
1376
1377 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1378 fs = xs = NULL;
1379
1380 tu6_emit_xs_config(cs, stage, xs, builder->shader_iova[stage]);
1381 }
1382
1383 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1384 tu_cs_emit(cs, 0);
1385
1386 tu6_emit_vpc(cs, vs, hs, ds, gs, fs);
1387 tu6_emit_vpc_varying_modes(cs, fs);
1388
1389 if (fs) {
1390 tu6_emit_fs_inputs(cs, fs);
1391 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1392 builder->use_dual_src_blend,
1393 builder->render_components,
1394 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1395 } else {
1396 /* TODO: check if these can be skipped if fs is disabled */
1397 struct ir3_shader_variant dummy_variant = {};
1398 tu6_emit_fs_inputs(cs, &dummy_variant);
1399 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1400 builder->use_dual_src_blend,
1401 builder->render_components,
1402 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1403 }
1404
1405 if (gs || hs) {
1406 uint32_t cps_per_patch = builder->create_info->pTessellationState ?
1407 builder->create_info->pTessellationState->patchControlPoints : 0;
1408 tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch);
1409 }
1410 }
1411
1412 static void
1413 tu6_emit_vertex_input(struct tu_cs *cs,
1414 const struct ir3_shader_variant *vs,
1415 const VkPipelineVertexInputStateCreateInfo *info,
1416 uint32_t *bindings_used)
1417 {
1418 uint32_t vfd_decode_idx = 0;
1419 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1420 uint32_t step_rate[MAX_VBS];
1421
1422 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1423 const VkVertexInputBindingDescription *binding =
1424 &info->pVertexBindingDescriptions[i];
1425
1426 tu_cs_emit_regs(cs,
1427 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1428
1429 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1430 binding_instanced |= 1 << binding->binding;
1431
1432 *bindings_used |= 1 << binding->binding;
1433 step_rate[binding->binding] = 1;
1434 }
1435
1436 const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_state =
1437 vk_find_struct_const(info->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1438 if (div_state) {
1439 for (uint32_t i = 0; i < div_state->vertexBindingDivisorCount; i++) {
1440 const VkVertexInputBindingDivisorDescriptionEXT *desc =
1441 &div_state->pVertexBindingDivisors[i];
1442 step_rate[desc->binding] = desc->divisor;
1443 }
1444 }
1445
1446 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1447
1448 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1449 const VkVertexInputAttributeDescription *attr =
1450 &info->pVertexAttributeDescriptions[i];
1451 uint32_t input_idx;
1452
1453 assert(*bindings_used & BIT(attr->binding));
1454
1455 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1456 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1457 break;
1458 }
1459
1460 /* attribute not used, skip it */
1461 if (input_idx == vs->inputs_count)
1462 continue;
1463
1464 const struct tu_native_format format = tu6_format_vtx(attr->format);
1465 tu_cs_emit_regs(cs,
1466 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1467 .idx = attr->binding,
1468 .offset = attr->offset,
1469 .instanced = binding_instanced & (1 << attr->binding),
1470 .format = format.fmt,
1471 .swap = format.swap,
1472 .unk30 = 1,
1473 ._float = !vk_format_is_int(attr->format)),
1474 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, step_rate[attr->binding]));
1475
1476 tu_cs_emit_regs(cs,
1477 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1478 .writemask = vs->inputs[input_idx].compmask,
1479 .regid = vs->inputs[input_idx].regid));
1480
1481 vfd_decode_idx++;
1482 }
1483
1484 tu_cs_emit_regs(cs,
1485 A6XX_VFD_CONTROL_0(
1486 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1487 .decode_cnt = vfd_decode_idx));
1488 }
1489
1490 static uint32_t
1491 tu6_guardband_adj(uint32_t v)
1492 {
1493 if (v > 256)
1494 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1495 else
1496 return 511;
1497 }
1498
1499 void
1500 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1501 {
1502 float offsets[3];
1503 float scales[3];
1504 scales[0] = viewport->width / 2.0f;
1505 scales[1] = viewport->height / 2.0f;
1506 scales[2] = viewport->maxDepth - viewport->minDepth;
1507 offsets[0] = viewport->x + scales[0];
1508 offsets[1] = viewport->y + scales[1];
1509 offsets[2] = viewport->minDepth;
1510
1511 VkOffset2D min;
1512 VkOffset2D max;
1513 min.x = (int32_t) viewport->x;
1514 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1515 if (viewport->height >= 0.0f) {
1516 min.y = (int32_t) viewport->y;
1517 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1518 } else {
1519 min.y = (int32_t)(viewport->y + viewport->height);
1520 max.y = (int32_t) ceilf(viewport->y);
1521 }
1522 /* the spec allows viewport->height to be 0.0f */
1523 if (min.y == max.y)
1524 max.y++;
1525 assert(min.x >= 0 && min.x < max.x);
1526 assert(min.y >= 0 && min.y < max.y);
1527
1528 VkExtent2D guardband_adj;
1529 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1530 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1531
1532 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1533 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1534 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1535 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1536 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1537 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1538 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1539
1540 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1541 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1542 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1543 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1544 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1545
1546 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1547 tu_cs_emit(cs,
1548 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1549 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1550
1551 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1552 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1553
1554 tu_cs_emit_regs(cs,
1555 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1556 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1557
1558 tu_cs_emit_regs(cs,
1559 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1560 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1561 }
1562
1563 void
1564 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1565 {
1566 VkOffset2D min = scissor->offset;
1567 VkOffset2D max = {
1568 scissor->offset.x + scissor->extent.width,
1569 scissor->offset.y + scissor->extent.height,
1570 };
1571
1572 /* special case for empty scissor with max == 0 to avoid overflow */
1573 if (max.x == 0)
1574 min.x = max.x = 1;
1575 if (max.y == 0)
1576 min.y = max.y = 1;
1577
1578 /* avoid overflow with large scissor
1579 * note the max will be limited to min - 1, so that empty scissor works
1580 */
1581 uint32_t scissor_max = BITFIELD_MASK(15);
1582 min.x = MIN2(scissor_max, min.x);
1583 min.y = MIN2(scissor_max, min.y);
1584 max.x = MIN2(scissor_max, max.x);
1585 max.y = MIN2(scissor_max, max.y);
1586
1587 tu_cs_emit_regs(cs,
1588 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0(.x = min.x, .y = min.y),
1589 A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0(.x = max.x - 1, .y = max.y - 1));
1590 }
1591
1592 void
1593 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1594 {
1595 if (!samp_loc) {
1596 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1597 tu_cs_emit(cs, 0);
1598
1599 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1600 tu_cs_emit(cs, 0);
1601
1602 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1603 tu_cs_emit(cs, 0);
1604 return;
1605 }
1606
1607 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1608 assert(samp_loc->sampleLocationGridSize.width == 1);
1609 assert(samp_loc->sampleLocationGridSize.height == 1);
1610
1611 uint32_t sample_config =
1612 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1613 uint32_t sample_locations = 0;
1614 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1615 sample_locations |=
1616 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1617 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1618 }
1619
1620 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1621 tu_cs_emit(cs, sample_config);
1622 tu_cs_emit(cs, sample_locations);
1623
1624 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1625 tu_cs_emit(cs, sample_config);
1626 tu_cs_emit(cs, sample_locations);
1627
1628 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1629 tu_cs_emit(cs, sample_config);
1630 tu_cs_emit(cs, sample_locations);
1631 }
1632
1633 static uint32_t
1634 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1635 VkSampleCountFlagBits samples)
1636 {
1637 uint32_t gras_su_cntl = 0;
1638
1639 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1640 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1641 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1642 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1643
1644 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1645 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1646
1647 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1648
1649 if (rast_info->depthBiasEnable)
1650 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1651
1652 if (samples > VK_SAMPLE_COUNT_1_BIT)
1653 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1654
1655 return gras_su_cntl;
1656 }
1657
1658 void
1659 tu6_emit_depth_bias(struct tu_cs *cs,
1660 float constant_factor,
1661 float clamp,
1662 float slope_factor)
1663 {
1664 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1665 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1666 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1667 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1668 }
1669
1670 static void
1671 tu6_emit_depth_control(struct tu_cs *cs,
1672 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1673 const VkPipelineRasterizationStateCreateInfo *rast_info)
1674 {
1675 uint32_t rb_depth_cntl = 0;
1676 if (ds_info->depthTestEnable) {
1677 rb_depth_cntl |=
1678 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1679 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1680 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
1681
1682 if (rast_info->depthClampEnable)
1683 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1684
1685 if (ds_info->depthWriteEnable)
1686 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1687 }
1688
1689 if (ds_info->depthBoundsTestEnable)
1690 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1691
1692 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1693 tu_cs_emit(cs, rb_depth_cntl);
1694 }
1695
1696 static void
1697 tu6_emit_stencil_control(struct tu_cs *cs,
1698 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1699 {
1700 uint32_t rb_stencil_control = 0;
1701 if (ds_info->stencilTestEnable) {
1702 const VkStencilOpState *front = &ds_info->front;
1703 const VkStencilOpState *back = &ds_info->back;
1704 rb_stencil_control |=
1705 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1706 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1707 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1708 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1709 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1710 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1711 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1712 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1713 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1714 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1715 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1716 }
1717
1718 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1719 tu_cs_emit(cs, rb_stencil_control);
1720 }
1721
1722 static uint32_t
1723 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1724 bool has_alpha)
1725 {
1726 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1727 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1728 has_alpha ? att->srcColorBlendFactor
1729 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1730 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1731 has_alpha ? att->dstColorBlendFactor
1732 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1733 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1734 const enum adreno_rb_blend_factor src_alpha_factor =
1735 tu6_blend_factor(att->srcAlphaBlendFactor);
1736 const enum adreno_rb_blend_factor dst_alpha_factor =
1737 tu6_blend_factor(att->dstAlphaBlendFactor);
1738
1739 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1740 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1741 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1742 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1743 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1744 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1745 }
1746
1747 static uint32_t
1748 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1749 uint32_t rb_mrt_control_rop,
1750 bool is_int,
1751 bool has_alpha)
1752 {
1753 uint32_t rb_mrt_control =
1754 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1755
1756 /* ignore blending and logic op for integer attachments */
1757 if (is_int) {
1758 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1759 return rb_mrt_control;
1760 }
1761
1762 rb_mrt_control |= rb_mrt_control_rop;
1763
1764 if (att->blendEnable) {
1765 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1766
1767 if (has_alpha)
1768 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1769 }
1770
1771 return rb_mrt_control;
1772 }
1773
1774 static void
1775 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1776 const VkPipelineColorBlendStateCreateInfo *blend_info,
1777 const VkFormat attachment_formats[MAX_RTS],
1778 uint32_t *blend_enable_mask)
1779 {
1780 *blend_enable_mask = 0;
1781
1782 bool rop_reads_dst = false;
1783 uint32_t rb_mrt_control_rop = 0;
1784 if (blend_info->logicOpEnable) {
1785 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1786 rb_mrt_control_rop =
1787 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1788 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1789 }
1790
1791 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1792 const VkPipelineColorBlendAttachmentState *att =
1793 &blend_info->pAttachments[i];
1794 const VkFormat format = attachment_formats[i];
1795
1796 uint32_t rb_mrt_control = 0;
1797 uint32_t rb_mrt_blend_control = 0;
1798 if (format != VK_FORMAT_UNDEFINED) {
1799 const bool is_int = vk_format_is_int(format);
1800 const bool has_alpha = vk_format_has_alpha(format);
1801
1802 rb_mrt_control =
1803 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1804 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1805
1806 if (att->blendEnable || rop_reads_dst)
1807 *blend_enable_mask |= 1 << i;
1808 }
1809
1810 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1811 tu_cs_emit(cs, rb_mrt_control);
1812 tu_cs_emit(cs, rb_mrt_blend_control);
1813 }
1814 }
1815
1816 static void
1817 tu6_emit_blend_control(struct tu_cs *cs,
1818 uint32_t blend_enable_mask,
1819 bool dual_src_blend,
1820 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1821 {
1822 const uint32_t sample_mask =
1823 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1824 : ((1 << msaa_info->rasterizationSamples) - 1);
1825
1826 tu_cs_emit_regs(cs,
1827 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1828 .dual_color_in_enable = dual_src_blend,
1829 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1830 .unk8 = true));
1831
1832 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1833 tu_cs_emit_regs(cs,
1834 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1835 .independent_blend = true,
1836 .sample_mask = sample_mask,
1837 .dual_color_in_enable = dual_src_blend,
1838 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1839 .alpha_to_one = msaa_info->alphaToOneEnable));
1840 }
1841
1842 static VkResult
1843 tu_pipeline_allocate_cs(struct tu_device *dev,
1844 struct tu_pipeline *pipeline,
1845 struct tu_pipeline_builder *builder,
1846 struct ir3_shader_variant *compute)
1847 {
1848 uint32_t size = 2048 + tu6_load_state_size(pipeline->layout, compute);
1849
1850 /* graphics case: */
1851 if (builder) {
1852 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1853 if (builder->variants[i])
1854 size += builder->variants[i]->info.sizedwords;
1855 }
1856
1857 size += builder->binning_variant->info.sizedwords;
1858 } else {
1859 size += compute->info.sizedwords;
1860 }
1861
1862 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, size);
1863
1864 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1865 * that LOAD_STATE can potentially take up a large amount of space so we
1866 * calculate its size explicitly.
1867 */
1868 return tu_cs_reserve_space(&pipeline->cs, size);
1869 }
1870
1871 static void
1872 tu_pipeline_shader_key_init(struct ir3_shader_key *key,
1873 const VkGraphicsPipelineCreateInfo *pipeline_info)
1874 {
1875 for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
1876 if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
1877 key->has_gs = true;
1878 break;
1879 }
1880 }
1881
1882 if (pipeline_info->pRasterizationState->rasterizerDiscardEnable)
1883 return;
1884
1885 const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
1886 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
1887 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1888 if (msaa_info->rasterizationSamples > 1 ||
1889 /* also set msaa key when sample location is not the default
1890 * since this affects varying interpolation */
1891 (sample_locations && sample_locations->sampleLocationsEnable)) {
1892 key->msaa = true;
1893 }
1894
1895 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1896 if (msaa_info->sampleShadingEnable)
1897 key->sample_shading = true;
1898
1899 /* We set this after we compile to NIR because we need the prim mode */
1900 key->tessellation = IR3_TESS_NONE;
1901 }
1902
1903 static uint32_t
1904 tu6_get_tessmode(struct tu_shader* shader)
1905 {
1906 uint32_t primitive_mode = shader->ir3_shader->nir->info.tess.primitive_mode;
1907 switch (primitive_mode) {
1908 case GL_ISOLINES:
1909 return IR3_TESS_ISOLINES;
1910 case GL_TRIANGLES:
1911 return IR3_TESS_TRIANGLES;
1912 case GL_QUADS:
1913 return IR3_TESS_QUADS;
1914 case GL_NONE:
1915 return IR3_TESS_NONE;
1916 default:
1917 unreachable("bad tessmode");
1918 }
1919 }
1920
1921 static uint64_t
1922 tu_upload_variant(struct tu_pipeline *pipeline,
1923 const struct ir3_shader_variant *variant)
1924 {
1925 struct tu_cs_memory memory;
1926
1927 if (!variant)
1928 return 0;
1929
1930 /* this expects to get enough alignment because shaders are allocated first
1931 * and sizedwords is always aligned correctly
1932 * note: an assert in tu6_emit_xs_config validates the alignment
1933 */
1934 tu_cs_alloc(&pipeline->cs, variant->info.sizedwords, 1, &memory);
1935
1936 memcpy(memory.map, variant->bin, sizeof(uint32_t) * variant->info.sizedwords);
1937 return memory.iova;
1938 }
1939
1940 static VkResult
1941 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
1942 struct tu_pipeline *pipeline)
1943 {
1944 const struct ir3_compiler *compiler = builder->device->compiler;
1945 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1946 NULL
1947 };
1948 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1949 gl_shader_stage stage =
1950 vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage);
1951 stage_infos[stage] = &builder->create_info->pStages[i];
1952 }
1953
1954 struct ir3_shader_key key = {};
1955 tu_pipeline_shader_key_init(&key, builder->create_info);
1956
1957 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1958 stage < MESA_SHADER_STAGES; stage++) {
1959 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1960 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
1961 continue;
1962
1963 struct tu_shader *shader =
1964 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1965 builder->alloc);
1966 if (!shader)
1967 return VK_ERROR_OUT_OF_HOST_MEMORY;
1968
1969 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
1970 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
1971 * the mode is specified in the tessellation control shader. */
1972 if ((stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_TESS_CTRL) &&
1973 key.tessellation == IR3_TESS_NONE) {
1974 key.tessellation = tu6_get_tessmode(shader);
1975 }
1976
1977 builder->shaders[stage] = shader;
1978 }
1979
1980 pipeline->tess.patch_type = key.tessellation;
1981
1982 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1983 stage < MESA_SHADER_STAGES; stage++) {
1984 if (!builder->shaders[stage])
1985 continue;
1986
1987 bool created;
1988 builder->variants[stage] =
1989 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
1990 &key, false, &created);
1991 if (!builder->variants[stage])
1992 return VK_ERROR_OUT_OF_HOST_MEMORY;
1993 }
1994
1995 uint32_t safe_constlens = ir3_trim_constlen(builder->variants, compiler);
1996
1997 key.safe_constlen = true;
1998
1999 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2000 stage < MESA_SHADER_STAGES; stage++) {
2001 if (!builder->shaders[stage])
2002 continue;
2003
2004 if (safe_constlens & (1 << stage)) {
2005 bool created;
2006 builder->variants[stage] =
2007 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2008 &key, false, &created);
2009 if (!builder->variants[stage])
2010 return VK_ERROR_OUT_OF_HOST_MEMORY;
2011 }
2012 }
2013
2014 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2015 struct ir3_shader_variant *variant;
2016
2017 if (vs->ir3_shader->stream_output.num_outputs ||
2018 !ir3_has_binning_vs(&key)) {
2019 variant = builder->variants[MESA_SHADER_VERTEX];
2020 } else {
2021 bool created;
2022 key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX));
2023 variant = ir3_shader_get_variant(vs->ir3_shader, &key,
2024 true, &created);
2025 if (!variant)
2026 return VK_ERROR_OUT_OF_HOST_MEMORY;
2027 }
2028
2029 builder->binning_variant = variant;
2030
2031 if (builder->shaders[MESA_SHADER_TESS_CTRL]) {
2032 struct ir3_shader *hs =
2033 builder->shaders[MESA_SHADER_TESS_CTRL]->ir3_shader;
2034 assert(hs->type != MESA_SHADER_NONE);
2035
2036 /* Calculate and store the per-vertex and per-patch HS-output sizes. */
2037 uint32_t per_vertex_output_size = 0;
2038 uint32_t per_patch_output_size = 0;
2039 nir_foreach_variable (output, &hs->nir->outputs) {
2040 switch (output->data.location) {
2041 case VARYING_SLOT_TESS_LEVEL_OUTER:
2042 case VARYING_SLOT_TESS_LEVEL_INNER:
2043 continue;
2044 }
2045 uint32_t size = glsl_count_attribute_slots(output->type, false) * 4;
2046 if (output->data.patch)
2047 per_patch_output_size += size;
2048 else
2049 per_vertex_output_size += size;
2050 }
2051 pipeline->tess.per_vertex_output_size = per_vertex_output_size;
2052 pipeline->tess.per_patch_output_size = per_patch_output_size;
2053 }
2054
2055 return VK_SUCCESS;
2056 }
2057
2058 static void
2059 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2060 struct tu_pipeline *pipeline)
2061 {
2062 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2063 builder->create_info->pDynamicState;
2064
2065 if (!dynamic_info)
2066 return;
2067
2068 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2069 VkDynamicState state = dynamic_info->pDynamicStates[i];
2070 switch (state) {
2071 case VK_DYNAMIC_STATE_VIEWPORT ... VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2072 pipeline->dynamic_state_mask |= BIT(state);
2073 break;
2074 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
2075 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS);
2076 break;
2077 default:
2078 assert(!"unsupported dynamic state");
2079 break;
2080 }
2081 }
2082 }
2083
2084 static void
2085 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2086 struct tu_shader *shader,
2087 struct ir3_shader_variant *v)
2088 {
2089 link->const_state = *ir3_const_state(v);
2090 link->constlen = v->constlen;
2091 link->push_consts = shader->push_consts;
2092 }
2093
2094 static void
2095 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2096 struct tu_pipeline *pipeline)
2097 {
2098 struct tu_cs prog_cs;
2099 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2100 tu6_emit_program(&prog_cs, builder, false);
2101 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2102
2103 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2104 tu6_emit_program(&prog_cs, builder, true);
2105 pipeline->program.binning_state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2106
2107 VkShaderStageFlags stages = 0;
2108 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2109 stages |= builder->create_info->pStages[i].stage;
2110 }
2111 pipeline->active_stages = stages;
2112
2113 uint32_t desc_sets = 0;
2114 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2115 if (!builder->shaders[i])
2116 continue;
2117
2118 tu_pipeline_set_linkage(&pipeline->program.link[i],
2119 builder->shaders[i],
2120 builder->variants[i]);
2121 desc_sets |= builder->shaders[i]->active_desc_sets;
2122 }
2123 pipeline->active_desc_sets = desc_sets;
2124 }
2125
2126 static void
2127 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2128 struct tu_pipeline *pipeline)
2129 {
2130 const VkPipelineVertexInputStateCreateInfo *vi_info =
2131 builder->create_info->pVertexInputState;
2132 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
2133 const struct ir3_shader_variant *bs = builder->binning_variant;
2134
2135 struct tu_cs vi_cs;
2136 tu_cs_begin_sub_stream(&pipeline->cs,
2137 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2138 tu6_emit_vertex_input(&vi_cs, vs, vi_info,
2139 &pipeline->vi.bindings_used);
2140 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2141
2142 if (bs) {
2143 tu_cs_begin_sub_stream(&pipeline->cs,
2144 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2145 tu6_emit_vertex_input(
2146 &vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
2147 pipeline->vi.binning_state_ib =
2148 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2149 }
2150 }
2151
2152 static void
2153 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2154 struct tu_pipeline *pipeline)
2155 {
2156 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2157 builder->create_info->pInputAssemblyState;
2158
2159 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2160 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2161 }
2162
2163 static bool
2164 tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs,
2165 uint32_t id, uint32_t size)
2166 {
2167 struct tu_cs_memory memory;
2168
2169 if (pipeline->dynamic_state_mask & BIT(id))
2170 return false;
2171
2172 /* TODO: share this logc with tu_cmd_dynamic_state */
2173 tu_cs_alloc(&pipeline->cs, size, 1, &memory);
2174 tu_cs_init_external(cs, memory.map, memory.map + size);
2175 tu_cs_begin(cs);
2176 tu_cs_reserve_space(cs, size);
2177
2178 assert(id < ARRAY_SIZE(pipeline->dynamic_state));
2179 pipeline->dynamic_state[id].iova = memory.iova;
2180 pipeline->dynamic_state[id].size = size;
2181 return true;
2182 }
2183
2184 static void
2185 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder,
2186 struct tu_pipeline *pipeline)
2187 {
2188 const VkPipelineTessellationStateCreateInfo *tess_info =
2189 builder->create_info->pTessellationState;
2190
2191 if (!tess_info)
2192 return;
2193
2194 assert(pipeline->ia.primtype == DI_PT_PATCHES0);
2195 assert(tess_info->patchControlPoints <= 32);
2196 pipeline->ia.primtype += tess_info->patchControlPoints;
2197 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info =
2198 vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2199 pipeline->tess.upper_left_domain_origin = !domain_info ||
2200 domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
2201 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
2202 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
2203 pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1;
2204 pipeline->tess.ds_bo_regid = ds->const_state->offsets.primitive_param + 1;
2205 }
2206
2207 static void
2208 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2209 struct tu_pipeline *pipeline)
2210 {
2211 /* The spec says:
2212 *
2213 * pViewportState is a pointer to an instance of the
2214 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2215 * pipeline has rasterization disabled."
2216 *
2217 * We leave the relevant registers stale in that case.
2218 */
2219 if (builder->rasterizer_discard)
2220 return;
2221
2222 const VkPipelineViewportStateCreateInfo *vp_info =
2223 builder->create_info->pViewportState;
2224
2225 struct tu_cs cs;
2226
2227 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_VIEWPORT, 18))
2228 tu6_emit_viewport(&cs, vp_info->pViewports);
2229
2230 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_SCISSOR, 3))
2231 tu6_emit_scissor(&cs, vp_info->pScissors);
2232 }
2233
2234 static void
2235 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2236 struct tu_pipeline *pipeline)
2237 {
2238 const VkPipelineRasterizationStateCreateInfo *rast_info =
2239 builder->create_info->pRasterizationState;
2240
2241 enum a6xx_polygon_mode mode = tu6_polygon_mode(rast_info->polygonMode);
2242
2243 struct tu_cs cs;
2244 tu_cs_begin_sub_stream(&pipeline->cs, 11, &cs);
2245
2246 tu_cs_emit_regs(&cs,
2247 A6XX_GRAS_CL_CNTL(
2248 .znear_clip_disable = rast_info->depthClampEnable,
2249 .zfar_clip_disable = rast_info->depthClampEnable,
2250 .unk5 = rast_info->depthClampEnable,
2251 .zero_gb_scale_z = 1,
2252 .vp_clip_code_ignore = 1));
2253
2254 tu_cs_emit_regs(&cs,
2255 A6XX_VPC_POLYGON_MODE(.mode = mode));
2256
2257 tu_cs_emit_regs(&cs,
2258 A6XX_PC_POLYGON_MODE(.mode = mode));
2259
2260 /* move to hw ctx init? */
2261 tu_cs_emit_regs(&cs, A6XX_GRAS_UNKNOWN_8001());
2262 tu_cs_emit_regs(&cs,
2263 A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
2264 A6XX_GRAS_SU_POINT_SIZE(1.0f));
2265
2266 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2267
2268 pipeline->gras_su_cntl =
2269 tu6_gras_su_cntl(rast_info, builder->samples);
2270
2271 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_LINE_WIDTH, 2)) {
2272 pipeline->gras_su_cntl |=
2273 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info->lineWidth / 2.0f);
2274 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = pipeline->gras_su_cntl));
2275 }
2276
2277 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BIAS, 4)) {
2278 tu6_emit_depth_bias(&cs, rast_info->depthBiasConstantFactor,
2279 rast_info->depthBiasClamp,
2280 rast_info->depthBiasSlopeFactor);
2281 }
2282
2283 }
2284
2285 static void
2286 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2287 struct tu_pipeline *pipeline)
2288 {
2289 /* The spec says:
2290 *
2291 * pDepthStencilState is a pointer to an instance of the
2292 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2293 * the pipeline has rasterization disabled or if the subpass of the
2294 * render pass the pipeline is created against does not use a
2295 * depth/stencil attachment.
2296 *
2297 * Disable both depth and stencil tests if there is no ds attachment,
2298 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2299 * only the separate stencil attachment
2300 */
2301 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2302 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2303 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2304 ? builder->create_info->pDepthStencilState
2305 : &dummy_ds_info;
2306 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2307 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2308 ? ds_info : &dummy_ds_info;
2309
2310 struct tu_cs cs;
2311 tu_cs_begin_sub_stream(&pipeline->cs, 6, &cs);
2312
2313 /* move to hw ctx init? */
2314 tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
2315 tu6_emit_depth_control(&cs, ds_info_depth,
2316 builder->create_info->pRasterizationState);
2317 tu6_emit_stencil_control(&cs, ds_info);
2318
2319 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2320
2321 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
2322 tu_cs_emit_regs(&cs,
2323 A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
2324 A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
2325 }
2326
2327 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
2328 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
2329 .bfmask = ds_info->back.compareMask & 0xff));
2330 }
2331
2332 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2)) {
2333 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.wrmask = ds_info->front.writeMask & 0xff,
2334 .bfwrmask = ds_info->back.writeMask & 0xff));
2335 }
2336
2337 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2)) {
2338 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.ref = ds_info->front.reference & 0xff,
2339 .bfref = ds_info->back.reference & 0xff));
2340 }
2341 }
2342
2343 static void
2344 tu_pipeline_builder_parse_multisample_and_color_blend(
2345 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2346 {
2347 /* The spec says:
2348 *
2349 * pMultisampleState is a pointer to an instance of the
2350 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2351 * has rasterization disabled.
2352 *
2353 * Also,
2354 *
2355 * pColorBlendState is a pointer to an instance of the
2356 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2357 * pipeline has rasterization disabled or if the subpass of the render
2358 * pass the pipeline is created against does not use any color
2359 * attachments.
2360 *
2361 * We leave the relevant registers stale when rasterization is disabled.
2362 */
2363 if (builder->rasterizer_discard)
2364 return;
2365
2366 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2367 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2368 builder->create_info->pMultisampleState;
2369 const VkPipelineColorBlendStateCreateInfo *blend_info =
2370 builder->use_color_attachments ? builder->create_info->pColorBlendState
2371 : &dummy_blend_info;
2372
2373 struct tu_cs cs;
2374 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 4, &cs);
2375
2376 uint32_t blend_enable_mask;
2377 tu6_emit_rb_mrt_controls(&cs, blend_info,
2378 builder->color_attachment_formats,
2379 &blend_enable_mask);
2380
2381 tu6_emit_blend_control(&cs, blend_enable_mask,
2382 builder->use_dual_src_blend, msaa_info);
2383
2384 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2385
2386 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5)) {
2387 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2388 tu_cs_emit_array(&cs, (const uint32_t *) blend_info->blendConstants, 4);
2389 }
2390
2391 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2392 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2393 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2394
2395 if (sample_locations && sample_locations->sampleLocationsEnable)
2396 samp_loc = &sample_locations->sampleLocationsInfo;
2397
2398 if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
2399 samp_loc ? 9 : 6)) {
2400 tu6_emit_sample_locations(&cs, samp_loc);
2401 }
2402 }
2403
2404 static void
2405 tu_pipeline_finish(struct tu_pipeline *pipeline,
2406 struct tu_device *dev,
2407 const VkAllocationCallbacks *alloc)
2408 {
2409 tu_cs_finish(&pipeline->cs);
2410 }
2411
2412 static VkResult
2413 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2414 struct tu_pipeline **pipeline)
2415 {
2416 VkResult result;
2417
2418 *pipeline =
2419 vk_zalloc2(&builder->device->alloc, builder->alloc, sizeof(**pipeline),
2420 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2421 if (!*pipeline)
2422 return VK_ERROR_OUT_OF_HOST_MEMORY;
2423
2424 (*pipeline)->layout = builder->layout;
2425
2426 /* compile and upload shaders */
2427 result = tu_pipeline_builder_compile_shaders(builder, *pipeline);
2428 if (result != VK_SUCCESS) {
2429 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2430 return result;
2431 }
2432
2433 result = tu_pipeline_allocate_cs(builder->device, *pipeline, builder, NULL);
2434 if (result != VK_SUCCESS) {
2435 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2436 return result;
2437 }
2438
2439 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2440 builder->shader_iova[i] = tu_upload_variant(*pipeline, builder->variants[i]);
2441
2442 builder->binning_vs_iova =
2443 tu_upload_variant(*pipeline, builder->binning_variant);
2444
2445 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2446 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2447 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2448 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2449 tu_pipeline_builder_parse_tessellation(builder, *pipeline);
2450 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2451 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2452 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2453 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2454 tu6_emit_load_state(*pipeline, false);
2455
2456 /* we should have reserved enough space upfront such that the CS never
2457 * grows
2458 */
2459 assert((*pipeline)->cs.bo_count == 1);
2460
2461 return VK_SUCCESS;
2462 }
2463
2464 static void
2465 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2466 {
2467 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2468 if (!builder->shaders[i])
2469 continue;
2470 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2471 }
2472 }
2473
2474 static void
2475 tu_pipeline_builder_init_graphics(
2476 struct tu_pipeline_builder *builder,
2477 struct tu_device *dev,
2478 struct tu_pipeline_cache *cache,
2479 const VkGraphicsPipelineCreateInfo *create_info,
2480 const VkAllocationCallbacks *alloc)
2481 {
2482 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2483
2484 *builder = (struct tu_pipeline_builder) {
2485 .device = dev,
2486 .cache = cache,
2487 .create_info = create_info,
2488 .alloc = alloc,
2489 .layout = layout,
2490 };
2491
2492 builder->rasterizer_discard =
2493 create_info->pRasterizationState->rasterizerDiscardEnable;
2494
2495 if (builder->rasterizer_discard) {
2496 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2497 } else {
2498 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2499
2500 const struct tu_render_pass *pass =
2501 tu_render_pass_from_handle(create_info->renderPass);
2502 const struct tu_subpass *subpass =
2503 &pass->subpasses[create_info->subpass];
2504
2505 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2506 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2507 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2508
2509 assert(subpass->color_count == 0 ||
2510 !create_info->pColorBlendState ||
2511 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2512 builder->color_attachment_count = subpass->color_count;
2513 for (uint32_t i = 0; i < subpass->color_count; i++) {
2514 const uint32_t a = subpass->color_attachments[i].attachment;
2515 if (a == VK_ATTACHMENT_UNUSED)
2516 continue;
2517
2518 builder->color_attachment_formats[i] = pass->attachments[a].format;
2519 builder->use_color_attachments = true;
2520 builder->render_components |= 0xf << (i * 4);
2521 }
2522
2523 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2524 builder->color_attachment_count++;
2525 builder->use_dual_src_blend = true;
2526 /* dual source blending has an extra fs output in the 2nd slot */
2527 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2528 builder->render_components |= 0xf << 4;
2529 }
2530 }
2531 }
2532
2533 static VkResult
2534 tu_graphics_pipeline_create(VkDevice device,
2535 VkPipelineCache pipelineCache,
2536 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2537 const VkAllocationCallbacks *pAllocator,
2538 VkPipeline *pPipeline)
2539 {
2540 TU_FROM_HANDLE(tu_device, dev, device);
2541 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2542
2543 struct tu_pipeline_builder builder;
2544 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2545 pCreateInfo, pAllocator);
2546
2547 struct tu_pipeline *pipeline = NULL;
2548 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2549 tu_pipeline_builder_finish(&builder);
2550
2551 if (result == VK_SUCCESS)
2552 *pPipeline = tu_pipeline_to_handle(pipeline);
2553 else
2554 *pPipeline = VK_NULL_HANDLE;
2555
2556 return result;
2557 }
2558
2559 VkResult
2560 tu_CreateGraphicsPipelines(VkDevice device,
2561 VkPipelineCache pipelineCache,
2562 uint32_t count,
2563 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2564 const VkAllocationCallbacks *pAllocator,
2565 VkPipeline *pPipelines)
2566 {
2567 VkResult final_result = VK_SUCCESS;
2568
2569 for (uint32_t i = 0; i < count; i++) {
2570 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2571 &pCreateInfos[i], pAllocator,
2572 &pPipelines[i]);
2573
2574 if (result != VK_SUCCESS)
2575 final_result = result;
2576 }
2577
2578 return final_result;
2579 }
2580
2581 static VkResult
2582 tu_compute_pipeline_create(VkDevice device,
2583 VkPipelineCache _cache,
2584 const VkComputePipelineCreateInfo *pCreateInfo,
2585 const VkAllocationCallbacks *pAllocator,
2586 VkPipeline *pPipeline)
2587 {
2588 TU_FROM_HANDLE(tu_device, dev, device);
2589 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2590 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2591 VkResult result;
2592
2593 struct tu_pipeline *pipeline;
2594
2595 *pPipeline = VK_NULL_HANDLE;
2596
2597 pipeline =
2598 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
2599 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2600 if (!pipeline)
2601 return VK_ERROR_OUT_OF_HOST_MEMORY;
2602
2603 pipeline->layout = layout;
2604
2605 struct ir3_shader_key key = {};
2606
2607 struct tu_shader *shader =
2608 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2609 if (!shader) {
2610 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2611 goto fail;
2612 }
2613
2614 bool created;
2615 struct ir3_shader_variant *v =
2616 ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
2617 if (!v) {
2618 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2619 goto fail;
2620 }
2621
2622 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2623 shader, v);
2624
2625 result = tu_pipeline_allocate_cs(dev, pipeline, NULL, v);
2626 if (result != VK_SUCCESS)
2627 goto fail;
2628
2629 uint64_t shader_iova = tu_upload_variant(pipeline, v);
2630
2631 for (int i = 0; i < 3; i++)
2632 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2633
2634 struct tu_cs prog_cs;
2635 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2636 tu6_emit_cs_config(&prog_cs, shader, v, shader_iova);
2637 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2638
2639 tu6_emit_load_state(pipeline, true);
2640
2641 *pPipeline = tu_pipeline_to_handle(pipeline);
2642 return VK_SUCCESS;
2643
2644 fail:
2645 if (shader)
2646 tu_shader_destroy(dev, shader, pAllocator);
2647
2648 vk_free2(&dev->alloc, pAllocator, pipeline);
2649
2650 return result;
2651 }
2652
2653 VkResult
2654 tu_CreateComputePipelines(VkDevice device,
2655 VkPipelineCache pipelineCache,
2656 uint32_t count,
2657 const VkComputePipelineCreateInfo *pCreateInfos,
2658 const VkAllocationCallbacks *pAllocator,
2659 VkPipeline *pPipelines)
2660 {
2661 VkResult final_result = VK_SUCCESS;
2662
2663 for (uint32_t i = 0; i < count; i++) {
2664 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2665 &pCreateInfos[i],
2666 pAllocator, &pPipelines[i]);
2667 if (result != VK_SUCCESS)
2668 final_result = result;
2669 }
2670
2671 return final_result;
2672 }
2673
2674 void
2675 tu_DestroyPipeline(VkDevice _device,
2676 VkPipeline _pipeline,
2677 const VkAllocationCallbacks *pAllocator)
2678 {
2679 TU_FROM_HANDLE(tu_device, dev, _device);
2680 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2681
2682 if (!_pipeline)
2683 return;
2684
2685 tu_pipeline_finish(pipeline, dev, pAllocator);
2686 vk_free2(&dev->alloc, pAllocator, pipeline);
2687 }