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turnip: pipeline program state refactor
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static inline uint32_t
46 tu6_vkstage2opcode(VkShaderStageFlags stage)
47 {
48 switch (stage) {
49 case VK_SHADER_STAGE_VERTEX_BIT:
50 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
51 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
52 case VK_SHADER_STAGE_GEOMETRY_BIT:
53 return CP_LOAD_STATE6_GEOM;
54 case VK_SHADER_STAGE_FRAGMENT_BIT:
55 case VK_SHADER_STAGE_COMPUTE_BIT:
56 return CP_LOAD_STATE6_FRAG;
57 default:
58 unreachable("bad shader type");
59 }
60 }
61
62 static enum a6xx_state_block
63 tu6_tex_stage2sb(VkShaderStageFlags stage)
64 {
65 switch (stage) {
66 case VK_SHADER_STAGE_VERTEX_BIT:
67 return SB6_VS_TEX;
68 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
69 return SB6_HS_TEX;
70 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
71 return SB6_DS_TEX;
72 case VK_SHADER_STAGE_GEOMETRY_BIT:
73 return SB6_GS_TEX;
74 case VK_SHADER_STAGE_FRAGMENT_BIT:
75 return SB6_FS_TEX;
76 case VK_SHADER_STAGE_COMPUTE_BIT:
77 return SB6_CS_TEX;
78 default:
79 unreachable("bad shader stage");
80 }
81 }
82
83 static enum a6xx_state_block
84 tu6_ubo_stage2sb(VkShaderStageFlags stage)
85 {
86 switch (stage) {
87 case VK_SHADER_STAGE_VERTEX_BIT:
88 return SB6_VS_SHADER;
89 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
90 return SB6_HS_SHADER;
91 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
92 return SB6_DS_SHADER;
93 case VK_SHADER_STAGE_GEOMETRY_BIT:
94 return SB6_GS_SHADER;
95 case VK_SHADER_STAGE_FRAGMENT_BIT:
96 return SB6_FS_SHADER;
97 case VK_SHADER_STAGE_COMPUTE_BIT:
98 return SB6_CS_SHADER;
99 default:
100 unreachable("bad shader stage");
101 }
102 }
103
104 static void
105 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
106 enum a6xx_state_block sb, unsigned base, unsigned offset,
107 unsigned count)
108 {
109 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
110 * clear if emitting more packets will even help anything. Presumably the
111 * descriptor cache is relatively small, and these packets stop doing
112 * anything when there are too many descriptors.
113 */
114 tu_cs_emit_pkt7(cs, opcode, 3);
115 tu_cs_emit(cs,
116 CP_LOAD_STATE6_0_STATE_TYPE(st) |
117 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
118 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
119 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
120 tu_cs_emit_qw(cs, offset | (base << 28));
121 }
122
123 static unsigned
124 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
125 {
126 const unsigned load_state_size = 4;
127 unsigned size = 0;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
130 for (unsigned j = 0; j < set_layout->binding_count; j++) {
131 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
132 unsigned count = 0;
133 /* Note: some users, like amber for example, pass in
134 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
135 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
136 */
137 VkShaderStageFlags stages = compute ?
138 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
139 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
140 unsigned stage_count = util_bitcount(stages);
141 switch (binding->type) {
142 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
143 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
144 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
145 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
146 /* IBO-backed resources only need one packet for all graphics stages */
147 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
148 count += 1;
149 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
150 count += 1;
151 break;
152 case VK_DESCRIPTOR_TYPE_SAMPLER:
153 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
154 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
155 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
156 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
157 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
158 /* Textures and UBO's needs a packet for each stage */
159 count = stage_count;
160 break;
161 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
162 /* Because of how we pack combined images and samplers, we
163 * currently can't use one packet for the whole array.
164 */
165 count = stage_count * binding->array_size * 2;
166 break;
167 default:
168 unreachable("bad descriptor type");
169 }
170 size += count * load_state_size;
171 }
172 }
173 return size;
174 }
175
176 static void
177 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
178 {
179 unsigned size = tu6_load_state_size(pipeline->layout, compute);
180 if (size == 0)
181 return;
182
183 struct tu_cs cs;
184 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
185
186 struct tu_pipeline_layout *layout = pipeline->layout;
187 for (unsigned i = 0; i < layout->num_sets; i++) {
188 /* From 13.2.7. Descriptor Set Binding:
189 *
190 * A compatible descriptor set must be bound for all set numbers that
191 * any shaders in a pipeline access, at the time that a draw or
192 * dispatch command is recorded to execute using that pipeline.
193 * However, if none of the shaders in a pipeline statically use any
194 * bindings with a particular set number, then no descriptor set need
195 * be bound for that set number, even if the pipeline layout includes
196 * a non-trivial descriptor set layout for that set number.
197 *
198 * This means that descriptor sets unused by the pipeline may have a
199 * garbage or 0 BINDLESS_BASE register, which will cause context faults
200 * when prefetching descriptors from these sets. Skip prefetching for
201 * descriptors from them to avoid this. This is also an optimization,
202 * since these prefetches would be useless.
203 */
204 if (!(pipeline->active_desc_sets & (1u << i)))
205 continue;
206
207 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
208 for (unsigned j = 0; j < set_layout->binding_count; j++) {
209 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
210 unsigned base = i;
211 unsigned offset = binding->offset / 4;
212 /* Note: some users, like amber for example, pass in
213 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
214 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
215 */
216 VkShaderStageFlags stages = compute ?
217 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
218 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
219 unsigned count = binding->array_size;
220 if (count == 0 || stages == 0)
221 continue;
222 switch (binding->type) {
223 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
224 base = MAX_SETS;
225 offset = (layout->input_attachment_count +
226 layout->set[i].dynamic_offset_start +
227 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
228 /* fallthrough */
229 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
230 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
231 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
232 /* IBO-backed resources only need one packet for all graphics stages */
233 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
234 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
235 base, offset, count);
236 }
237 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
238 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
239 base, offset, count);
240 }
241 break;
242 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
243 base = MAX_SETS;
244 offset = (layout->set[i].input_attachment_start +
245 binding->input_attachment_offset) * A6XX_TEX_CONST_DWORDS;
246 case VK_DESCRIPTOR_TYPE_SAMPLER:
247 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
248 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
249 unsigned stage_log2;
250 for_each_bit(stage_log2, stages) {
251 VkShaderStageFlags stage = 1 << stage_log2;
252 emit_load_state(&cs, tu6_vkstage2opcode(stage),
253 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
254 ST6_SHADER : ST6_CONSTANTS,
255 tu6_tex_stage2sb(stage), base, offset, count);
256 }
257 break;
258 }
259 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
260 base = MAX_SETS;
261 offset = (layout->input_attachment_count +
262 layout->set[i].dynamic_offset_start +
263 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
264 /* fallthrough */
265 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
266 unsigned stage_log2;
267 for_each_bit(stage_log2, stages) {
268 VkShaderStageFlags stage = 1 << stage_log2;
269 emit_load_state(&cs, tu6_vkstage2opcode(stage), ST6_UBO,
270 tu6_ubo_stage2sb(stage), base, offset, count);
271 }
272 break;
273 }
274 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
275 unsigned stage_log2;
276 for_each_bit(stage_log2, stages) {
277 VkShaderStageFlags stage = 1 << stage_log2;
278 /* TODO: We could emit less CP_LOAD_STATE6 if we used
279 * struct-of-arrays instead of array-of-structs.
280 */
281 for (unsigned i = 0; i < count; i++) {
282 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
283 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
284 emit_load_state(&cs, tu6_vkstage2opcode(stage),
285 ST6_CONSTANTS, tu6_tex_stage2sb(stage),
286 base, tex_offset, 1);
287 emit_load_state(&cs, tu6_vkstage2opcode(stage),
288 ST6_SHADER, tu6_tex_stage2sb(stage),
289 base, sam_offset, 1);
290 }
291 }
292 break;
293 }
294 default:
295 unreachable("bad descriptor type");
296 }
297 }
298 }
299
300 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
301 }
302
303 struct tu_pipeline_builder
304 {
305 struct tu_device *device;
306 struct tu_pipeline_cache *cache;
307 struct tu_pipeline_layout *layout;
308 const VkAllocationCallbacks *alloc;
309 const VkGraphicsPipelineCreateInfo *create_info;
310
311 struct tu_shader *shaders[MESA_SHADER_STAGES];
312 uint32_t shader_offsets[MESA_SHADER_STAGES];
313 uint32_t binning_vs_offset;
314 uint32_t shader_total_size;
315
316 bool rasterizer_discard;
317 /* these states are affectd by rasterizer_discard */
318 VkSampleCountFlagBits samples;
319 bool use_color_attachments;
320 bool use_dual_src_blend;
321 uint32_t color_attachment_count;
322 VkFormat color_attachment_formats[MAX_RTS];
323 VkFormat depth_attachment_format;
324 uint32_t render_components;
325 };
326
327 static enum tu_dynamic_state_bits
328 tu_dynamic_state_bit(VkDynamicState state)
329 {
330 switch (state) {
331 case VK_DYNAMIC_STATE_VIEWPORT:
332 return TU_DYNAMIC_VIEWPORT;
333 case VK_DYNAMIC_STATE_SCISSOR:
334 return TU_DYNAMIC_SCISSOR;
335 case VK_DYNAMIC_STATE_LINE_WIDTH:
336 return TU_DYNAMIC_LINE_WIDTH;
337 case VK_DYNAMIC_STATE_DEPTH_BIAS:
338 return TU_DYNAMIC_DEPTH_BIAS;
339 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
340 return TU_DYNAMIC_BLEND_CONSTANTS;
341 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
342 return TU_DYNAMIC_DEPTH_BOUNDS;
343 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
344 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
345 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
346 return TU_DYNAMIC_STENCIL_WRITE_MASK;
347 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
348 return TU_DYNAMIC_STENCIL_REFERENCE;
349 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
350 return TU_DYNAMIC_SAMPLE_LOCATIONS;
351 default:
352 unreachable("invalid dynamic state");
353 return 0;
354 }
355 }
356
357 static gl_shader_stage
358 tu_shader_stage(VkShaderStageFlagBits stage)
359 {
360 switch (stage) {
361 case VK_SHADER_STAGE_VERTEX_BIT:
362 return MESA_SHADER_VERTEX;
363 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
364 return MESA_SHADER_TESS_CTRL;
365 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
366 return MESA_SHADER_TESS_EVAL;
367 case VK_SHADER_STAGE_GEOMETRY_BIT:
368 return MESA_SHADER_GEOMETRY;
369 case VK_SHADER_STAGE_FRAGMENT_BIT:
370 return MESA_SHADER_FRAGMENT;
371 case VK_SHADER_STAGE_COMPUTE_BIT:
372 return MESA_SHADER_COMPUTE;
373 default:
374 unreachable("invalid VkShaderStageFlagBits");
375 return MESA_SHADER_NONE;
376 }
377 }
378
379 static bool
380 tu_logic_op_reads_dst(VkLogicOp op)
381 {
382 switch (op) {
383 case VK_LOGIC_OP_CLEAR:
384 case VK_LOGIC_OP_COPY:
385 case VK_LOGIC_OP_COPY_INVERTED:
386 case VK_LOGIC_OP_SET:
387 return false;
388 default:
389 return true;
390 }
391 }
392
393 static VkBlendFactor
394 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
395 {
396 /* treat dst alpha as 1.0 and avoid reading it */
397 switch (factor) {
398 case VK_BLEND_FACTOR_DST_ALPHA:
399 return VK_BLEND_FACTOR_ONE;
400 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
401 return VK_BLEND_FACTOR_ZERO;
402 default:
403 return factor;
404 }
405 }
406
407 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
408 {
409 switch (factor) {
410 case VK_BLEND_FACTOR_SRC1_COLOR:
411 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
412 case VK_BLEND_FACTOR_SRC1_ALPHA:
413 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
414 return true;
415 default:
416 return false;
417 }
418 }
419
420 static bool
421 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
422 {
423 if (!info)
424 return false;
425
426 for (unsigned i = 0; i < info->attachmentCount; i++) {
427 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
428 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
429 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
430 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
431 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
432 return true;
433 }
434
435 return false;
436 }
437
438 static enum pc_di_primtype
439 tu6_primtype(VkPrimitiveTopology topology)
440 {
441 switch (topology) {
442 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
443 return DI_PT_POINTLIST;
444 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
445 return DI_PT_LINELIST;
446 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
447 return DI_PT_LINESTRIP;
448 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
449 return DI_PT_TRILIST;
450 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
451 return DI_PT_TRISTRIP;
452 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
453 return DI_PT_TRIFAN;
454 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
455 return DI_PT_LINE_ADJ;
456 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
457 return DI_PT_LINESTRIP_ADJ;
458 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
459 return DI_PT_TRI_ADJ;
460 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
461 return DI_PT_TRISTRIP_ADJ;
462 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
463 default:
464 unreachable("invalid primitive topology");
465 return DI_PT_NONE;
466 }
467 }
468
469 static enum adreno_compare_func
470 tu6_compare_func(VkCompareOp op)
471 {
472 switch (op) {
473 case VK_COMPARE_OP_NEVER:
474 return FUNC_NEVER;
475 case VK_COMPARE_OP_LESS:
476 return FUNC_LESS;
477 case VK_COMPARE_OP_EQUAL:
478 return FUNC_EQUAL;
479 case VK_COMPARE_OP_LESS_OR_EQUAL:
480 return FUNC_LEQUAL;
481 case VK_COMPARE_OP_GREATER:
482 return FUNC_GREATER;
483 case VK_COMPARE_OP_NOT_EQUAL:
484 return FUNC_NOTEQUAL;
485 case VK_COMPARE_OP_GREATER_OR_EQUAL:
486 return FUNC_GEQUAL;
487 case VK_COMPARE_OP_ALWAYS:
488 return FUNC_ALWAYS;
489 default:
490 unreachable("invalid VkCompareOp");
491 return FUNC_NEVER;
492 }
493 }
494
495 static enum adreno_stencil_op
496 tu6_stencil_op(VkStencilOp op)
497 {
498 switch (op) {
499 case VK_STENCIL_OP_KEEP:
500 return STENCIL_KEEP;
501 case VK_STENCIL_OP_ZERO:
502 return STENCIL_ZERO;
503 case VK_STENCIL_OP_REPLACE:
504 return STENCIL_REPLACE;
505 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
506 return STENCIL_INCR_CLAMP;
507 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
508 return STENCIL_DECR_CLAMP;
509 case VK_STENCIL_OP_INVERT:
510 return STENCIL_INVERT;
511 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
512 return STENCIL_INCR_WRAP;
513 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
514 return STENCIL_DECR_WRAP;
515 default:
516 unreachable("invalid VkStencilOp");
517 return STENCIL_KEEP;
518 }
519 }
520
521 static enum a3xx_rop_code
522 tu6_rop(VkLogicOp op)
523 {
524 switch (op) {
525 case VK_LOGIC_OP_CLEAR:
526 return ROP_CLEAR;
527 case VK_LOGIC_OP_AND:
528 return ROP_AND;
529 case VK_LOGIC_OP_AND_REVERSE:
530 return ROP_AND_REVERSE;
531 case VK_LOGIC_OP_COPY:
532 return ROP_COPY;
533 case VK_LOGIC_OP_AND_INVERTED:
534 return ROP_AND_INVERTED;
535 case VK_LOGIC_OP_NO_OP:
536 return ROP_NOOP;
537 case VK_LOGIC_OP_XOR:
538 return ROP_XOR;
539 case VK_LOGIC_OP_OR:
540 return ROP_OR;
541 case VK_LOGIC_OP_NOR:
542 return ROP_NOR;
543 case VK_LOGIC_OP_EQUIVALENT:
544 return ROP_EQUIV;
545 case VK_LOGIC_OP_INVERT:
546 return ROP_INVERT;
547 case VK_LOGIC_OP_OR_REVERSE:
548 return ROP_OR_REVERSE;
549 case VK_LOGIC_OP_COPY_INVERTED:
550 return ROP_COPY_INVERTED;
551 case VK_LOGIC_OP_OR_INVERTED:
552 return ROP_OR_INVERTED;
553 case VK_LOGIC_OP_NAND:
554 return ROP_NAND;
555 case VK_LOGIC_OP_SET:
556 return ROP_SET;
557 default:
558 unreachable("invalid VkLogicOp");
559 return ROP_NOOP;
560 }
561 }
562
563 static enum adreno_rb_blend_factor
564 tu6_blend_factor(VkBlendFactor factor)
565 {
566 switch (factor) {
567 case VK_BLEND_FACTOR_ZERO:
568 return FACTOR_ZERO;
569 case VK_BLEND_FACTOR_ONE:
570 return FACTOR_ONE;
571 case VK_BLEND_FACTOR_SRC_COLOR:
572 return FACTOR_SRC_COLOR;
573 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
574 return FACTOR_ONE_MINUS_SRC_COLOR;
575 case VK_BLEND_FACTOR_DST_COLOR:
576 return FACTOR_DST_COLOR;
577 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
578 return FACTOR_ONE_MINUS_DST_COLOR;
579 case VK_BLEND_FACTOR_SRC_ALPHA:
580 return FACTOR_SRC_ALPHA;
581 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
582 return FACTOR_ONE_MINUS_SRC_ALPHA;
583 case VK_BLEND_FACTOR_DST_ALPHA:
584 return FACTOR_DST_ALPHA;
585 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
586 return FACTOR_ONE_MINUS_DST_ALPHA;
587 case VK_BLEND_FACTOR_CONSTANT_COLOR:
588 return FACTOR_CONSTANT_COLOR;
589 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
590 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
591 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
592 return FACTOR_CONSTANT_ALPHA;
593 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
594 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
595 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
596 return FACTOR_SRC_ALPHA_SATURATE;
597 case VK_BLEND_FACTOR_SRC1_COLOR:
598 return FACTOR_SRC1_COLOR;
599 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
600 return FACTOR_ONE_MINUS_SRC1_COLOR;
601 case VK_BLEND_FACTOR_SRC1_ALPHA:
602 return FACTOR_SRC1_ALPHA;
603 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
604 return FACTOR_ONE_MINUS_SRC1_ALPHA;
605 default:
606 unreachable("invalid VkBlendFactor");
607 return FACTOR_ZERO;
608 }
609 }
610
611 static enum a3xx_rb_blend_opcode
612 tu6_blend_op(VkBlendOp op)
613 {
614 switch (op) {
615 case VK_BLEND_OP_ADD:
616 return BLEND_DST_PLUS_SRC;
617 case VK_BLEND_OP_SUBTRACT:
618 return BLEND_SRC_MINUS_DST;
619 case VK_BLEND_OP_REVERSE_SUBTRACT:
620 return BLEND_DST_MINUS_SRC;
621 case VK_BLEND_OP_MIN:
622 return BLEND_MIN_DST_SRC;
623 case VK_BLEND_OP_MAX:
624 return BLEND_MAX_DST_SRC;
625 default:
626 unreachable("invalid VkBlendOp");
627 return BLEND_DST_PLUS_SRC;
628 }
629 }
630
631 static void
632 tu6_emit_xs_config(struct tu_cs *cs,
633 gl_shader_stage stage, /* xs->type, but xs may be NULL */
634 const struct ir3_shader_variant *xs,
635 uint64_t binary_iova)
636 {
637 static const struct xs_config {
638 uint16_t reg_sp_xs_ctrl;
639 uint16_t reg_sp_xs_config;
640 uint16_t reg_hlsq_xs_ctrl;
641 uint16_t reg_sp_vs_obj_start;
642 uint8_t opcode;
643 enum a6xx_state_block sb : 8;
644 } xs_config[] = {
645 [MESA_SHADER_VERTEX] = {
646 REG_A6XX_SP_VS_CTRL_REG0,
647 REG_A6XX_SP_VS_CONFIG,
648 REG_A6XX_HLSQ_VS_CNTL,
649 REG_A6XX_SP_VS_OBJ_START_LO,
650 CP_LOAD_STATE6_GEOM,
651 SB6_VS_SHADER,
652 },
653 [MESA_SHADER_TESS_CTRL] = {
654 REG_A6XX_SP_HS_CTRL_REG0,
655 REG_A6XX_SP_HS_CONFIG,
656 REG_A6XX_HLSQ_HS_CNTL,
657 REG_A6XX_SP_HS_OBJ_START_LO,
658 CP_LOAD_STATE6_GEOM,
659 SB6_HS_SHADER,
660 },
661 [MESA_SHADER_TESS_EVAL] = {
662 REG_A6XX_SP_DS_CTRL_REG0,
663 REG_A6XX_SP_DS_CONFIG,
664 REG_A6XX_HLSQ_DS_CNTL,
665 REG_A6XX_SP_DS_OBJ_START_LO,
666 CP_LOAD_STATE6_GEOM,
667 SB6_DS_SHADER,
668 },
669 [MESA_SHADER_GEOMETRY] = {
670 REG_A6XX_SP_GS_CTRL_REG0,
671 REG_A6XX_SP_GS_CONFIG,
672 REG_A6XX_HLSQ_GS_CNTL,
673 REG_A6XX_SP_GS_OBJ_START_LO,
674 CP_LOAD_STATE6_GEOM,
675 SB6_GS_SHADER,
676 },
677 [MESA_SHADER_FRAGMENT] = {
678 REG_A6XX_SP_FS_CTRL_REG0,
679 REG_A6XX_SP_FS_CONFIG,
680 REG_A6XX_HLSQ_FS_CNTL,
681 REG_A6XX_SP_FS_OBJ_START_LO,
682 CP_LOAD_STATE6_FRAG,
683 SB6_FS_SHADER,
684 },
685 [MESA_SHADER_COMPUTE] = {
686 REG_A6XX_SP_CS_CTRL_REG0,
687 REG_A6XX_SP_CS_CONFIG,
688 REG_A6XX_HLSQ_CS_CNTL,
689 REG_A6XX_SP_CS_OBJ_START_LO,
690 CP_LOAD_STATE6_FRAG,
691 SB6_CS_SHADER,
692 },
693 };
694 const struct xs_config *cfg = &xs_config[stage];
695
696 if (!xs) {
697 /* shader stage disabled */
698 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
699 tu_cs_emit(cs, 0);
700
701 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
702 tu_cs_emit(cs, 0);
703 return;
704 }
705
706 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
707 enum a3xx_threadsize threadsize = FOUR_QUADS;
708
709 /* TODO:
710 * the "threadsize" field may have nothing to do with threadsize,
711 * use a value that matches the blob until it is figured out
712 */
713 if (xs->type == MESA_SHADER_GEOMETRY)
714 threadsize = TWO_QUADS;
715
716 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
717 tu_cs_emit(cs,
718 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
719 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
720 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
721 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
722 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
723 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
724 /* only fragment shader sets VARYING bit */
725 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
726 /* unknown bit, seems unnecessary */
727 COND(is_fs, 0x1000000));
728
729 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
730 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
731 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
732 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
733 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
734 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO));
735 tu_cs_emit(cs, xs->instrlen);
736
737 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
738 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(xs->constlen, 4)) |
739 A6XX_HLSQ_VS_CNTL_ENABLED);
740
741 /* emit program binary
742 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
743 */
744
745 assert((binary_iova & 0x7f) == 0);
746
747 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
748 tu_cs_emit_qw(cs, binary_iova);
749
750 tu_cs_emit_pkt7(cs, cfg->opcode, 3);
751 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
752 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
753 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
754 CP_LOAD_STATE6_0_STATE_BLOCK(cfg->sb) |
755 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
756 tu_cs_emit_qw(cs, binary_iova);
757
758 /* emit immediates */
759
760 const struct ir3_const_state *const_state = &xs->shader->const_state;
761 uint32_t base = const_state->offsets.immediate;
762 int size = const_state->immediates_count;
763
764 /* truncate size to avoid writing constants that shader
765 * does not use:
766 */
767 size = MIN2(size + base, xs->constlen) - base;
768
769 if (size <= 0)
770 return;
771
772 tu_cs_emit_pkt7(cs, cfg->opcode, 3 + size * 4);
773 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
774 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
775 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
776 CP_LOAD_STATE6_0_STATE_BLOCK(cfg->sb) |
777 CP_LOAD_STATE6_0_NUM_UNIT(size));
778 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
779 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
780
781 for (unsigned i = 0; i < size; i++) {
782 tu_cs_emit(cs, const_state->immediates[i].val[0]);
783 tu_cs_emit(cs, const_state->immediates[i].val[1]);
784 tu_cs_emit(cs, const_state->immediates[i].val[2]);
785 tu_cs_emit(cs, const_state->immediates[i].val[3]);
786 }
787 }
788
789 static void
790 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
791 const struct ir3_shader_variant *v,
792 uint32_t binary_iova)
793 {
794 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
795 tu_cs_emit(cs, 0xff);
796
797 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
798
799 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
800 tu_cs_emit(cs, 0x41);
801
802 uint32_t local_invocation_id =
803 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
804 uint32_t work_group_id =
805 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
806
807 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
808 tu_cs_emit(cs,
809 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
810 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
811 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
812 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
813 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
814 }
815
816 static void
817 tu6_emit_vs_system_values(struct tu_cs *cs,
818 const struct ir3_shader_variant *vs,
819 const struct ir3_shader_variant *gs,
820 bool primid_passthru)
821 {
822 const uint32_t vertexid_regid =
823 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
824 const uint32_t instanceid_regid =
825 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
826 const uint32_t primitiveid_regid = gs ?
827 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
828 regid(63, 0);
829 const uint32_t gsheader_regid = gs ?
830 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
831 regid(63, 0);
832
833 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
834 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
835 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
836 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
837 0xfc000000);
838 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
839 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
840 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
841 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
842 0xfc00); /* VFD_CONTROL_5 */
843 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
844 }
845
846 /* Add any missing varyings needed for stream-out. Otherwise varyings not
847 * used by fragment shader will be stripped out.
848 */
849 static void
850 tu6_link_streamout(struct ir3_shader_linkage *l,
851 const struct ir3_shader_variant *v)
852 {
853 const struct ir3_stream_output_info *info = &v->shader->stream_output;
854
855 /*
856 * First, any stream-out varyings not already in linkage map (ie. also
857 * consumed by frag shader) need to be added:
858 */
859 for (unsigned i = 0; i < info->num_outputs; i++) {
860 const struct ir3_stream_output *out = &info->output[i];
861 unsigned compmask =
862 (1 << (out->num_components + out->start_component)) - 1;
863 unsigned k = out->register_index;
864 unsigned idx, nextloc = 0;
865
866 /* psize/pos need to be the last entries in linkage map, and will
867 * get added link_stream_out, so skip over them:
868 */
869 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
870 v->outputs[k].slot == VARYING_SLOT_POS)
871 continue;
872
873 for (idx = 0; idx < l->cnt; idx++) {
874 if (l->var[idx].regid == v->outputs[k].regid)
875 break;
876 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
877 }
878
879 /* add if not already in linkage map: */
880 if (idx == l->cnt)
881 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
882
883 /* expand component-mask if needed, ie streaming out all components
884 * but frag shader doesn't consume all components:
885 */
886 if (compmask & ~l->var[idx].compmask) {
887 l->var[idx].compmask |= compmask;
888 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
889 util_last_bit(l->var[idx].compmask));
890 }
891 }
892 }
893
894 static void
895 tu6_setup_streamout(const struct ir3_shader_variant *v,
896 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
897 {
898 const struct ir3_stream_output_info *info = &v->shader->stream_output;
899
900 memset(tf, 0, sizeof(*tf));
901
902 tf->prog_count = align(l->max_loc, 2) / 2;
903
904 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
905
906 /* set stride info to the streamout state */
907 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
908 tf->stride[i] = info->stride[i];
909
910 for (unsigned i = 0; i < info->num_outputs; i++) {
911 const struct ir3_stream_output *out = &info->output[i];
912 unsigned k = out->register_index;
913 unsigned idx;
914
915 /* Skip it, if there's an unused reg in the middle of outputs. */
916 if (v->outputs[k].regid == INVALID_REG)
917 continue;
918
919 tf->ncomp[out->output_buffer] += out->num_components;
920
921 /* linkage map sorted by order frag shader wants things, so
922 * a bit less ideal here..
923 */
924 for (idx = 0; idx < l->cnt; idx++)
925 if (l->var[idx].regid == v->outputs[k].regid)
926 break;
927
928 debug_assert(idx < l->cnt);
929
930 for (unsigned j = 0; j < out->num_components; j++) {
931 unsigned c = j + out->start_component;
932 unsigned loc = l->var[idx].loc + c;
933 unsigned off = j + out->dst_offset; /* in dwords */
934
935 if (loc & 1) {
936 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
937 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
938 A6XX_VPC_SO_PROG_B_OFF(off * 4);
939 } else {
940 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
941 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
942 A6XX_VPC_SO_PROG_A_OFF(off * 4);
943 }
944 }
945 }
946
947 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
948 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
949 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
950 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
951 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
952 }
953
954 static void
955 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
956 enum a6xx_state_block block, uint32_t offset,
957 uint32_t size, uint32_t *dwords) {
958 assert(size % 4 == 0);
959
960 tu_cs_emit_pkt7(cs, opcode, 3 + size);
961 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
962 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
963 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
964 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
965 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
966
967 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
968 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
969 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
970
971 tu_cs_emit_array(cs, dwords, size);
972 }
973
974 static void
975 tu6_emit_link_map(struct tu_cs *cs,
976 const struct ir3_shader_variant *producer,
977 const struct ir3_shader_variant *consumer) {
978 const struct ir3_const_state *const_state = &consumer->shader->const_state;
979 uint32_t base = const_state->offsets.primitive_map;
980 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
981 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
982 int size = DIV_ROUND_UP(num_loc, 4);
983
984 size = (MIN2(size + base, consumer->constlen) - base) * 4;
985 if (size <= 0)
986 return;
987
988 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
989 patch_locs);
990 }
991
992 static uint16_t
993 gl_primitive_to_tess(uint16_t primitive) {
994 switch (primitive) {
995 case GL_POINTS:
996 return TESS_POINTS;
997 case GL_LINE_STRIP:
998 return TESS_LINES;
999 case GL_TRIANGLE_STRIP:
1000 return TESS_CW_TRIS;
1001 default:
1002 unreachable("");
1003 }
1004 }
1005
1006 static void
1007 tu6_emit_vpc(struct tu_cs *cs,
1008 const struct ir3_shader_variant *vs,
1009 const struct ir3_shader_variant *gs,
1010 const struct ir3_shader_variant *fs,
1011 struct tu_streamout_state *tf)
1012 {
1013 const struct ir3_shader_variant *last_shader = gs ?: vs;
1014 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
1015 if (fs)
1016 ir3_link_shaders(&linkage, last_shader, fs, true);
1017
1018 if (last_shader->shader->stream_output.num_outputs)
1019 tu6_link_streamout(&linkage, last_shader);
1020
1021 /* We do this after linking shaders in order to know whether PrimID
1022 * passthrough needs to be enabled.
1023 */
1024 bool primid_passthru = linkage.primid_loc != 0xff;
1025 tu6_emit_vs_system_values(cs, vs, gs, primid_passthru);
1026
1027 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
1028 tu_cs_emit(cs, ~linkage.varmask[0]);
1029 tu_cs_emit(cs, ~linkage.varmask[1]);
1030 tu_cs_emit(cs, ~linkage.varmask[2]);
1031 tu_cs_emit(cs, ~linkage.varmask[3]);
1032
1033 /* a6xx finds position/pointsize at the end */
1034 const uint32_t position_regid =
1035 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
1036 const uint32_t pointsize_regid =
1037 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
1038 const uint32_t layer_regid = gs ?
1039 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
1040
1041 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
1042 if (layer_regid != regid(63, 0)) {
1043 layer_loc = linkage.max_loc;
1044 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
1045 }
1046 if (position_regid != regid(63, 0)) {
1047 position_loc = linkage.max_loc;
1048 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
1049 }
1050 if (pointsize_regid != regid(63, 0)) {
1051 pointsize_loc = linkage.max_loc;
1052 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
1053 }
1054
1055 if (last_shader->shader->stream_output.num_outputs)
1056 tu6_setup_streamout(last_shader, &linkage, tf);
1057
1058 /* map outputs of the last shader to VPC */
1059 assert(linkage.cnt <= 32);
1060 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
1061 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
1062 uint32_t sp_out[16];
1063 uint32_t sp_vpc_dst[8];
1064 for (uint32_t i = 0; i < linkage.cnt; i++) {
1065 ((uint16_t *) sp_out)[i] =
1066 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
1067 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
1068 ((uint8_t *) sp_vpc_dst)[i] =
1069 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
1070 }
1071
1072 if (gs)
1073 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
1074 else
1075 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
1076 tu_cs_emit_array(cs, sp_out, sp_out_count);
1077
1078 if (gs)
1079 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
1080 else
1081 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
1082 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
1083
1084 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
1085 tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
1086
1087 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
1088 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
1089 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
1090 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
1091 A6XX_VPC_CNTL_0_UNKLOC(0xff));
1092
1093 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
1094 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
1095 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
1096 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
1097
1098 if (gs) {
1099 tu6_emit_link_map(cs, vs, gs);
1100
1101 uint32_t primitive_regid =
1102 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
1103 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
1104 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
1105 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
1106 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
1107
1108 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
1109 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
1110
1111 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
1112 tu_cs_emit(cs, CONDREG(layer_regid,
1113 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
1114
1115 uint32_t flags_regid = ir3_find_output_regid(gs,
1116 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
1117
1118 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
1119 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
1120 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
1121
1122 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
1123 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
1124 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
1125 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
1126 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
1127
1128 uint32_t vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
1129 uint16_t output =
1130 gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
1131 uint32_t invocations = gs->shader->nir->info.gs.invocations - 1;
1132 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1133 tu_cs_emit(cs,
1134 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1135 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1136 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1137
1138 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1139 tu_cs_emit(cs, 0);
1140
1141 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
1142 tu_cs_emit(cs, 0);
1143
1144 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1145 tu_cs_emit(cs, 0xff);
1146
1147 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
1148 tu_cs_emit(cs, 0xffff00);
1149
1150 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1151 uint32_t vec4_size =
1152 gs->shader->nir->info.gs.vertices_in *
1153 DIV_ROUND_UP(vs->shader->output_size, 4);
1154 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1155 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1156
1157 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
1158 tu_cs_emit(cs, 0);
1159
1160 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1161 tu_cs_emit(cs, vs->shader->output_size);
1162 }
1163
1164 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
1165 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
1166
1167 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
1168 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
1169 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
1170 }
1171
1172 static int
1173 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1174 uint32_t index,
1175 uint8_t *interp_mode,
1176 uint8_t *ps_repl_mode)
1177 {
1178 enum
1179 {
1180 INTERP_SMOOTH = 0,
1181 INTERP_FLAT = 1,
1182 INTERP_ZERO = 2,
1183 INTERP_ONE = 3,
1184 };
1185 enum
1186 {
1187 PS_REPL_NONE = 0,
1188 PS_REPL_S = 1,
1189 PS_REPL_T = 2,
1190 PS_REPL_ONE_MINUS_T = 3,
1191 };
1192
1193 const uint32_t compmask = fs->inputs[index].compmask;
1194
1195 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1196 * fourth component occupy three consecutive varying slots
1197 */
1198 int shift = 0;
1199 *interp_mode = 0;
1200 *ps_repl_mode = 0;
1201 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1202 if (compmask & 0x1) {
1203 *ps_repl_mode |= PS_REPL_S << shift;
1204 shift += 2;
1205 }
1206 if (compmask & 0x2) {
1207 *ps_repl_mode |= PS_REPL_T << shift;
1208 shift += 2;
1209 }
1210 if (compmask & 0x4) {
1211 *interp_mode |= INTERP_ZERO << shift;
1212 shift += 2;
1213 }
1214 if (compmask & 0x8) {
1215 *interp_mode |= INTERP_ONE << 6;
1216 shift += 2;
1217 }
1218 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1219 fs->inputs[index].rasterflat) {
1220 for (int i = 0; i < 4; i++) {
1221 if (compmask & (1 << i)) {
1222 *interp_mode |= INTERP_FLAT << shift;
1223 shift += 2;
1224 }
1225 }
1226 }
1227
1228 return shift;
1229 }
1230
1231 static void
1232 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1233 const struct ir3_shader_variant *fs)
1234 {
1235 uint32_t interp_modes[8] = { 0 };
1236 uint32_t ps_repl_modes[8] = { 0 };
1237
1238 if (fs) {
1239 for (int i = -1;
1240 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1241
1242 /* get the mode for input i */
1243 uint8_t interp_mode;
1244 uint8_t ps_repl_mode;
1245 const int bits =
1246 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1247
1248 /* OR the mode into the array */
1249 const uint32_t inloc = fs->inputs[i].inloc * 2;
1250 uint32_t n = inloc / 32;
1251 uint32_t shift = inloc % 32;
1252 interp_modes[n] |= interp_mode << shift;
1253 ps_repl_modes[n] |= ps_repl_mode << shift;
1254 if (shift + bits > 32) {
1255 n++;
1256 shift = 32 - shift;
1257
1258 interp_modes[n] |= interp_mode >> shift;
1259 ps_repl_modes[n] |= ps_repl_mode >> shift;
1260 }
1261 }
1262 }
1263
1264 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1265 tu_cs_emit_array(cs, interp_modes, 8);
1266
1267 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1268 tu_cs_emit_array(cs, ps_repl_modes, 8);
1269 }
1270
1271 static void
1272 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1273 {
1274 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1275 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
1276 uint32_t smask_in_regid;
1277
1278 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
1279 bool enable_varyings = fs->total_in > 0;
1280
1281 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1282 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1283 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1284 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1285 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1286 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1287 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1288 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1289 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1290
1291 if (fs->num_sampler_prefetch > 0) {
1292 assert(VALIDREG(ij_pix_regid));
1293 /* also, it seems like ij_pix is *required* to be r0.x */
1294 assert(ij_pix_regid == regid(0, 0));
1295 }
1296
1297 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1298 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1299 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1300 0x7000); // XXX);
1301 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1302 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1303 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1304 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1305 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1306 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1307 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1308 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1309 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1310 }
1311
1312 if (fs->num_sampler_prefetch > 0) {
1313 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1314 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1315 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1316 tu_cs_emit(cs,
1317 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1318 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1319 }
1320 }
1321
1322 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1323 tu_cs_emit(cs, 0x7);
1324 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1325 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1326 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1327 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1328 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1329 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1330 0xfc00fc00);
1331 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1332 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1333 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1334 0x0000fc00);
1335 tu_cs_emit(cs, 0xfc);
1336
1337 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1338 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1339
1340 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1341 tu_cs_emit(cs,
1342 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1343 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1344 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1345 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1346 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1347 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
1348 A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
1349 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1350
1351 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1352 tu_cs_emit(cs,
1353 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1354 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1355 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1356 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1357 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1358 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1359 COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
1360 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
1361 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1362 tu_cs_emit(cs,
1363 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1364 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1365 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1366 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1367
1368 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1369 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1370
1371 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1372 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1373
1374 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1375 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1376 }
1377
1378 static void
1379 tu6_emit_fs_outputs(struct tu_cs *cs,
1380 const struct ir3_shader_variant *fs,
1381 uint32_t mrt_count, bool dual_src_blend,
1382 uint32_t render_components)
1383 {
1384 uint32_t smask_regid, posz_regid;
1385
1386 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1387 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1388
1389 uint32_t fragdata_regid[8];
1390 if (fs->color0_mrt) {
1391 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1392 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1393 fragdata_regid[i] = fragdata_regid[0];
1394 } else {
1395 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1396 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1397 }
1398
1399 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1400 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1401 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1402 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
1403 0xfc000000);
1404 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1405
1406 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1407 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1408 // TODO we could have a mix of half and full precision outputs,
1409 // we really need to figure out half-precision from IR3_REG_HALF
1410 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1411 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1412 }
1413
1414 tu_cs_emit_regs(cs,
1415 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1416
1417 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1418 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1419 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1420 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1421 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1422
1423 tu_cs_emit_regs(cs,
1424 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1425
1426 enum a6xx_ztest_mode zmode;
1427
1428 if (fs->no_earlyz || fs->has_kill || fs->writes_pos) {
1429 zmode = A6XX_LATE_Z;
1430 } else {
1431 zmode = A6XX_EARLY_Z;
1432 }
1433
1434 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1435 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1436
1437 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1438 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1439 }
1440
1441 static void
1442 tu6_emit_geometry_consts(struct tu_cs *cs,
1443 const struct ir3_shader_variant *vs,
1444 const struct ir3_shader_variant *gs) {
1445 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1446
1447 uint32_t params[4] = {
1448 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1449 vs->shader->output_size * 4, /* vertex stride */
1450 0,
1451 0,
1452 };
1453 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1454 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1455 ARRAY_SIZE(params), params);
1456
1457 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1458 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1459 ARRAY_SIZE(params), params);
1460 }
1461
1462 /* get pointer to first variant, return NULL if shader is NULL */
1463 static const struct ir3_shader_variant *
1464 tu_shader_get_variant(const struct tu_shader *shader)
1465 {
1466 return shader ? &shader->variants[0] : NULL;
1467 }
1468
1469 static void
1470 tu6_emit_program(struct tu_cs *cs,
1471 struct tu_pipeline_builder *builder,
1472 const struct tu_bo *binary_bo,
1473 bool binning_pass,
1474 struct tu_streamout_state *tf)
1475 {
1476 const struct ir3_shader_variant *vs =
1477 tu_shader_get_variant(builder->shaders[MESA_SHADER_VERTEX]);
1478 const struct ir3_shader_variant *gs =
1479 tu_shader_get_variant(builder->shaders[MESA_SHADER_GEOMETRY]);
1480 const struct ir3_shader_variant *fs =
1481 tu_shader_get_variant(builder->shaders[MESA_SHADER_FRAGMENT]);
1482 gl_shader_stage stage = MESA_SHADER_VERTEX;
1483
1484 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1485
1486 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1487 tu_cs_emit(cs, 0xff); /* XXX */
1488
1489 /* if we have streamout, use full VS in binning pass, as the
1490 * binning pass VS will have outputs on other than position/psize
1491 * stripped out
1492 *
1493 * GS also can have streamout, but we completely disable the
1494 * the binning pass variant when GS is present because we don't
1495 * support compiling correct binning pass variants with GS
1496 */
1497 if (binning_pass && vs->shader->stream_output.num_outputs == 0 && !gs) {
1498 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1499 tu6_emit_xs_config(cs, stage, vs,
1500 binary_bo->iova + builder->binning_vs_offset);
1501 stage++;
1502 }
1503
1504 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1505 const struct ir3_shader_variant *xs =
1506 tu_shader_get_variant(builder->shaders[stage]);
1507
1508 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1509 fs = xs = NULL;
1510
1511 tu6_emit_xs_config(cs, stage, xs,
1512 binary_bo->iova + builder->shader_offsets[stage]);
1513 }
1514
1515 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1516 tu_cs_emit(cs, 0);
1517
1518 tu6_emit_vpc(cs, vs, gs, fs, tf);
1519 tu6_emit_vpc_varying_modes(cs, fs);
1520
1521 if (fs) {
1522 tu6_emit_fs_inputs(cs, fs);
1523 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1524 builder->use_dual_src_blend,
1525 builder->render_components);
1526 } else {
1527 /* TODO: check if these can be skipped if fs is disabled */
1528 struct ir3_shader_variant dummy_variant = {};
1529 tu6_emit_fs_inputs(cs, &dummy_variant);
1530 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1531 builder->use_dual_src_blend,
1532 builder->render_components);
1533 }
1534
1535 if (gs)
1536 tu6_emit_geometry_consts(cs, vs, gs);
1537 }
1538
1539 static void
1540 tu6_emit_vertex_input(struct tu_cs *cs,
1541 const struct ir3_shader_variant *vs,
1542 const VkPipelineVertexInputStateCreateInfo *info,
1543 uint32_t *bindings_used)
1544 {
1545 uint32_t vfd_decode_idx = 0;
1546 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1547
1548 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1549 const VkVertexInputBindingDescription *binding =
1550 &info->pVertexBindingDescriptions[i];
1551
1552 tu_cs_emit_regs(cs,
1553 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1554
1555 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1556 binding_instanced |= 1 << binding->binding;
1557
1558 *bindings_used |= 1 << binding->binding;
1559 }
1560
1561 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1562
1563 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1564 const VkVertexInputAttributeDescription *attr =
1565 &info->pVertexAttributeDescriptions[i];
1566 uint32_t input_idx;
1567
1568 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1569 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1570 break;
1571 }
1572
1573 /* attribute not used, skip it */
1574 if (input_idx == vs->inputs_count)
1575 continue;
1576
1577 const struct tu_native_format format = tu6_format_vtx(attr->format);
1578 tu_cs_emit_regs(cs,
1579 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1580 .idx = attr->binding,
1581 .offset = attr->offset,
1582 .instanced = binding_instanced & (1 << attr->binding),
1583 .format = format.fmt,
1584 .swap = format.swap,
1585 .unk30 = 1,
1586 ._float = !vk_format_is_int(attr->format)),
1587 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1588
1589 tu_cs_emit_regs(cs,
1590 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1591 .writemask = vs->inputs[input_idx].compmask,
1592 .regid = vs->inputs[input_idx].regid));
1593
1594 vfd_decode_idx++;
1595 }
1596
1597 tu_cs_emit_regs(cs,
1598 A6XX_VFD_CONTROL_0(
1599 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1600 .decode_cnt = vfd_decode_idx));
1601 }
1602
1603 static uint32_t
1604 tu6_guardband_adj(uint32_t v)
1605 {
1606 if (v > 256)
1607 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1608 else
1609 return 511;
1610 }
1611
1612 void
1613 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1614 {
1615 float offsets[3];
1616 float scales[3];
1617 scales[0] = viewport->width / 2.0f;
1618 scales[1] = viewport->height / 2.0f;
1619 scales[2] = viewport->maxDepth - viewport->minDepth;
1620 offsets[0] = viewport->x + scales[0];
1621 offsets[1] = viewport->y + scales[1];
1622 offsets[2] = viewport->minDepth;
1623
1624 VkOffset2D min;
1625 VkOffset2D max;
1626 min.x = (int32_t) viewport->x;
1627 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1628 if (viewport->height >= 0.0f) {
1629 min.y = (int32_t) viewport->y;
1630 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1631 } else {
1632 min.y = (int32_t)(viewport->y + viewport->height);
1633 max.y = (int32_t) ceilf(viewport->y);
1634 }
1635 /* the spec allows viewport->height to be 0.0f */
1636 if (min.y == max.y)
1637 max.y++;
1638 assert(min.x >= 0 && min.x < max.x);
1639 assert(min.y >= 0 && min.y < max.y);
1640
1641 VkExtent2D guardband_adj;
1642 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1643 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1644
1645 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1646 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1647 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1648 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1649 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1650 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1651 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1652
1653 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1654 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1655 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1656 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1657 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1658
1659 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1660 tu_cs_emit(cs,
1661 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1662 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1663
1664 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1665 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1666
1667 tu_cs_emit_regs(cs,
1668 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1669 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1670
1671 tu_cs_emit_regs(cs,
1672 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1673 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1674 }
1675
1676 void
1677 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1678 {
1679 const VkOffset2D min = scissor->offset;
1680 const VkOffset2D max = {
1681 scissor->offset.x + scissor->extent.width,
1682 scissor->offset.y + scissor->extent.height,
1683 };
1684
1685 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1686 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1687 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1688 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1689 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1690 }
1691
1692 void
1693 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1694 {
1695 if (!samp_loc) {
1696 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1697 tu_cs_emit(cs, 0);
1698
1699 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1700 tu_cs_emit(cs, 0);
1701
1702 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1703 tu_cs_emit(cs, 0);
1704 return;
1705 }
1706
1707 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1708 assert(samp_loc->sampleLocationGridSize.width == 1);
1709 assert(samp_loc->sampleLocationGridSize.height == 1);
1710
1711 uint32_t sample_config =
1712 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1713 uint32_t sample_locations = 0;
1714 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1715 sample_locations |=
1716 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1717 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1718 }
1719
1720 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1721 tu_cs_emit(cs, sample_config);
1722 tu_cs_emit(cs, sample_locations);
1723
1724 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1725 tu_cs_emit(cs, sample_config);
1726 tu_cs_emit(cs, sample_locations);
1727
1728 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1729 tu_cs_emit(cs, sample_config);
1730 tu_cs_emit(cs, sample_locations);
1731 }
1732
1733 static void
1734 tu6_emit_gras_unknowns(struct tu_cs *cs)
1735 {
1736 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1737 tu_cs_emit(cs, 0x0);
1738 }
1739
1740 static void
1741 tu6_emit_point_size(struct tu_cs *cs)
1742 {
1743 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1744 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1745 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1746 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1747 }
1748
1749 static uint32_t
1750 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1751 VkSampleCountFlagBits samples)
1752 {
1753 uint32_t gras_su_cntl = 0;
1754
1755 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1756 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1757 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1758 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1759
1760 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1761 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1762
1763 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1764
1765 if (rast_info->depthBiasEnable)
1766 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1767
1768 if (samples > VK_SAMPLE_COUNT_1_BIT)
1769 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1770
1771 return gras_su_cntl;
1772 }
1773
1774 void
1775 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1776 uint32_t gras_su_cntl,
1777 float line_width)
1778 {
1779 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1780 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1781
1782 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1783 tu_cs_emit(cs, gras_su_cntl);
1784 }
1785
1786 void
1787 tu6_emit_depth_bias(struct tu_cs *cs,
1788 float constant_factor,
1789 float clamp,
1790 float slope_factor)
1791 {
1792 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1793 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1794 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1795 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1796 }
1797
1798 static void
1799 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1800 {
1801 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1802 tu_cs_emit(cs, 0);
1803 }
1804
1805 static void
1806 tu6_emit_depth_control(struct tu_cs *cs,
1807 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1808 const VkPipelineRasterizationStateCreateInfo *rast_info)
1809 {
1810 assert(!ds_info->depthBoundsTestEnable);
1811
1812 uint32_t rb_depth_cntl = 0;
1813 if (ds_info->depthTestEnable) {
1814 rb_depth_cntl |=
1815 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1816 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1817 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1818
1819 if (rast_info->depthClampEnable)
1820 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1821
1822 if (ds_info->depthWriteEnable)
1823 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1824 }
1825
1826 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1827 tu_cs_emit(cs, rb_depth_cntl);
1828 }
1829
1830 static void
1831 tu6_emit_stencil_control(struct tu_cs *cs,
1832 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1833 {
1834 uint32_t rb_stencil_control = 0;
1835 if (ds_info->stencilTestEnable) {
1836 const VkStencilOpState *front = &ds_info->front;
1837 const VkStencilOpState *back = &ds_info->back;
1838 rb_stencil_control |=
1839 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1840 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1841 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1842 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1843 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1844 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1845 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1846 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1847 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1848 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1849 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1850 }
1851
1852 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1853 tu_cs_emit(cs, rb_stencil_control);
1854 }
1855
1856 void
1857 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1858 {
1859 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1860 tu_cs_emit(
1861 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1862 }
1863
1864 void
1865 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1866 {
1867 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1868 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1869 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1870 }
1871
1872 void
1873 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1874 {
1875 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1876 tu_cs_emit(cs,
1877 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1878 }
1879
1880 static uint32_t
1881 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1882 bool has_alpha)
1883 {
1884 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1885 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1886 has_alpha ? att->srcColorBlendFactor
1887 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1888 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1889 has_alpha ? att->dstColorBlendFactor
1890 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1891 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1892 const enum adreno_rb_blend_factor src_alpha_factor =
1893 tu6_blend_factor(att->srcAlphaBlendFactor);
1894 const enum adreno_rb_blend_factor dst_alpha_factor =
1895 tu6_blend_factor(att->dstAlphaBlendFactor);
1896
1897 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1898 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1899 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1900 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1901 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1902 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1903 }
1904
1905 static uint32_t
1906 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1907 uint32_t rb_mrt_control_rop,
1908 bool is_int,
1909 bool has_alpha)
1910 {
1911 uint32_t rb_mrt_control =
1912 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1913
1914 /* ignore blending and logic op for integer attachments */
1915 if (is_int) {
1916 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1917 return rb_mrt_control;
1918 }
1919
1920 rb_mrt_control |= rb_mrt_control_rop;
1921
1922 if (att->blendEnable) {
1923 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1924
1925 if (has_alpha)
1926 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1927 }
1928
1929 return rb_mrt_control;
1930 }
1931
1932 static void
1933 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1934 const VkPipelineColorBlendStateCreateInfo *blend_info,
1935 const VkFormat attachment_formats[MAX_RTS],
1936 uint32_t *blend_enable_mask)
1937 {
1938 *blend_enable_mask = 0;
1939
1940 bool rop_reads_dst = false;
1941 uint32_t rb_mrt_control_rop = 0;
1942 if (blend_info->logicOpEnable) {
1943 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1944 rb_mrt_control_rop =
1945 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1946 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1947 }
1948
1949 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1950 const VkPipelineColorBlendAttachmentState *att =
1951 &blend_info->pAttachments[i];
1952 const VkFormat format = attachment_formats[i];
1953
1954 uint32_t rb_mrt_control = 0;
1955 uint32_t rb_mrt_blend_control = 0;
1956 if (format != VK_FORMAT_UNDEFINED) {
1957 const bool is_int = vk_format_is_int(format);
1958 const bool has_alpha = vk_format_has_alpha(format);
1959
1960 rb_mrt_control =
1961 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1962 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1963
1964 if (att->blendEnable || rop_reads_dst)
1965 *blend_enable_mask |= 1 << i;
1966 }
1967
1968 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1969 tu_cs_emit(cs, rb_mrt_control);
1970 tu_cs_emit(cs, rb_mrt_blend_control);
1971 }
1972 }
1973
1974 static void
1975 tu6_emit_blend_control(struct tu_cs *cs,
1976 uint32_t blend_enable_mask,
1977 bool dual_src_blend,
1978 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1979 {
1980 const uint32_t sample_mask =
1981 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1982 : ((1 << msaa_info->rasterizationSamples) - 1);
1983
1984 tu_cs_emit_regs(cs,
1985 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1986 .dual_color_in_enable = dual_src_blend,
1987 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1988 .unk8 = true));
1989
1990 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1991 tu_cs_emit_regs(cs,
1992 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1993 .independent_blend = true,
1994 .sample_mask = sample_mask,
1995 .dual_color_in_enable = dual_src_blend,
1996 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1997 .alpha_to_one = msaa_info->alphaToOneEnable));
1998 }
1999
2000 void
2001 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
2002 {
2003 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2004 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
2005 }
2006
2007 static VkResult
2008 tu_pipeline_create(struct tu_device *dev,
2009 struct tu_pipeline_layout *layout,
2010 bool compute,
2011 const VkAllocationCallbacks *pAllocator,
2012 struct tu_pipeline **out_pipeline)
2013 {
2014 struct tu_pipeline *pipeline =
2015 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
2016 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2017 if (!pipeline)
2018 return VK_ERROR_OUT_OF_HOST_MEMORY;
2019
2020 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
2021
2022 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
2023 * that LOAD_STATE can potentially take up a large amount of space so we
2024 * calculate its size explicitly.
2025 */
2026 unsigned load_state_size = tu6_load_state_size(layout, compute);
2027 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size);
2028 if (result != VK_SUCCESS) {
2029 vk_free2(&dev->alloc, pAllocator, pipeline);
2030 return result;
2031 }
2032
2033 *out_pipeline = pipeline;
2034
2035 return VK_SUCCESS;
2036 }
2037
2038 static VkResult
2039 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
2040 {
2041 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
2042 NULL
2043 };
2044 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
2045 gl_shader_stage stage =
2046 tu_shader_stage(builder->create_info->pStages[i].stage);
2047 stage_infos[stage] = &builder->create_info->pStages[i];
2048 }
2049
2050 struct tu_shader_compile_options options;
2051 tu_shader_compile_options_init(&options, builder->create_info);
2052
2053 /* compile shaders in reverse order */
2054 struct tu_shader *next_stage_shader = NULL;
2055 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
2056 stage > MESA_SHADER_NONE; stage--) {
2057 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
2058 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
2059 continue;
2060
2061 struct tu_shader *shader =
2062 tu_shader_create(builder->device, stage, stage_info, builder->layout,
2063 builder->alloc);
2064 if (!shader)
2065 return VK_ERROR_OUT_OF_HOST_MEMORY;
2066
2067 VkResult result =
2068 tu_shader_compile(builder->device, shader, next_stage_shader,
2069 &options, builder->alloc);
2070 if (result != VK_SUCCESS)
2071 return result;
2072
2073 builder->shaders[stage] = shader;
2074 builder->shader_offsets[stage] = builder->shader_total_size;
2075 builder->shader_total_size +=
2076 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
2077
2078 next_stage_shader = shader;
2079 }
2080
2081 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2082 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2083 const struct ir3_shader_variant *variant;
2084
2085 if (vs->ir3_shader.stream_output.num_outputs)
2086 variant = &vs->variants[0];
2087 else
2088 variant = &vs->variants[1];
2089
2090 builder->binning_vs_offset = builder->shader_total_size;
2091 builder->shader_total_size +=
2092 sizeof(uint32_t) * variant->info.sizedwords;
2093 }
2094
2095 return VK_SUCCESS;
2096 }
2097
2098 static VkResult
2099 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
2100 struct tu_pipeline *pipeline)
2101 {
2102 struct tu_bo *bo = &pipeline->program.binary_bo;
2103
2104 VkResult result =
2105 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
2106 if (result != VK_SUCCESS)
2107 return result;
2108
2109 result = tu_bo_map(builder->device, bo);
2110 if (result != VK_SUCCESS)
2111 return result;
2112
2113 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2114 const struct tu_shader *shader = builder->shaders[i];
2115 if (!shader)
2116 continue;
2117
2118 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
2119 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
2120 }
2121
2122 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2123 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2124 const struct ir3_shader_variant *variant;
2125 void *bin;
2126
2127 if (vs->ir3_shader.stream_output.num_outputs) {
2128 variant = &vs->variants[0];
2129 bin = vs->binary;
2130 } else {
2131 variant = &vs->variants[1];
2132 bin = vs->binning_binary;
2133 }
2134
2135 memcpy(bo->map + builder->binning_vs_offset, bin,
2136 sizeof(uint32_t) * variant->info.sizedwords);
2137 }
2138
2139 return VK_SUCCESS;
2140 }
2141
2142 static void
2143 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2144 struct tu_pipeline *pipeline)
2145 {
2146 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2147 builder->create_info->pDynamicState;
2148
2149 if (!dynamic_info)
2150 return;
2151
2152 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2153 pipeline->dynamic_state.mask |=
2154 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
2155 }
2156 }
2157
2158 static void
2159 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2160 struct tu_shader *shader,
2161 struct ir3_shader_variant *v)
2162 {
2163 link->ubo_state = v->shader->ubo_state;
2164 link->const_state = v->shader->const_state;
2165 link->constlen = v->constlen;
2166 link->push_consts = shader->push_consts;
2167 }
2168
2169 static void
2170 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2171 struct tu_pipeline *pipeline)
2172 {
2173 struct tu_cs prog_cs;
2174 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2175 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
2176 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2177
2178 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2179 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
2180 pipeline->program.binning_state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2181
2182 VkShaderStageFlags stages = 0;
2183 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2184 stages |= builder->create_info->pStages[i].stage;
2185 }
2186 pipeline->active_stages = stages;
2187
2188 uint32_t desc_sets = 0;
2189 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2190 if (!builder->shaders[i])
2191 continue;
2192
2193 tu_pipeline_set_linkage(&pipeline->program.link[i],
2194 builder->shaders[i],
2195 &builder->shaders[i]->variants[0]);
2196 desc_sets |= builder->shaders[i]->active_desc_sets;
2197 }
2198 pipeline->active_desc_sets = desc_sets;
2199
2200 if (builder->shaders[MESA_SHADER_FRAGMENT]) {
2201 memcpy(pipeline->program.input_attachment_idx,
2202 builder->shaders[MESA_SHADER_FRAGMENT]->attachment_idx,
2203 sizeof(pipeline->program.input_attachment_idx));
2204 }
2205 }
2206
2207 static void
2208 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2209 struct tu_pipeline *pipeline)
2210 {
2211 const VkPipelineVertexInputStateCreateInfo *vi_info =
2212 builder->create_info->pVertexInputState;
2213 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2214
2215 struct tu_cs vi_cs;
2216 tu_cs_begin_sub_stream(&pipeline->cs,
2217 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2218 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
2219 &pipeline->vi.bindings_used);
2220 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2221
2222 if (vs->has_binning_pass) {
2223 tu_cs_begin_sub_stream(&pipeline->cs,
2224 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2225 tu6_emit_vertex_input(
2226 &vi_cs, &vs->variants[1], vi_info, &pipeline->vi.bindings_used);
2227 pipeline->vi.binning_state_ib =
2228 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2229 }
2230 }
2231
2232 static void
2233 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2234 struct tu_pipeline *pipeline)
2235 {
2236 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2237 builder->create_info->pInputAssemblyState;
2238
2239 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2240 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2241 }
2242
2243 static void
2244 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2245 struct tu_pipeline *pipeline)
2246 {
2247 /* The spec says:
2248 *
2249 * pViewportState is a pointer to an instance of the
2250 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2251 * pipeline has rasterization disabled."
2252 *
2253 * We leave the relevant registers stale in that case.
2254 */
2255 if (builder->rasterizer_discard)
2256 return;
2257
2258 const VkPipelineViewportStateCreateInfo *vp_info =
2259 builder->create_info->pViewportState;
2260
2261 struct tu_cs vp_cs;
2262 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
2263
2264 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2265 assert(vp_info->viewportCount == 1);
2266 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
2267 }
2268
2269 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2270 assert(vp_info->scissorCount == 1);
2271 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
2272 }
2273
2274 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
2275 }
2276
2277 static void
2278 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2279 struct tu_pipeline *pipeline)
2280 {
2281 const VkPipelineRasterizationStateCreateInfo *rast_info =
2282 builder->create_info->pRasterizationState;
2283
2284 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2285
2286 struct tu_cs rast_cs;
2287 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
2288
2289
2290 tu_cs_emit_regs(&rast_cs,
2291 A6XX_GRAS_CL_CNTL(
2292 .znear_clip_disable = rast_info->depthClampEnable,
2293 .zfar_clip_disable = rast_info->depthClampEnable,
2294 .unk5 = rast_info->depthClampEnable,
2295 .zero_gb_scale_z = 1,
2296 .vp_clip_code_ignore = 1));
2297 /* move to hw ctx init? */
2298 tu6_emit_gras_unknowns(&rast_cs);
2299 tu6_emit_point_size(&rast_cs);
2300
2301 const uint32_t gras_su_cntl =
2302 tu6_gras_su_cntl(rast_info, builder->samples);
2303
2304 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
2305 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
2306
2307 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
2308 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
2309 rast_info->depthBiasClamp,
2310 rast_info->depthBiasSlopeFactor);
2311 }
2312
2313 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
2314
2315 pipeline->rast.gras_su_cntl = gras_su_cntl;
2316 }
2317
2318 static void
2319 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2320 struct tu_pipeline *pipeline)
2321 {
2322 /* The spec says:
2323 *
2324 * pDepthStencilState is a pointer to an instance of the
2325 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2326 * the pipeline has rasterization disabled or if the subpass of the
2327 * render pass the pipeline is created against does not use a
2328 * depth/stencil attachment.
2329 *
2330 * Disable both depth and stencil tests if there is no ds attachment,
2331 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2332 * only the separate stencil attachment
2333 */
2334 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2335 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2336 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2337 ? builder->create_info->pDepthStencilState
2338 : &dummy_ds_info;
2339 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2340 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2341 ? ds_info : &dummy_ds_info;
2342
2343 struct tu_cs ds_cs;
2344 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2345
2346 /* move to hw ctx init? */
2347 tu6_emit_alpha_control_disable(&ds_cs);
2348
2349 tu6_emit_depth_control(&ds_cs, ds_info_depth,
2350 builder->create_info->pRasterizationState);
2351 tu6_emit_stencil_control(&ds_cs, ds_info);
2352
2353 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2354 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2355 ds_info->back.compareMask);
2356 }
2357 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2358 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2359 ds_info->back.writeMask);
2360 }
2361 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2362 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2363 ds_info->back.reference);
2364 }
2365
2366 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2367 }
2368
2369 static void
2370 tu_pipeline_builder_parse_multisample_and_color_blend(
2371 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2372 {
2373 /* The spec says:
2374 *
2375 * pMultisampleState is a pointer to an instance of the
2376 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2377 * has rasterization disabled.
2378 *
2379 * Also,
2380 *
2381 * pColorBlendState is a pointer to an instance of the
2382 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2383 * pipeline has rasterization disabled or if the subpass of the render
2384 * pass the pipeline is created against does not use any color
2385 * attachments.
2386 *
2387 * We leave the relevant registers stale when rasterization is disabled.
2388 */
2389 if (builder->rasterizer_discard)
2390 return;
2391
2392 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2393 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2394 builder->create_info->pMultisampleState;
2395 const VkPipelineColorBlendStateCreateInfo *blend_info =
2396 builder->use_color_attachments ? builder->create_info->pColorBlendState
2397 : &dummy_blend_info;
2398
2399 struct tu_cs blend_cs;
2400 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 18, &blend_cs);
2401
2402 uint32_t blend_enable_mask;
2403 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2404 builder->color_attachment_formats,
2405 &blend_enable_mask);
2406
2407 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2408 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2409
2410 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SAMPLE_LOCATIONS)) {
2411 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2412 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2413 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2414
2415 if (sample_locations && sample_locations->sampleLocationsEnable)
2416 samp_loc = &sample_locations->sampleLocationsInfo;
2417
2418 tu6_emit_sample_locations(&blend_cs, samp_loc);
2419 }
2420
2421 tu6_emit_blend_control(&blend_cs, blend_enable_mask,
2422 builder->use_dual_src_blend, msaa_info);
2423
2424 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2425 }
2426
2427 static void
2428 tu_pipeline_finish(struct tu_pipeline *pipeline,
2429 struct tu_device *dev,
2430 const VkAllocationCallbacks *alloc)
2431 {
2432 tu_cs_finish(&pipeline->cs);
2433
2434 if (pipeline->program.binary_bo.gem_handle)
2435 tu_bo_finish(dev, &pipeline->program.binary_bo);
2436 }
2437
2438 static VkResult
2439 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2440 struct tu_pipeline **pipeline)
2441 {
2442 VkResult result = tu_pipeline_create(builder->device, builder->layout,
2443 false, builder->alloc, pipeline);
2444 if (result != VK_SUCCESS)
2445 return result;
2446
2447 (*pipeline)->layout = builder->layout;
2448
2449 /* compile and upload shaders */
2450 result = tu_pipeline_builder_compile_shaders(builder);
2451 if (result == VK_SUCCESS)
2452 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2453 if (result != VK_SUCCESS) {
2454 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2455 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2456 *pipeline = VK_NULL_HANDLE;
2457
2458 return result;
2459 }
2460
2461 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2462 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2463 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2464 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2465 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2466 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2467 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2468 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2469 tu6_emit_load_state(*pipeline, false);
2470
2471 /* we should have reserved enough space upfront such that the CS never
2472 * grows
2473 */
2474 assert((*pipeline)->cs.bo_count == 1);
2475
2476 return VK_SUCCESS;
2477 }
2478
2479 static void
2480 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2481 {
2482 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2483 if (!builder->shaders[i])
2484 continue;
2485 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2486 }
2487 }
2488
2489 static void
2490 tu_pipeline_builder_init_graphics(
2491 struct tu_pipeline_builder *builder,
2492 struct tu_device *dev,
2493 struct tu_pipeline_cache *cache,
2494 const VkGraphicsPipelineCreateInfo *create_info,
2495 const VkAllocationCallbacks *alloc)
2496 {
2497 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2498
2499 *builder = (struct tu_pipeline_builder) {
2500 .device = dev,
2501 .cache = cache,
2502 .create_info = create_info,
2503 .alloc = alloc,
2504 .layout = layout,
2505 };
2506
2507 builder->rasterizer_discard =
2508 create_info->pRasterizationState->rasterizerDiscardEnable;
2509
2510 if (builder->rasterizer_discard) {
2511 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2512 } else {
2513 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2514
2515 const struct tu_render_pass *pass =
2516 tu_render_pass_from_handle(create_info->renderPass);
2517 const struct tu_subpass *subpass =
2518 &pass->subpasses[create_info->subpass];
2519
2520 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2521 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2522 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2523
2524 assert(subpass->color_count == 0 ||
2525 !create_info->pColorBlendState ||
2526 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2527 builder->color_attachment_count = subpass->color_count;
2528 for (uint32_t i = 0; i < subpass->color_count; i++) {
2529 const uint32_t a = subpass->color_attachments[i].attachment;
2530 if (a == VK_ATTACHMENT_UNUSED)
2531 continue;
2532
2533 builder->color_attachment_formats[i] = pass->attachments[a].format;
2534 builder->use_color_attachments = true;
2535 builder->render_components |= 0xf << (i * 4);
2536 }
2537
2538 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2539 builder->color_attachment_count++;
2540 builder->use_dual_src_blend = true;
2541 /* dual source blending has an extra fs output in the 2nd slot */
2542 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2543 builder->render_components |= 0xf << 4;
2544 }
2545 }
2546 }
2547
2548 static VkResult
2549 tu_graphics_pipeline_create(VkDevice device,
2550 VkPipelineCache pipelineCache,
2551 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2552 const VkAllocationCallbacks *pAllocator,
2553 VkPipeline *pPipeline)
2554 {
2555 TU_FROM_HANDLE(tu_device, dev, device);
2556 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2557
2558 struct tu_pipeline_builder builder;
2559 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2560 pCreateInfo, pAllocator);
2561
2562 struct tu_pipeline *pipeline = NULL;
2563 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2564 tu_pipeline_builder_finish(&builder);
2565
2566 if (result == VK_SUCCESS)
2567 *pPipeline = tu_pipeline_to_handle(pipeline);
2568 else
2569 *pPipeline = VK_NULL_HANDLE;
2570
2571 return result;
2572 }
2573
2574 VkResult
2575 tu_CreateGraphicsPipelines(VkDevice device,
2576 VkPipelineCache pipelineCache,
2577 uint32_t count,
2578 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2579 const VkAllocationCallbacks *pAllocator,
2580 VkPipeline *pPipelines)
2581 {
2582 VkResult final_result = VK_SUCCESS;
2583
2584 for (uint32_t i = 0; i < count; i++) {
2585 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2586 &pCreateInfos[i], pAllocator,
2587 &pPipelines[i]);
2588
2589 if (result != VK_SUCCESS)
2590 final_result = result;
2591 }
2592
2593 return final_result;
2594 }
2595
2596 static VkResult
2597 tu_compute_upload_shader(VkDevice device,
2598 struct tu_pipeline *pipeline,
2599 struct tu_shader *shader)
2600 {
2601 TU_FROM_HANDLE(tu_device, dev, device);
2602 struct tu_bo *bo = &pipeline->program.binary_bo;
2603 struct ir3_shader_variant *v = &shader->variants[0];
2604
2605 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2606 VkResult result =
2607 tu_bo_init_new(dev, bo, shader_size);
2608 if (result != VK_SUCCESS)
2609 return result;
2610
2611 result = tu_bo_map(dev, bo);
2612 if (result != VK_SUCCESS)
2613 return result;
2614
2615 memcpy(bo->map, shader->binary, shader_size);
2616
2617 return VK_SUCCESS;
2618 }
2619
2620
2621 static VkResult
2622 tu_compute_pipeline_create(VkDevice device,
2623 VkPipelineCache _cache,
2624 const VkComputePipelineCreateInfo *pCreateInfo,
2625 const VkAllocationCallbacks *pAllocator,
2626 VkPipeline *pPipeline)
2627 {
2628 TU_FROM_HANDLE(tu_device, dev, device);
2629 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2630 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2631 VkResult result;
2632
2633 struct tu_pipeline *pipeline;
2634
2635 *pPipeline = VK_NULL_HANDLE;
2636
2637 result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline);
2638 if (result != VK_SUCCESS)
2639 return result;
2640
2641 pipeline->layout = layout;
2642
2643 struct tu_shader_compile_options options;
2644 tu_shader_compile_options_init(&options, NULL);
2645
2646 struct tu_shader *shader =
2647 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2648 if (!shader) {
2649 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2650 goto fail;
2651 }
2652
2653 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2654 if (result != VK_SUCCESS)
2655 goto fail;
2656
2657 struct ir3_shader_variant *v = &shader->variants[0];
2658
2659 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2660 shader, v);
2661
2662 result = tu_compute_upload_shader(device, pipeline, shader);
2663 if (result != VK_SUCCESS)
2664 goto fail;
2665
2666 for (int i = 0; i < 3; i++)
2667 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2668
2669 struct tu_cs prog_cs;
2670 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2671 tu6_emit_cs_config(&prog_cs, shader, v, pipeline->program.binary_bo.iova);
2672 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2673
2674 tu6_emit_load_state(pipeline, true);
2675
2676 *pPipeline = tu_pipeline_to_handle(pipeline);
2677 return VK_SUCCESS;
2678
2679 fail:
2680 if (shader)
2681 tu_shader_destroy(dev, shader, pAllocator);
2682
2683 tu_pipeline_finish(pipeline, dev, pAllocator);
2684 vk_free2(&dev->alloc, pAllocator, pipeline);
2685
2686 return result;
2687 }
2688
2689 VkResult
2690 tu_CreateComputePipelines(VkDevice device,
2691 VkPipelineCache pipelineCache,
2692 uint32_t count,
2693 const VkComputePipelineCreateInfo *pCreateInfos,
2694 const VkAllocationCallbacks *pAllocator,
2695 VkPipeline *pPipelines)
2696 {
2697 VkResult final_result = VK_SUCCESS;
2698
2699 for (uint32_t i = 0; i < count; i++) {
2700 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2701 &pCreateInfos[i],
2702 pAllocator, &pPipelines[i]);
2703 if (result != VK_SUCCESS)
2704 final_result = result;
2705 }
2706
2707 return final_result;
2708 }
2709
2710 void
2711 tu_DestroyPipeline(VkDevice _device,
2712 VkPipeline _pipeline,
2713 const VkAllocationCallbacks *pAllocator)
2714 {
2715 TU_FROM_HANDLE(tu_device, dev, _device);
2716 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2717
2718 if (!_pipeline)
2719 return;
2720
2721 tu_pipeline_finish(pipeline, dev, pAllocator);
2722 vk_free2(&dev->alloc, pAllocator, pipeline);
2723 }