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ir3: Skip missing VS outputs in VS out map when linking
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static inline uint32_t
46 tu6_vkstage2opcode(VkShaderStageFlags stage)
47 {
48 switch (stage) {
49 case VK_SHADER_STAGE_VERTEX_BIT:
50 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
51 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
52 case VK_SHADER_STAGE_GEOMETRY_BIT:
53 return CP_LOAD_STATE6_GEOM;
54 case VK_SHADER_STAGE_FRAGMENT_BIT:
55 case VK_SHADER_STAGE_COMPUTE_BIT:
56 return CP_LOAD_STATE6_FRAG;
57 default:
58 unreachable("bad shader type");
59 }
60 }
61
62 static enum a6xx_state_block
63 tu6_tex_stage2sb(VkShaderStageFlags stage)
64 {
65 switch (stage) {
66 case VK_SHADER_STAGE_VERTEX_BIT:
67 return SB6_VS_TEX;
68 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
69 return SB6_HS_TEX;
70 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
71 return SB6_DS_TEX;
72 case VK_SHADER_STAGE_GEOMETRY_BIT:
73 return SB6_GS_TEX;
74 case VK_SHADER_STAGE_FRAGMENT_BIT:
75 return SB6_FS_TEX;
76 case VK_SHADER_STAGE_COMPUTE_BIT:
77 return SB6_CS_TEX;
78 default:
79 unreachable("bad shader stage");
80 }
81 }
82
83 static enum a6xx_state_block
84 tu6_ubo_stage2sb(VkShaderStageFlags stage)
85 {
86 switch (stage) {
87 case VK_SHADER_STAGE_VERTEX_BIT:
88 return SB6_VS_SHADER;
89 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
90 return SB6_HS_SHADER;
91 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
92 return SB6_DS_SHADER;
93 case VK_SHADER_STAGE_GEOMETRY_BIT:
94 return SB6_GS_SHADER;
95 case VK_SHADER_STAGE_FRAGMENT_BIT:
96 return SB6_FS_SHADER;
97 case VK_SHADER_STAGE_COMPUTE_BIT:
98 return SB6_CS_SHADER;
99 default:
100 unreachable("bad shader stage");
101 }
102 }
103
104 static void
105 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
106 enum a6xx_state_block sb, unsigned base, unsigned offset,
107 unsigned count)
108 {
109 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
110 * clear if emitting more packets will even help anything. Presumably the
111 * descriptor cache is relatively small, and these packets stop doing
112 * anything when there are too many descriptors.
113 */
114 tu_cs_emit_pkt7(cs, opcode, 3);
115 tu_cs_emit(cs,
116 CP_LOAD_STATE6_0_STATE_TYPE(st) |
117 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
118 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
119 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
120 tu_cs_emit_qw(cs, offset | (base << 28));
121 }
122
123 static unsigned
124 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
125 {
126 const unsigned load_state_size = 4;
127 unsigned size = 0;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
130 for (unsigned j = 0; j < set_layout->binding_count; j++) {
131 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
132 unsigned count = 0;
133 /* Note: some users, like amber for example, pass in
134 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
135 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
136 */
137 VkShaderStageFlags stages = compute ?
138 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
139 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
140 unsigned stage_count = util_bitcount(stages);
141 switch (binding->type) {
142 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
143 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
144 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
145 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
146 /* IBO-backed resources only need one packet for all graphics stages */
147 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
148 count += 1;
149 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
150 count += 1;
151 break;
152 case VK_DESCRIPTOR_TYPE_SAMPLER:
153 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
154 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
155 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
156 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
157 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
158 /* Textures and UBO's needs a packet for each stage */
159 count = stage_count;
160 break;
161 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
162 /* Because of how we pack combined images and samplers, we
163 * currently can't use one packet for the whole array.
164 */
165 count = stage_count * binding->array_size * 2;
166 break;
167 default:
168 unreachable("bad descriptor type");
169 }
170 size += count * load_state_size;
171 }
172 }
173 return size;
174 }
175
176 static void
177 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
178 {
179 unsigned size = tu6_load_state_size(pipeline->layout, compute);
180 if (size == 0)
181 return;
182
183 struct tu_cs cs;
184 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
185
186 struct tu_pipeline_layout *layout = pipeline->layout;
187 for (unsigned i = 0; i < layout->num_sets; i++) {
188 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
189 for (unsigned j = 0; j < set_layout->binding_count; j++) {
190 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
191 unsigned base = i;
192 unsigned offset = binding->offset / 4;
193 /* Note: some users, like amber for example, pass in
194 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
195 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
196 */
197 VkShaderStageFlags stages = compute ?
198 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
199 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
200 unsigned count = binding->array_size;
201 if (count == 0 || stages == 0)
202 continue;
203 switch (binding->type) {
204 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
205 base = MAX_SETS;
206 offset = (layout->input_attachment_count +
207 layout->set[i].dynamic_offset_start +
208 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
209 /* fallthrough */
210 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
211 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
212 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
213 /* IBO-backed resources only need one packet for all graphics stages */
214 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
215 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
216 base, offset, count);
217 }
218 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
219 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
220 base, offset, count);
221 }
222 break;
223 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
224 base = MAX_SETS;
225 offset = (layout->set[i].input_attachment_start +
226 binding->input_attachment_offset) * A6XX_TEX_CONST_DWORDS;
227 case VK_DESCRIPTOR_TYPE_SAMPLER:
228 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
229 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
230 unsigned stage_log2;
231 for_each_bit(stage_log2, stages) {
232 VkShaderStageFlags stage = 1 << stage_log2;
233 emit_load_state(&cs, tu6_vkstage2opcode(stage),
234 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
235 ST6_SHADER : ST6_CONSTANTS,
236 tu6_tex_stage2sb(stage), base, offset, count);
237 }
238 break;
239 }
240 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
241 base = MAX_SETS;
242 offset = (layout->input_attachment_count +
243 layout->set[i].dynamic_offset_start +
244 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
245 /* fallthrough */
246 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
247 unsigned stage_log2;
248 for_each_bit(stage_log2, stages) {
249 VkShaderStageFlags stage = 1 << stage_log2;
250 emit_load_state(&cs, tu6_vkstage2opcode(stage), ST6_UBO,
251 tu6_ubo_stage2sb(stage), base, offset, count);
252 }
253 break;
254 }
255 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
256 unsigned stage_log2;
257 for_each_bit(stage_log2, stages) {
258 VkShaderStageFlags stage = 1 << stage_log2;
259 /* TODO: We could emit less CP_LOAD_STATE6 if we used
260 * struct-of-arrays instead of array-of-structs.
261 */
262 for (unsigned i = 0; i < count; i++) {
263 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
264 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
265 emit_load_state(&cs, tu6_vkstage2opcode(stage),
266 ST6_CONSTANTS, tu6_tex_stage2sb(stage),
267 base, tex_offset, 1);
268 emit_load_state(&cs, tu6_vkstage2opcode(stage),
269 ST6_SHADER, tu6_tex_stage2sb(stage),
270 base, sam_offset, 1);
271 }
272 }
273 break;
274 }
275 default:
276 unreachable("bad descriptor type");
277 }
278 }
279 }
280
281 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
282 }
283
284 struct tu_pipeline_builder
285 {
286 struct tu_device *device;
287 struct tu_pipeline_cache *cache;
288 struct tu_pipeline_layout *layout;
289 const VkAllocationCallbacks *alloc;
290 const VkGraphicsPipelineCreateInfo *create_info;
291
292 struct tu_shader *shaders[MESA_SHADER_STAGES];
293 uint32_t shader_offsets[MESA_SHADER_STAGES];
294 uint32_t binning_vs_offset;
295 uint32_t shader_total_size;
296
297 bool rasterizer_discard;
298 /* these states are affectd by rasterizer_discard */
299 VkSampleCountFlagBits samples;
300 bool use_color_attachments;
301 uint32_t color_attachment_count;
302 VkFormat color_attachment_formats[MAX_RTS];
303 VkFormat depth_attachment_format;
304 };
305
306 static enum tu_dynamic_state_bits
307 tu_dynamic_state_bit(VkDynamicState state)
308 {
309 switch (state) {
310 case VK_DYNAMIC_STATE_VIEWPORT:
311 return TU_DYNAMIC_VIEWPORT;
312 case VK_DYNAMIC_STATE_SCISSOR:
313 return TU_DYNAMIC_SCISSOR;
314 case VK_DYNAMIC_STATE_LINE_WIDTH:
315 return TU_DYNAMIC_LINE_WIDTH;
316 case VK_DYNAMIC_STATE_DEPTH_BIAS:
317 return TU_DYNAMIC_DEPTH_BIAS;
318 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
319 return TU_DYNAMIC_BLEND_CONSTANTS;
320 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
321 return TU_DYNAMIC_DEPTH_BOUNDS;
322 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
323 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
324 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
325 return TU_DYNAMIC_STENCIL_WRITE_MASK;
326 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
327 return TU_DYNAMIC_STENCIL_REFERENCE;
328 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
329 return TU_DYNAMIC_SAMPLE_LOCATIONS;
330 default:
331 unreachable("invalid dynamic state");
332 return 0;
333 }
334 }
335
336 static gl_shader_stage
337 tu_shader_stage(VkShaderStageFlagBits stage)
338 {
339 switch (stage) {
340 case VK_SHADER_STAGE_VERTEX_BIT:
341 return MESA_SHADER_VERTEX;
342 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
343 return MESA_SHADER_TESS_CTRL;
344 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
345 return MESA_SHADER_TESS_EVAL;
346 case VK_SHADER_STAGE_GEOMETRY_BIT:
347 return MESA_SHADER_GEOMETRY;
348 case VK_SHADER_STAGE_FRAGMENT_BIT:
349 return MESA_SHADER_FRAGMENT;
350 case VK_SHADER_STAGE_COMPUTE_BIT:
351 return MESA_SHADER_COMPUTE;
352 default:
353 unreachable("invalid VkShaderStageFlagBits");
354 return MESA_SHADER_NONE;
355 }
356 }
357
358 static bool
359 tu_logic_op_reads_dst(VkLogicOp op)
360 {
361 switch (op) {
362 case VK_LOGIC_OP_CLEAR:
363 case VK_LOGIC_OP_COPY:
364 case VK_LOGIC_OP_COPY_INVERTED:
365 case VK_LOGIC_OP_SET:
366 return false;
367 default:
368 return true;
369 }
370 }
371
372 static VkBlendFactor
373 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
374 {
375 /* treat dst alpha as 1.0 and avoid reading it */
376 switch (factor) {
377 case VK_BLEND_FACTOR_DST_ALPHA:
378 return VK_BLEND_FACTOR_ONE;
379 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
380 return VK_BLEND_FACTOR_ZERO;
381 default:
382 return factor;
383 }
384 }
385
386 static enum pc_di_primtype
387 tu6_primtype(VkPrimitiveTopology topology)
388 {
389 switch (topology) {
390 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
391 return DI_PT_POINTLIST;
392 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
393 return DI_PT_LINELIST;
394 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
395 return DI_PT_LINESTRIP;
396 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
397 return DI_PT_TRILIST;
398 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
399 return DI_PT_TRISTRIP;
400 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
401 return DI_PT_TRIFAN;
402 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
403 return DI_PT_LINE_ADJ;
404 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
405 return DI_PT_LINESTRIP_ADJ;
406 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
407 return DI_PT_TRI_ADJ;
408 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
409 return DI_PT_TRISTRIP_ADJ;
410 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
411 default:
412 unreachable("invalid primitive topology");
413 return DI_PT_NONE;
414 }
415 }
416
417 static enum adreno_compare_func
418 tu6_compare_func(VkCompareOp op)
419 {
420 switch (op) {
421 case VK_COMPARE_OP_NEVER:
422 return FUNC_NEVER;
423 case VK_COMPARE_OP_LESS:
424 return FUNC_LESS;
425 case VK_COMPARE_OP_EQUAL:
426 return FUNC_EQUAL;
427 case VK_COMPARE_OP_LESS_OR_EQUAL:
428 return FUNC_LEQUAL;
429 case VK_COMPARE_OP_GREATER:
430 return FUNC_GREATER;
431 case VK_COMPARE_OP_NOT_EQUAL:
432 return FUNC_NOTEQUAL;
433 case VK_COMPARE_OP_GREATER_OR_EQUAL:
434 return FUNC_GEQUAL;
435 case VK_COMPARE_OP_ALWAYS:
436 return FUNC_ALWAYS;
437 default:
438 unreachable("invalid VkCompareOp");
439 return FUNC_NEVER;
440 }
441 }
442
443 static enum adreno_stencil_op
444 tu6_stencil_op(VkStencilOp op)
445 {
446 switch (op) {
447 case VK_STENCIL_OP_KEEP:
448 return STENCIL_KEEP;
449 case VK_STENCIL_OP_ZERO:
450 return STENCIL_ZERO;
451 case VK_STENCIL_OP_REPLACE:
452 return STENCIL_REPLACE;
453 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
454 return STENCIL_INCR_CLAMP;
455 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
456 return STENCIL_DECR_CLAMP;
457 case VK_STENCIL_OP_INVERT:
458 return STENCIL_INVERT;
459 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
460 return STENCIL_INCR_WRAP;
461 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
462 return STENCIL_DECR_WRAP;
463 default:
464 unreachable("invalid VkStencilOp");
465 return STENCIL_KEEP;
466 }
467 }
468
469 static enum a3xx_rop_code
470 tu6_rop(VkLogicOp op)
471 {
472 switch (op) {
473 case VK_LOGIC_OP_CLEAR:
474 return ROP_CLEAR;
475 case VK_LOGIC_OP_AND:
476 return ROP_AND;
477 case VK_LOGIC_OP_AND_REVERSE:
478 return ROP_AND_REVERSE;
479 case VK_LOGIC_OP_COPY:
480 return ROP_COPY;
481 case VK_LOGIC_OP_AND_INVERTED:
482 return ROP_AND_INVERTED;
483 case VK_LOGIC_OP_NO_OP:
484 return ROP_NOOP;
485 case VK_LOGIC_OP_XOR:
486 return ROP_XOR;
487 case VK_LOGIC_OP_OR:
488 return ROP_OR;
489 case VK_LOGIC_OP_NOR:
490 return ROP_NOR;
491 case VK_LOGIC_OP_EQUIVALENT:
492 return ROP_EQUIV;
493 case VK_LOGIC_OP_INVERT:
494 return ROP_INVERT;
495 case VK_LOGIC_OP_OR_REVERSE:
496 return ROP_OR_REVERSE;
497 case VK_LOGIC_OP_COPY_INVERTED:
498 return ROP_COPY_INVERTED;
499 case VK_LOGIC_OP_OR_INVERTED:
500 return ROP_OR_INVERTED;
501 case VK_LOGIC_OP_NAND:
502 return ROP_NAND;
503 case VK_LOGIC_OP_SET:
504 return ROP_SET;
505 default:
506 unreachable("invalid VkLogicOp");
507 return ROP_NOOP;
508 }
509 }
510
511 static enum adreno_rb_blend_factor
512 tu6_blend_factor(VkBlendFactor factor)
513 {
514 switch (factor) {
515 case VK_BLEND_FACTOR_ZERO:
516 return FACTOR_ZERO;
517 case VK_BLEND_FACTOR_ONE:
518 return FACTOR_ONE;
519 case VK_BLEND_FACTOR_SRC_COLOR:
520 return FACTOR_SRC_COLOR;
521 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
522 return FACTOR_ONE_MINUS_SRC_COLOR;
523 case VK_BLEND_FACTOR_DST_COLOR:
524 return FACTOR_DST_COLOR;
525 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
526 return FACTOR_ONE_MINUS_DST_COLOR;
527 case VK_BLEND_FACTOR_SRC_ALPHA:
528 return FACTOR_SRC_ALPHA;
529 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
530 return FACTOR_ONE_MINUS_SRC_ALPHA;
531 case VK_BLEND_FACTOR_DST_ALPHA:
532 return FACTOR_DST_ALPHA;
533 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
534 return FACTOR_ONE_MINUS_DST_ALPHA;
535 case VK_BLEND_FACTOR_CONSTANT_COLOR:
536 return FACTOR_CONSTANT_COLOR;
537 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
538 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
539 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
540 return FACTOR_CONSTANT_ALPHA;
541 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
542 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
543 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
544 return FACTOR_SRC_ALPHA_SATURATE;
545 case VK_BLEND_FACTOR_SRC1_COLOR:
546 return FACTOR_SRC1_COLOR;
547 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
548 return FACTOR_ONE_MINUS_SRC1_COLOR;
549 case VK_BLEND_FACTOR_SRC1_ALPHA:
550 return FACTOR_SRC1_ALPHA;
551 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
552 return FACTOR_ONE_MINUS_SRC1_ALPHA;
553 default:
554 unreachable("invalid VkBlendFactor");
555 return FACTOR_ZERO;
556 }
557 }
558
559 static enum a3xx_rb_blend_opcode
560 tu6_blend_op(VkBlendOp op)
561 {
562 switch (op) {
563 case VK_BLEND_OP_ADD:
564 return BLEND_DST_PLUS_SRC;
565 case VK_BLEND_OP_SUBTRACT:
566 return BLEND_SRC_MINUS_DST;
567 case VK_BLEND_OP_REVERSE_SUBTRACT:
568 return BLEND_DST_MINUS_SRC;
569 case VK_BLEND_OP_MIN:
570 return BLEND_MIN_DST_SRC;
571 case VK_BLEND_OP_MAX:
572 return BLEND_MAX_DST_SRC;
573 default:
574 unreachable("invalid VkBlendOp");
575 return BLEND_DST_PLUS_SRC;
576 }
577 }
578
579 static uint32_t
580 emit_xs_config(const struct ir3_shader_variant *sh)
581 {
582 if (sh->instrlen) {
583 return A6XX_SP_VS_CONFIG_ENABLED |
584 COND(sh->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
585 COND(sh->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
586 COND(sh->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
587 COND(sh->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO);
588 } else {
589 return 0;
590 }
591 }
592
593 static void
594 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
595 const struct ir3_shader_variant *vs)
596 {
597 uint32_t sp_vs_ctrl =
598 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
599 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
600 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
601 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
602 if (vs->need_pixlod)
603 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
604 if (vs->need_fine_derivatives)
605 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_DIFF_FINE;
606
607 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
608 tu_cs_emit(cs, sp_vs_ctrl);
609
610 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
611 tu_cs_emit(cs, emit_xs_config(vs));
612 tu_cs_emit(cs, vs->instrlen);
613
614 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
615 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
616 A6XX_HLSQ_VS_CNTL_ENABLED);
617 }
618
619 static void
620 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
621 const struct ir3_shader_variant *hs)
622 {
623 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
624 tu_cs_emit(cs, 0);
625
626 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
627 tu_cs_emit(cs, emit_xs_config(hs));
628 tu_cs_emit(cs, hs->instrlen);
629
630 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
631 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
632 }
633
634 static void
635 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
636 const struct ir3_shader_variant *ds)
637 {
638 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
639 tu_cs_emit(cs, emit_xs_config(ds));
640 tu_cs_emit(cs, ds->instrlen);
641
642 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
643 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
644 }
645
646 static void
647 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
648 const struct ir3_shader_variant *gs)
649 {
650 bool has_gs = gs->type != MESA_SHADER_NONE;
651 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
652 tu_cs_emit(cs, 0);
653
654 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
655 tu_cs_emit(cs, emit_xs_config(gs));
656 tu_cs_emit(cs, gs->instrlen);
657
658 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
659 tu_cs_emit(cs, COND(has_gs, A6XX_HLSQ_GS_CNTL_ENABLED) |
660 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
661 }
662
663 static void
664 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
665 const struct ir3_shader_variant *fs)
666 {
667 uint32_t sp_fs_ctrl =
668 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
669 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
670 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
671 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
672 if (fs->total_in > 0)
673 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
674 if (fs->need_pixlod)
675 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
676 if (fs->need_fine_derivatives)
677 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_DIFF_FINE;
678
679 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
680 tu_cs_emit(cs, sp_fs_ctrl);
681
682 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
683 tu_cs_emit(cs, emit_xs_config(fs));
684 tu_cs_emit(cs, fs->instrlen);
685
686 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
687 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
688 A6XX_HLSQ_FS_CNTL_ENABLED);
689 }
690
691 static void
692 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
693 const struct ir3_shader_variant *v)
694 {
695 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
696 tu_cs_emit(cs, 0xff);
697
698 unsigned constlen = align(v->constlen, 4);
699 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
700 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
701 A6XX_HLSQ_CS_CNTL_ENABLED);
702
703 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
704 tu_cs_emit(cs, emit_xs_config(v));
705 tu_cs_emit(cs, v->instrlen);
706
707 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
708 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
709 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
710 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
711 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
712 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE) |
713 COND(v->need_fine_derivatives, A6XX_SP_CS_CTRL_REG0_DIFF_FINE));
714
715 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
716 tu_cs_emit(cs, 0x41);
717
718 uint32_t local_invocation_id =
719 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
720 uint32_t work_group_id =
721 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
722
723 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
724 tu_cs_emit(cs,
725 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
726 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
727 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
728 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
729 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
730 }
731
732 static void
733 tu6_emit_vs_system_values(struct tu_cs *cs,
734 const struct ir3_shader_variant *vs,
735 const struct ir3_shader_variant *gs)
736 {
737 const uint32_t vertexid_regid =
738 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
739 const uint32_t instanceid_regid =
740 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
741 const uint32_t primitiveid_regid = gs->type != MESA_SHADER_NONE ?
742 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
743 regid(63, 0);
744 const uint32_t gsheader_regid = gs->type != MESA_SHADER_NONE ?
745 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
746 regid(63, 0);
747
748 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
749 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
750 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
751 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
752 0xfc000000);
753 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
754 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
755 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
756 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
757 0xfc00); /* VFD_CONTROL_5 */
758 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
759 }
760
761 /* Add any missing varyings needed for stream-out. Otherwise varyings not
762 * used by fragment shader will be stripped out.
763 */
764 static void
765 tu6_link_streamout(struct ir3_shader_linkage *l,
766 const struct ir3_shader_variant *v)
767 {
768 const struct ir3_stream_output_info *info = &v->shader->stream_output;
769
770 /*
771 * First, any stream-out varyings not already in linkage map (ie. also
772 * consumed by frag shader) need to be added:
773 */
774 for (unsigned i = 0; i < info->num_outputs; i++) {
775 const struct ir3_stream_output *out = &info->output[i];
776 unsigned compmask =
777 (1 << (out->num_components + out->start_component)) - 1;
778 unsigned k = out->register_index;
779 unsigned idx, nextloc = 0;
780
781 /* psize/pos need to be the last entries in linkage map, and will
782 * get added link_stream_out, so skip over them:
783 */
784 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
785 v->outputs[k].slot == VARYING_SLOT_POS)
786 continue;
787
788 for (idx = 0; idx < l->cnt; idx++) {
789 if (l->var[idx].regid == v->outputs[k].regid)
790 break;
791 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
792 }
793
794 /* add if not already in linkage map: */
795 if (idx == l->cnt)
796 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
797
798 /* expand component-mask if needed, ie streaming out all components
799 * but frag shader doesn't consume all components:
800 */
801 if (compmask & ~l->var[idx].compmask) {
802 l->var[idx].compmask |= compmask;
803 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
804 util_last_bit(l->var[idx].compmask));
805 }
806 }
807 }
808
809 static void
810 tu6_setup_streamout(const struct ir3_shader_variant *v,
811 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
812 {
813 const struct ir3_stream_output_info *info = &v->shader->stream_output;
814
815 memset(tf, 0, sizeof(*tf));
816
817 tf->prog_count = align(l->max_loc, 2) / 2;
818
819 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
820
821 /* set stride info to the streamout state */
822 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
823 tf->stride[i] = info->stride[i];
824
825 for (unsigned i = 0; i < info->num_outputs; i++) {
826 const struct ir3_stream_output *out = &info->output[i];
827 unsigned k = out->register_index;
828 unsigned idx;
829
830 /* Skip it, if there's an unused reg in the middle of outputs. */
831 if (v->outputs[k].regid == INVALID_REG)
832 continue;
833
834 tf->ncomp[out->output_buffer] += out->num_components;
835
836 /* linkage map sorted by order frag shader wants things, so
837 * a bit less ideal here..
838 */
839 for (idx = 0; idx < l->cnt; idx++)
840 if (l->var[idx].regid == v->outputs[k].regid)
841 break;
842
843 debug_assert(idx < l->cnt);
844
845 for (unsigned j = 0; j < out->num_components; j++) {
846 unsigned c = j + out->start_component;
847 unsigned loc = l->var[idx].loc + c;
848 unsigned off = j + out->dst_offset; /* in dwords */
849
850 if (loc & 1) {
851 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
852 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
853 A6XX_VPC_SO_PROG_B_OFF(off * 4);
854 } else {
855 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
856 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
857 A6XX_VPC_SO_PROG_A_OFF(off * 4);
858 }
859 }
860 }
861
862 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
863 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
864 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
865 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
866 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
867 }
868
869 static void
870 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
871 enum a6xx_state_block block, uint32_t offset,
872 uint32_t size, uint32_t *dwords) {
873 assert(size % 4 == 0);
874
875 tu_cs_emit_pkt7(cs, opcode, 3 + size);
876 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
877 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
878 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
879 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
880 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
881
882 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
883 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
884 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
885
886 tu_cs_emit_array(cs, dwords, size);
887 }
888
889 static void
890 tu6_emit_link_map(struct tu_cs *cs,
891 const struct ir3_shader_variant *producer,
892 const struct ir3_shader_variant *consumer) {
893 const struct ir3_const_state *const_state = &consumer->shader->const_state;
894 uint32_t base = const_state->offsets.primitive_map;
895 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
896 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
897 int size = DIV_ROUND_UP(num_loc, 4);
898
899 size = (MIN2(size + base, consumer->constlen) - base) * 4;
900 if (size <= 0)
901 return;
902
903 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
904 patch_locs);
905 }
906
907 static uint16_t
908 gl_primitive_to_tess(uint16_t primitive) {
909 switch (primitive) {
910 case GL_POINTS:
911 return TESS_POINTS;
912 case GL_LINE_STRIP:
913 return TESS_LINES;
914 case GL_TRIANGLE_STRIP:
915 return TESS_CW_TRIS;
916 default:
917 unreachable("");
918 }
919 }
920
921 static void
922 tu6_emit_vpc(struct tu_cs *cs,
923 const struct ir3_shader_variant *vs,
924 const struct ir3_shader_variant *gs,
925 const struct ir3_shader_variant *fs,
926 bool binning_pass,
927 struct tu_streamout_state *tf)
928 {
929 bool has_gs = gs->type != MESA_SHADER_NONE;
930 const struct ir3_shader_variant *last_shader = has_gs ? gs : vs;
931 struct ir3_shader_linkage linkage = { 0 };
932 ir3_link_shaders(&linkage, last_shader, fs, true);
933
934 if (last_shader->shader->stream_output.num_outputs)
935 tu6_link_streamout(&linkage, last_shader);
936
937 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
938 tu_cs_emit(cs, ~linkage.varmask[0]);
939 tu_cs_emit(cs, ~linkage.varmask[1]);
940 tu_cs_emit(cs, ~linkage.varmask[2]);
941 tu_cs_emit(cs, ~linkage.varmask[3]);
942
943 /* a6xx finds position/pointsize at the end */
944 const uint32_t position_regid =
945 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
946 const uint32_t pointsize_regid =
947 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
948 const uint32_t layer_regid = has_gs ?
949 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
950
951 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
952 if (layer_regid != regid(63, 0)) {
953 layer_loc = linkage.max_loc;
954 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
955 }
956 if (position_regid != regid(63, 0)) {
957 position_loc = linkage.max_loc;
958 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
959 }
960 if (pointsize_regid != regid(63, 0)) {
961 pointsize_loc = linkage.max_loc;
962 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
963 }
964
965 if (last_shader->shader->stream_output.num_outputs)
966 tu6_setup_streamout(last_shader, &linkage, tf);
967
968 /* map outputs of the last shader to VPC */
969 assert(linkage.cnt <= 32);
970 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
971 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
972 uint32_t sp_out[16];
973 uint32_t sp_vpc_dst[8];
974 for (uint32_t i = 0; i < linkage.cnt; i++) {
975 ((uint16_t *) sp_out)[i] =
976 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
977 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
978 ((uint8_t *) sp_vpc_dst)[i] =
979 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
980 }
981
982 if (has_gs)
983 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
984 else
985 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
986 tu_cs_emit_array(cs, sp_out, sp_out_count);
987
988 if (has_gs)
989 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
990 else
991 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
992 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
993
994 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
995 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
996 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
997 0xff00ff00);
998
999 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
1000 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
1001 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
1002 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
1003
1004 if (has_gs) {
1005 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1006 tu_cs_emit(cs, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
1007 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
1008 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
1009 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
1010
1011 tu6_emit_link_map(cs, vs, gs);
1012
1013 uint32_t primitive_regid =
1014 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
1015 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
1016 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
1017 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
1018 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
1019
1020 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
1021 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
1022
1023 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
1024 tu_cs_emit(cs, CONDREG(layer_regid,
1025 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
1026
1027 uint32_t flags_regid = ir3_find_output_regid(gs,
1028 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
1029
1030 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
1031 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
1032 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
1033
1034 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
1035 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
1036 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
1037 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
1038 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
1039
1040 uint32_t vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
1041 uint16_t output =
1042 gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
1043 uint32_t invocations = gs->shader->nir->info.gs.invocations - 1;
1044 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1045 tu_cs_emit(cs,
1046 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1047 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1048 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1049
1050 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1051 tu_cs_emit(cs, 0);
1052
1053 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
1054 tu_cs_emit(cs, 0);
1055
1056 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1057 tu_cs_emit(cs, 0xff);
1058
1059 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
1060 tu_cs_emit(cs, 0xffff00);
1061
1062 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1063 uint32_t vec4_size =
1064 gs->shader->nir->info.gs.vertices_in *
1065 DIV_ROUND_UP(vs->shader->output_size, 4);
1066 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1067 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1068
1069 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
1070 tu_cs_emit(cs, 0);
1071
1072 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
1073 tu_cs_emit(cs, vs->shader->output_size);
1074 }
1075
1076 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
1077 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
1078
1079 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
1080 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
1081 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
1082 }
1083
1084 static int
1085 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1086 uint32_t index,
1087 uint8_t *interp_mode,
1088 uint8_t *ps_repl_mode)
1089 {
1090 enum
1091 {
1092 INTERP_SMOOTH = 0,
1093 INTERP_FLAT = 1,
1094 INTERP_ZERO = 2,
1095 INTERP_ONE = 3,
1096 };
1097 enum
1098 {
1099 PS_REPL_NONE = 0,
1100 PS_REPL_S = 1,
1101 PS_REPL_T = 2,
1102 PS_REPL_ONE_MINUS_T = 3,
1103 };
1104
1105 const uint32_t compmask = fs->inputs[index].compmask;
1106
1107 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1108 * fourth component occupy three consecutive varying slots
1109 */
1110 int shift = 0;
1111 *interp_mode = 0;
1112 *ps_repl_mode = 0;
1113 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1114 if (compmask & 0x1) {
1115 *ps_repl_mode |= PS_REPL_S << shift;
1116 shift += 2;
1117 }
1118 if (compmask & 0x2) {
1119 *ps_repl_mode |= PS_REPL_T << shift;
1120 shift += 2;
1121 }
1122 if (compmask & 0x4) {
1123 *interp_mode |= INTERP_ZERO << shift;
1124 shift += 2;
1125 }
1126 if (compmask & 0x8) {
1127 *interp_mode |= INTERP_ONE << 6;
1128 shift += 2;
1129 }
1130 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1131 fs->inputs[index].rasterflat) {
1132 for (int i = 0; i < 4; i++) {
1133 if (compmask & (1 << i)) {
1134 *interp_mode |= INTERP_FLAT << shift;
1135 shift += 2;
1136 }
1137 }
1138 }
1139
1140 return shift;
1141 }
1142
1143 static void
1144 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1145 const struct ir3_shader_variant *fs,
1146 bool binning_pass)
1147 {
1148 uint32_t interp_modes[8] = { 0 };
1149 uint32_t ps_repl_modes[8] = { 0 };
1150
1151 if (!binning_pass) {
1152 for (int i = -1;
1153 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1154
1155 /* get the mode for input i */
1156 uint8_t interp_mode;
1157 uint8_t ps_repl_mode;
1158 const int bits =
1159 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1160
1161 /* OR the mode into the array */
1162 const uint32_t inloc = fs->inputs[i].inloc * 2;
1163 uint32_t n = inloc / 32;
1164 uint32_t shift = inloc % 32;
1165 interp_modes[n] |= interp_mode << shift;
1166 ps_repl_modes[n] |= ps_repl_mode << shift;
1167 if (shift + bits > 32) {
1168 n++;
1169 shift = 32 - shift;
1170
1171 interp_modes[n] |= interp_mode >> shift;
1172 ps_repl_modes[n] |= ps_repl_mode >> shift;
1173 }
1174 }
1175 }
1176
1177 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1178 tu_cs_emit_array(cs, interp_modes, 8);
1179
1180 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1181 tu_cs_emit_array(cs, ps_repl_modes, 8);
1182 }
1183
1184 static void
1185 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1186 {
1187 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1188 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
1189 uint32_t smask_in_regid;
1190
1191 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
1192 bool enable_varyings = fs->total_in > 0;
1193
1194 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1195 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1196 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1197 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1198 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1199 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1200 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1201 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1202 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1203
1204 if (fs->num_sampler_prefetch > 0) {
1205 assert(VALIDREG(ij_pix_regid));
1206 /* also, it seems like ij_pix is *required* to be r0.x */
1207 assert(ij_pix_regid == regid(0, 0));
1208 }
1209
1210 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1211 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1212 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1213 0x7000); // XXX);
1214 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1215 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1216 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1217 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1218 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1219 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1220 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1221 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1222 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1223 }
1224
1225 if (fs->num_sampler_prefetch > 0) {
1226 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1227 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1228 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1229 tu_cs_emit(cs,
1230 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1231 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1232 }
1233 }
1234
1235 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1236 tu_cs_emit(cs, 0x7);
1237 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1238 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1239 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1240 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1241 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1242 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1243 0xfc00fc00);
1244 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1245 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1246 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1247 0x0000fc00);
1248 tu_cs_emit(cs, 0xfc);
1249
1250 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1251 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1252
1253 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1254 tu_cs_emit(cs, 0xff); /* XXX */
1255
1256 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1257 tu_cs_emit(cs,
1258 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1259 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1260 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1261 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1262 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1263 COND(fs->frag_coord,
1264 A6XX_GRAS_CNTL_SIZE |
1265 A6XX_GRAS_CNTL_XCOORD |
1266 A6XX_GRAS_CNTL_YCOORD |
1267 A6XX_GRAS_CNTL_ZCOORD |
1268 A6XX_GRAS_CNTL_WCOORD) |
1269 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1270
1271 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1272 tu_cs_emit(cs,
1273 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1274 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1275 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1276 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1277 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1278 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1279 COND(fs->frag_coord,
1280 A6XX_RB_RENDER_CONTROL0_SIZE |
1281 A6XX_RB_RENDER_CONTROL0_XCOORD |
1282 A6XX_RB_RENDER_CONTROL0_YCOORD |
1283 A6XX_RB_RENDER_CONTROL0_ZCOORD |
1284 A6XX_RB_RENDER_CONTROL0_WCOORD) |
1285 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1286 tu_cs_emit(cs,
1287 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1288 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1289 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1290 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1291
1292 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1293 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1294
1295 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1296 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1297
1298 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1299 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1300 }
1301
1302 static void
1303 tu6_emit_fs_outputs(struct tu_cs *cs,
1304 const struct ir3_shader_variant *fs,
1305 uint32_t mrt_count)
1306 {
1307 uint32_t smask_regid, posz_regid;
1308
1309 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1310 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1311
1312 uint32_t fragdata_regid[8];
1313 if (fs->color0_mrt) {
1314 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1315 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1316 fragdata_regid[i] = fragdata_regid[0];
1317 } else {
1318 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1319 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1320 }
1321
1322 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1323 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1324 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1325 0xfc000000);
1326 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1327
1328 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1329 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1330 // TODO we could have a mix of half and full precision outputs,
1331 // we really need to figure out half-precision from IR3_REG_HALF
1332 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1333 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1334 }
1335
1336 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1337 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1338 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
1339 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1340
1341 uint32_t gras_su_depth_plane_cntl = 0;
1342 uint32_t rb_depth_plane_cntl = 0;
1343 if (fs->no_earlyz || fs->writes_pos) {
1344 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1345 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1346 }
1347
1348 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1349 tu_cs_emit(cs, gras_su_depth_plane_cntl);
1350
1351 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1352 tu_cs_emit(cs, rb_depth_plane_cntl);
1353 }
1354
1355 static void
1356 tu6_emit_shader_object(struct tu_cs *cs,
1357 gl_shader_stage stage,
1358 const struct ir3_shader_variant *variant,
1359 const struct tu_bo *binary_bo,
1360 uint32_t binary_offset)
1361 {
1362 uint16_t reg;
1363 uint8_t opcode;
1364 enum a6xx_state_block sb;
1365 switch (stage) {
1366 case MESA_SHADER_VERTEX:
1367 reg = REG_A6XX_SP_VS_OBJ_START_LO;
1368 opcode = CP_LOAD_STATE6_GEOM;
1369 sb = SB6_VS_SHADER;
1370 break;
1371 case MESA_SHADER_TESS_CTRL:
1372 reg = REG_A6XX_SP_HS_OBJ_START_LO;
1373 opcode = CP_LOAD_STATE6_GEOM;
1374 sb = SB6_HS_SHADER;
1375 break;
1376 case MESA_SHADER_TESS_EVAL:
1377 reg = REG_A6XX_SP_DS_OBJ_START_LO;
1378 opcode = CP_LOAD_STATE6_GEOM;
1379 sb = SB6_DS_SHADER;
1380 break;
1381 case MESA_SHADER_GEOMETRY:
1382 reg = REG_A6XX_SP_GS_OBJ_START_LO;
1383 opcode = CP_LOAD_STATE6_GEOM;
1384 sb = SB6_GS_SHADER;
1385 break;
1386 case MESA_SHADER_FRAGMENT:
1387 reg = REG_A6XX_SP_FS_OBJ_START_LO;
1388 opcode = CP_LOAD_STATE6_FRAG;
1389 sb = SB6_FS_SHADER;
1390 break;
1391 case MESA_SHADER_COMPUTE:
1392 reg = REG_A6XX_SP_CS_OBJ_START_LO;
1393 opcode = CP_LOAD_STATE6_FRAG;
1394 sb = SB6_CS_SHADER;
1395 break;
1396 default:
1397 unreachable("invalid gl_shader_stage");
1398 opcode = CP_LOAD_STATE6_GEOM;
1399 sb = SB6_VS_SHADER;
1400 break;
1401 }
1402
1403 if (!variant->instrlen) {
1404 tu_cs_emit_pkt4(cs, reg, 2);
1405 tu_cs_emit_qw(cs, 0);
1406 return;
1407 }
1408
1409 assert(variant->type == stage);
1410
1411 const uint64_t binary_iova = binary_bo->iova + binary_offset;
1412 assert((binary_iova & 0xf) == 0);
1413 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1414 * of the shader. this could be a potential source of problems at some point
1415 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1416 */
1417
1418 tu_cs_emit_pkt4(cs, reg, 2);
1419 tu_cs_emit_qw(cs, binary_iova);
1420
1421 /* always indirect */
1422 const bool indirect = true;
1423 if (indirect) {
1424 tu_cs_emit_pkt7(cs, opcode, 3);
1425 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1426 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1427 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1428 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1429 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1430 tu_cs_emit_qw(cs, binary_iova);
1431 } else {
1432 const void *binary = binary_bo->map + binary_offset;
1433
1434 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
1435 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1436 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1437 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1438 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1439 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1440 tu_cs_emit_qw(cs, 0);
1441 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
1442 }
1443 }
1444
1445 static void
1446 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
1447 uint32_t opcode, enum a6xx_state_block block)
1448 {
1449 /* dummy variant */
1450 if (!v->shader)
1451 return;
1452
1453 const struct ir3_const_state *const_state = &v->shader->const_state;
1454 uint32_t base = const_state->offsets.immediate;
1455 int size = const_state->immediates_count;
1456
1457 /* truncate size to avoid writing constants that shader
1458 * does not use:
1459 */
1460 size = MIN2(size + base, v->constlen) - base;
1461
1462 if (size <= 0)
1463 return;
1464
1465 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1466 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1467 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1468 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1469 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1470 CP_LOAD_STATE6_0_NUM_UNIT(size));
1471 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1472 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1473
1474 for (unsigned i = 0; i < size; i++) {
1475 tu_cs_emit(cs, const_state->immediates[i].val[0]);
1476 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1477 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1478 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1479 }
1480 }
1481
1482 static void
1483 tu6_emit_geometry_consts(struct tu_cs *cs,
1484 const struct ir3_shader_variant *vs,
1485 const struct ir3_shader_variant *gs) {
1486 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1487
1488 uint32_t params[4] = {
1489 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1490 vs->shader->output_size * 4, /* vertex stride */
1491 0,
1492 0,
1493 };
1494 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1495 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1496 ARRAY_SIZE(params), params);
1497
1498 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1499 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1500 ARRAY_SIZE(params), params);
1501 }
1502
1503 static void
1504 tu6_emit_program(struct tu_cs *cs,
1505 const struct tu_pipeline_builder *builder,
1506 const struct tu_bo *binary_bo,
1507 bool binning_pass,
1508 struct tu_streamout_state *tf)
1509 {
1510 static const struct ir3_shader_variant dummy_variant = {
1511 .type = MESA_SHADER_NONE
1512 };
1513 assert(builder->shaders[MESA_SHADER_VERTEX]);
1514 const struct ir3_shader_variant *vs =
1515 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1516 const struct ir3_shader_variant *hs =
1517 builder->shaders[MESA_SHADER_TESS_CTRL]
1518 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1519 : &dummy_variant;
1520 const struct ir3_shader_variant *ds =
1521 builder->shaders[MESA_SHADER_TESS_EVAL]
1522 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1523 : &dummy_variant;
1524 const struct ir3_shader_variant *gs =
1525 builder->shaders[MESA_SHADER_GEOMETRY]
1526 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1527 : &dummy_variant;
1528 const struct ir3_shader_variant *fs =
1529 builder->shaders[MESA_SHADER_FRAGMENT]
1530 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1531 : &dummy_variant;
1532 bool has_gs = gs->type != MESA_SHADER_NONE;
1533
1534 if (binning_pass) {
1535 /* if we have streamout, use full VS in binning pass, as the
1536 * binning pass VS will have outputs on other than position/psize
1537 * stripped out:
1538 */
1539 if (vs->shader->stream_output.num_outputs == 0)
1540 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1541 fs = &dummy_variant;
1542 }
1543
1544 tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1545 tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1546 tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1547 tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1548 tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1549
1550 tu6_emit_vs_system_values(cs, vs, gs);
1551 tu6_emit_vpc(cs, vs, gs, fs, binning_pass, tf);
1552 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1553 tu6_emit_fs_inputs(cs, fs);
1554 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1555
1556 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1557 binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1558 if (has_gs)
1559 tu6_emit_shader_object(cs, MESA_SHADER_GEOMETRY, gs, binary_bo,
1560 builder->shader_offsets[MESA_SHADER_GEOMETRY]);
1561 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1562 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1563
1564 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1565 if (has_gs) {
1566 tu6_emit_immediates(cs, gs, CP_LOAD_STATE6_GEOM, SB6_GS_SHADER);
1567 tu6_emit_geometry_consts(cs, vs, gs);
1568 }
1569 if (!binning_pass)
1570 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1571 }
1572
1573 static void
1574 tu6_emit_vertex_input(struct tu_cs *cs,
1575 const struct ir3_shader_variant *vs,
1576 const VkPipelineVertexInputStateCreateInfo *info,
1577 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1578 uint32_t *count)
1579 {
1580 uint32_t vfd_fetch_idx = 0;
1581 uint32_t vfd_decode_idx = 0;
1582 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1583
1584 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1585 const VkVertexInputBindingDescription *binding =
1586 &info->pVertexBindingDescriptions[i];
1587
1588 tu_cs_emit_regs(cs,
1589 A6XX_VFD_FETCH_STRIDE(vfd_fetch_idx, binding->stride));
1590
1591 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1592 binding_instanced |= 1 << binding->binding;
1593
1594 bindings[vfd_fetch_idx] = binding->binding;
1595 vfd_fetch_idx++;
1596 }
1597
1598 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1599
1600 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1601 const VkVertexInputAttributeDescription *attr =
1602 &info->pVertexAttributeDescriptions[i];
1603 uint32_t binding_idx, input_idx;
1604
1605 for (binding_idx = 0; binding_idx < vfd_fetch_idx; binding_idx++) {
1606 if (bindings[binding_idx] == attr->binding)
1607 break;
1608 }
1609 assert(binding_idx < vfd_fetch_idx);
1610
1611 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1612 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1613 break;
1614 }
1615
1616 /* attribute not used, skip it */
1617 if (input_idx == vs->inputs_count)
1618 continue;
1619
1620 const struct tu_native_format format = tu6_format_vtx(attr->format);
1621 tu_cs_emit_regs(cs,
1622 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1623 .idx = binding_idx,
1624 .offset = attr->offset,
1625 .instanced = binding_instanced & (1 << attr->binding),
1626 .format = format.fmt,
1627 .swap = format.swap,
1628 .unk30 = 1,
1629 ._float = !vk_format_is_int(attr->format)),
1630 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1631
1632 tu_cs_emit_regs(cs,
1633 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1634 .writemask = vs->inputs[input_idx].compmask,
1635 .regid = vs->inputs[input_idx].regid));
1636
1637 vfd_decode_idx++;
1638 }
1639
1640 tu_cs_emit_regs(cs,
1641 A6XX_VFD_CONTROL_0(
1642 .fetch_cnt = vfd_fetch_idx,
1643 .decode_cnt = vfd_decode_idx));
1644
1645 *count = vfd_fetch_idx;
1646 }
1647
1648 static uint32_t
1649 tu6_guardband_adj(uint32_t v)
1650 {
1651 if (v > 256)
1652 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1653 else
1654 return 511;
1655 }
1656
1657 void
1658 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1659 {
1660 float offsets[3];
1661 float scales[3];
1662 scales[0] = viewport->width / 2.0f;
1663 scales[1] = viewport->height / 2.0f;
1664 scales[2] = viewport->maxDepth - viewport->minDepth;
1665 offsets[0] = viewport->x + scales[0];
1666 offsets[1] = viewport->y + scales[1];
1667 offsets[2] = viewport->minDepth;
1668
1669 VkOffset2D min;
1670 VkOffset2D max;
1671 min.x = (int32_t) viewport->x;
1672 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1673 if (viewport->height >= 0.0f) {
1674 min.y = (int32_t) viewport->y;
1675 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1676 } else {
1677 min.y = (int32_t)(viewport->y + viewport->height);
1678 max.y = (int32_t) ceilf(viewport->y);
1679 }
1680 /* the spec allows viewport->height to be 0.0f */
1681 if (min.y == max.y)
1682 max.y++;
1683 assert(min.x >= 0 && min.x < max.x);
1684 assert(min.y >= 0 && min.y < max.y);
1685
1686 VkExtent2D guardband_adj;
1687 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1688 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1689
1690 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1691 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1692 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1693 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1694 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1695 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1696 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1697
1698 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1699 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1700 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1701 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1702 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1703
1704 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1705 tu_cs_emit(cs,
1706 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1707 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1708
1709 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1710 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1711
1712 tu_cs_emit_regs(cs,
1713 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1714 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1715
1716 tu_cs_emit_regs(cs,
1717 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1718 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1719 }
1720
1721 void
1722 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1723 {
1724 const VkOffset2D min = scissor->offset;
1725 const VkOffset2D max = {
1726 scissor->offset.x + scissor->extent.width,
1727 scissor->offset.y + scissor->extent.height,
1728 };
1729
1730 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1731 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1732 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1733 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1734 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1735 }
1736
1737 void
1738 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1739 {
1740 if (!samp_loc) {
1741 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1742 tu_cs_emit(cs, 0);
1743
1744 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1745 tu_cs_emit(cs, 0);
1746
1747 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1748 tu_cs_emit(cs, 0);
1749 return;
1750 }
1751
1752 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1753 assert(samp_loc->sampleLocationGridSize.width == 1);
1754 assert(samp_loc->sampleLocationGridSize.height == 1);
1755
1756 uint32_t sample_config =
1757 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1758 uint32_t sample_locations = 0;
1759 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1760 sample_locations |=
1761 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1762 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1763 }
1764
1765 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1766 tu_cs_emit(cs, sample_config);
1767 tu_cs_emit(cs, sample_locations);
1768
1769 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1770 tu_cs_emit(cs, sample_config);
1771 tu_cs_emit(cs, sample_locations);
1772
1773 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1774 tu_cs_emit(cs, sample_config);
1775 tu_cs_emit(cs, sample_locations);
1776 }
1777
1778 static void
1779 tu6_emit_gras_unknowns(struct tu_cs *cs)
1780 {
1781 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1782 tu_cs_emit(cs, 0x0);
1783 }
1784
1785 static void
1786 tu6_emit_point_size(struct tu_cs *cs)
1787 {
1788 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1789 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1790 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1791 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1792 }
1793
1794 static uint32_t
1795 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1796 VkSampleCountFlagBits samples)
1797 {
1798 uint32_t gras_su_cntl = 0;
1799
1800 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1801 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1802 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1803 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1804
1805 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1806 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1807
1808 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1809
1810 if (rast_info->depthBiasEnable)
1811 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1812
1813 if (samples > VK_SAMPLE_COUNT_1_BIT)
1814 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1815
1816 return gras_su_cntl;
1817 }
1818
1819 void
1820 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1821 uint32_t gras_su_cntl,
1822 float line_width)
1823 {
1824 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1825 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1826
1827 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1828 tu_cs_emit(cs, gras_su_cntl);
1829 }
1830
1831 void
1832 tu6_emit_depth_bias(struct tu_cs *cs,
1833 float constant_factor,
1834 float clamp,
1835 float slope_factor)
1836 {
1837 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1838 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1839 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1840 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1841 }
1842
1843 static void
1844 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1845 {
1846 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1847 tu_cs_emit(cs, 0);
1848 }
1849
1850 static void
1851 tu6_emit_depth_control(struct tu_cs *cs,
1852 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1853 const VkPipelineRasterizationStateCreateInfo *rast_info)
1854 {
1855 assert(!ds_info->depthBoundsTestEnable);
1856
1857 uint32_t rb_depth_cntl = 0;
1858 if (ds_info->depthTestEnable) {
1859 rb_depth_cntl |=
1860 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1861 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1862 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1863
1864 if (rast_info->depthClampEnable)
1865 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1866
1867 if (ds_info->depthWriteEnable)
1868 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1869 }
1870
1871 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1872 tu_cs_emit(cs, rb_depth_cntl);
1873 }
1874
1875 static void
1876 tu6_emit_stencil_control(struct tu_cs *cs,
1877 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1878 {
1879 uint32_t rb_stencil_control = 0;
1880 if (ds_info->stencilTestEnable) {
1881 const VkStencilOpState *front = &ds_info->front;
1882 const VkStencilOpState *back = &ds_info->back;
1883 rb_stencil_control |=
1884 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1885 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1886 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1887 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1888 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1889 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1890 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1891 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1892 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1893 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1894 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1895 }
1896
1897 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1898 tu_cs_emit(cs, rb_stencil_control);
1899 }
1900
1901 void
1902 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1903 {
1904 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1905 tu_cs_emit(
1906 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1907 }
1908
1909 void
1910 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1911 {
1912 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1913 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1914 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1915 }
1916
1917 void
1918 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1919 {
1920 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1921 tu_cs_emit(cs,
1922 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1923 }
1924
1925 static uint32_t
1926 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1927 bool has_alpha)
1928 {
1929 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1930 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1931 has_alpha ? att->srcColorBlendFactor
1932 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1933 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1934 has_alpha ? att->dstColorBlendFactor
1935 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1936 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1937 const enum adreno_rb_blend_factor src_alpha_factor =
1938 tu6_blend_factor(att->srcAlphaBlendFactor);
1939 const enum adreno_rb_blend_factor dst_alpha_factor =
1940 tu6_blend_factor(att->dstAlphaBlendFactor);
1941
1942 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1943 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1944 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1945 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1946 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1947 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1948 }
1949
1950 static uint32_t
1951 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1952 uint32_t rb_mrt_control_rop,
1953 bool is_int,
1954 bool has_alpha)
1955 {
1956 uint32_t rb_mrt_control =
1957 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1958
1959 /* ignore blending and logic op for integer attachments */
1960 if (is_int) {
1961 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1962 return rb_mrt_control;
1963 }
1964
1965 rb_mrt_control |= rb_mrt_control_rop;
1966
1967 if (att->blendEnable) {
1968 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1969
1970 if (has_alpha)
1971 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1972 }
1973
1974 return rb_mrt_control;
1975 }
1976
1977 static void
1978 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1979 const VkPipelineColorBlendStateCreateInfo *blend_info,
1980 const VkFormat attachment_formats[MAX_RTS],
1981 uint32_t *blend_enable_mask)
1982 {
1983 *blend_enable_mask = 0;
1984
1985 bool rop_reads_dst = false;
1986 uint32_t rb_mrt_control_rop = 0;
1987 if (blend_info->logicOpEnable) {
1988 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1989 rb_mrt_control_rop =
1990 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1991 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1992 }
1993
1994 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1995 const VkPipelineColorBlendAttachmentState *att =
1996 &blend_info->pAttachments[i];
1997 const VkFormat format = attachment_formats[i];
1998
1999 uint32_t rb_mrt_control = 0;
2000 uint32_t rb_mrt_blend_control = 0;
2001 if (format != VK_FORMAT_UNDEFINED) {
2002 const bool is_int = vk_format_is_int(format);
2003 const bool has_alpha = vk_format_has_alpha(format);
2004
2005 rb_mrt_control =
2006 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
2007 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
2008
2009 if (att->blendEnable || rop_reads_dst)
2010 *blend_enable_mask |= 1 << i;
2011 }
2012
2013 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
2014 tu_cs_emit(cs, rb_mrt_control);
2015 tu_cs_emit(cs, rb_mrt_blend_control);
2016 }
2017 }
2018
2019 static void
2020 tu6_emit_blend_control(struct tu_cs *cs,
2021 uint32_t blend_enable_mask,
2022 const VkPipelineMultisampleStateCreateInfo *msaa_info)
2023 {
2024 assert(!msaa_info->alphaToOneEnable);
2025
2026 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
2027 if (blend_enable_mask)
2028 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
2029 if (msaa_info->alphaToCoverageEnable)
2030 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
2031
2032 const uint32_t sample_mask =
2033 msaa_info->pSampleMask ? *msaa_info->pSampleMask
2034 : ((1 << msaa_info->rasterizationSamples) - 1);
2035
2036 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
2037 uint32_t rb_blend_cntl =
2038 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
2039 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
2040 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
2041 if (msaa_info->alphaToCoverageEnable)
2042 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
2043
2044 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
2045 tu_cs_emit(cs, sp_blend_cntl);
2046
2047 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
2048 tu_cs_emit(cs, rb_blend_cntl);
2049 }
2050
2051 void
2052 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
2053 {
2054 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2055 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
2056 }
2057
2058 static VkResult
2059 tu_pipeline_create(struct tu_device *dev,
2060 struct tu_pipeline_layout *layout,
2061 bool compute,
2062 const VkAllocationCallbacks *pAllocator,
2063 struct tu_pipeline **out_pipeline)
2064 {
2065 struct tu_pipeline *pipeline =
2066 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
2067 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2068 if (!pipeline)
2069 return VK_ERROR_OUT_OF_HOST_MEMORY;
2070
2071 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
2072
2073 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
2074 * that LOAD_STATE can potentially take up a large amount of space so we
2075 * calculate its size explicitly.
2076 */
2077 unsigned load_state_size = tu6_load_state_size(layout, compute);
2078 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size);
2079 if (result != VK_SUCCESS) {
2080 vk_free2(&dev->alloc, pAllocator, pipeline);
2081 return result;
2082 }
2083
2084 *out_pipeline = pipeline;
2085
2086 return VK_SUCCESS;
2087 }
2088
2089 static VkResult
2090 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
2091 {
2092 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
2093 NULL
2094 };
2095 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
2096 gl_shader_stage stage =
2097 tu_shader_stage(builder->create_info->pStages[i].stage);
2098 stage_infos[stage] = &builder->create_info->pStages[i];
2099 }
2100
2101 struct tu_shader_compile_options options;
2102 tu_shader_compile_options_init(&options, builder->create_info);
2103
2104 /* compile shaders in reverse order */
2105 struct tu_shader *next_stage_shader = NULL;
2106 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
2107 stage > MESA_SHADER_NONE; stage--) {
2108 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
2109 if (!stage_info)
2110 continue;
2111
2112 struct tu_shader *shader =
2113 tu_shader_create(builder->device, stage, stage_info, builder->layout,
2114 builder->alloc);
2115 if (!shader)
2116 return VK_ERROR_OUT_OF_HOST_MEMORY;
2117
2118 VkResult result =
2119 tu_shader_compile(builder->device, shader, next_stage_shader,
2120 &options, builder->alloc);
2121 if (result != VK_SUCCESS)
2122 return result;
2123
2124 builder->shaders[stage] = shader;
2125 builder->shader_offsets[stage] = builder->shader_total_size;
2126 builder->shader_total_size +=
2127 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
2128
2129 next_stage_shader = shader;
2130 }
2131
2132 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2133 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2134 const struct ir3_shader_variant *variant;
2135
2136 if (vs->ir3_shader.stream_output.num_outputs)
2137 variant = &vs->variants[0];
2138 else
2139 variant = &vs->variants[1];
2140
2141 builder->binning_vs_offset = builder->shader_total_size;
2142 builder->shader_total_size +=
2143 sizeof(uint32_t) * variant->info.sizedwords;
2144 }
2145
2146 return VK_SUCCESS;
2147 }
2148
2149 static VkResult
2150 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
2151 struct tu_pipeline *pipeline)
2152 {
2153 struct tu_bo *bo = &pipeline->program.binary_bo;
2154
2155 VkResult result =
2156 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
2157 if (result != VK_SUCCESS)
2158 return result;
2159
2160 result = tu_bo_map(builder->device, bo);
2161 if (result != VK_SUCCESS)
2162 return result;
2163
2164 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2165 const struct tu_shader *shader = builder->shaders[i];
2166 if (!shader)
2167 continue;
2168
2169 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
2170 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
2171 }
2172
2173 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2174 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2175 const struct ir3_shader_variant *variant;
2176 void *bin;
2177
2178 if (vs->ir3_shader.stream_output.num_outputs) {
2179 variant = &vs->variants[0];
2180 bin = vs->binary;
2181 } else {
2182 variant = &vs->variants[1];
2183 bin = vs->binning_binary;
2184 }
2185
2186 memcpy(bo->map + builder->binning_vs_offset, bin,
2187 sizeof(uint32_t) * variant->info.sizedwords);
2188 }
2189
2190 return VK_SUCCESS;
2191 }
2192
2193 static void
2194 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2195 struct tu_pipeline *pipeline)
2196 {
2197 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2198 builder->create_info->pDynamicState;
2199
2200 if (!dynamic_info)
2201 return;
2202
2203 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2204 pipeline->dynamic_state.mask |=
2205 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
2206 }
2207 }
2208
2209 static void
2210 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2211 struct tu_shader *shader,
2212 struct ir3_shader_variant *v)
2213 {
2214 link->ubo_state = v->shader->ubo_state;
2215 link->const_state = v->shader->const_state;
2216 link->constlen = v->constlen;
2217 link->push_consts = shader->push_consts;
2218 }
2219
2220 static void
2221 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2222 struct tu_pipeline *pipeline)
2223 {
2224 struct tu_cs prog_cs;
2225 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2226 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
2227 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2228
2229 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2230 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
2231 pipeline->program.binning_state_ib =
2232 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2233
2234 VkShaderStageFlags stages = 0;
2235 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2236 stages |= builder->create_info->pStages[i].stage;
2237 }
2238 pipeline->active_stages = stages;
2239
2240 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2241 if (!builder->shaders[i])
2242 continue;
2243
2244 tu_pipeline_set_linkage(&pipeline->program.link[i],
2245 builder->shaders[i],
2246 &builder->shaders[i]->variants[0]);
2247 }
2248
2249 if (builder->shaders[MESA_SHADER_FRAGMENT]) {
2250 memcpy(pipeline->program.input_attachment_idx,
2251 builder->shaders[MESA_SHADER_FRAGMENT]->attachment_idx,
2252 sizeof(pipeline->program.input_attachment_idx));
2253 }
2254 }
2255
2256 static void
2257 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2258 struct tu_pipeline *pipeline)
2259 {
2260 const VkPipelineVertexInputStateCreateInfo *vi_info =
2261 builder->create_info->pVertexInputState;
2262 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2263
2264 struct tu_cs vi_cs;
2265 tu_cs_begin_sub_stream(&pipeline->cs,
2266 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2267 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
2268 pipeline->vi.bindings, &pipeline->vi.count);
2269 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2270
2271 if (vs->has_binning_pass) {
2272 tu_cs_begin_sub_stream(&pipeline->cs,
2273 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2274 tu6_emit_vertex_input(
2275 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
2276 &pipeline->vi.binning_count);
2277 pipeline->vi.binning_state_ib =
2278 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2279 }
2280 }
2281
2282 static void
2283 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2284 struct tu_pipeline *pipeline)
2285 {
2286 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2287 builder->create_info->pInputAssemblyState;
2288
2289 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2290 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2291 }
2292
2293 static void
2294 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2295 struct tu_pipeline *pipeline)
2296 {
2297 /* The spec says:
2298 *
2299 * pViewportState is a pointer to an instance of the
2300 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2301 * pipeline has rasterization disabled."
2302 *
2303 * We leave the relevant registers stale in that case.
2304 */
2305 if (builder->rasterizer_discard)
2306 return;
2307
2308 const VkPipelineViewportStateCreateInfo *vp_info =
2309 builder->create_info->pViewportState;
2310
2311 struct tu_cs vp_cs;
2312 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
2313
2314 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2315 assert(vp_info->viewportCount == 1);
2316 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
2317 }
2318
2319 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2320 assert(vp_info->scissorCount == 1);
2321 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
2322 }
2323
2324 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
2325 }
2326
2327 static void
2328 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2329 struct tu_pipeline *pipeline)
2330 {
2331 const VkPipelineRasterizationStateCreateInfo *rast_info =
2332 builder->create_info->pRasterizationState;
2333
2334 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2335
2336 struct tu_cs rast_cs;
2337 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
2338
2339
2340 tu_cs_emit_regs(&rast_cs,
2341 A6XX_GRAS_CL_CNTL(
2342 .znear_clip_disable = rast_info->depthClampEnable,
2343 .zfar_clip_disable = rast_info->depthClampEnable,
2344 .unk5 = rast_info->depthClampEnable,
2345 .zero_gb_scale_z = 1,
2346 .vp_clip_code_ignore = 1));
2347 /* move to hw ctx init? */
2348 tu6_emit_gras_unknowns(&rast_cs);
2349 tu6_emit_point_size(&rast_cs);
2350
2351 const uint32_t gras_su_cntl =
2352 tu6_gras_su_cntl(rast_info, builder->samples);
2353
2354 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
2355 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
2356
2357 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
2358 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
2359 rast_info->depthBiasClamp,
2360 rast_info->depthBiasSlopeFactor);
2361 }
2362
2363 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
2364
2365 pipeline->rast.gras_su_cntl = gras_su_cntl;
2366 }
2367
2368 static void
2369 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2370 struct tu_pipeline *pipeline)
2371 {
2372 /* The spec says:
2373 *
2374 * pDepthStencilState is a pointer to an instance of the
2375 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2376 * the pipeline has rasterization disabled or if the subpass of the
2377 * render pass the pipeline is created against does not use a
2378 * depth/stencil attachment.
2379 *
2380 * Disable both depth and stencil tests if there is no ds attachment,
2381 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2382 * only the separate stencil attachment
2383 */
2384 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2385 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2386 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2387 ? builder->create_info->pDepthStencilState
2388 : &dummy_ds_info;
2389 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2390 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2391 ? ds_info : &dummy_ds_info;
2392
2393 struct tu_cs ds_cs;
2394 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2395
2396 /* move to hw ctx init? */
2397 tu6_emit_alpha_control_disable(&ds_cs);
2398
2399 tu6_emit_depth_control(&ds_cs, ds_info_depth,
2400 builder->create_info->pRasterizationState);
2401 tu6_emit_stencil_control(&ds_cs, ds_info);
2402
2403 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2404 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2405 ds_info->back.compareMask);
2406 }
2407 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2408 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2409 ds_info->back.writeMask);
2410 }
2411 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2412 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2413 ds_info->back.reference);
2414 }
2415
2416 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2417 }
2418
2419 static void
2420 tu_pipeline_builder_parse_multisample_and_color_blend(
2421 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2422 {
2423 /* The spec says:
2424 *
2425 * pMultisampleState is a pointer to an instance of the
2426 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2427 * has rasterization disabled.
2428 *
2429 * Also,
2430 *
2431 * pColorBlendState is a pointer to an instance of the
2432 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2433 * pipeline has rasterization disabled or if the subpass of the render
2434 * pass the pipeline is created against does not use any color
2435 * attachments.
2436 *
2437 * We leave the relevant registers stale when rasterization is disabled.
2438 */
2439 if (builder->rasterizer_discard)
2440 return;
2441
2442 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2443 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2444 builder->create_info->pMultisampleState;
2445 const VkPipelineColorBlendStateCreateInfo *blend_info =
2446 builder->use_color_attachments ? builder->create_info->pColorBlendState
2447 : &dummy_blend_info;
2448
2449 struct tu_cs blend_cs;
2450 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 9, &blend_cs);
2451
2452 uint32_t blend_enable_mask;
2453 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2454 builder->color_attachment_formats,
2455 &blend_enable_mask);
2456
2457 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2458 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2459
2460 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SAMPLE_LOCATIONS)) {
2461 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2462 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2463 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2464
2465 if (sample_locations && sample_locations->sampleLocationsEnable)
2466 samp_loc = &sample_locations->sampleLocationsInfo;
2467
2468 tu6_emit_sample_locations(&blend_cs, samp_loc);
2469 }
2470
2471 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
2472
2473 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2474 }
2475
2476 static void
2477 tu_pipeline_finish(struct tu_pipeline *pipeline,
2478 struct tu_device *dev,
2479 const VkAllocationCallbacks *alloc)
2480 {
2481 tu_cs_finish(&pipeline->cs);
2482
2483 if (pipeline->program.binary_bo.gem_handle)
2484 tu_bo_finish(dev, &pipeline->program.binary_bo);
2485 }
2486
2487 static VkResult
2488 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2489 struct tu_pipeline **pipeline)
2490 {
2491 VkResult result = tu_pipeline_create(builder->device, builder->layout,
2492 false, builder->alloc, pipeline);
2493 if (result != VK_SUCCESS)
2494 return result;
2495
2496 (*pipeline)->layout = builder->layout;
2497
2498 /* compile and upload shaders */
2499 result = tu_pipeline_builder_compile_shaders(builder);
2500 if (result == VK_SUCCESS)
2501 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2502 if (result != VK_SUCCESS) {
2503 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2504 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2505 *pipeline = VK_NULL_HANDLE;
2506
2507 return result;
2508 }
2509
2510 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2511 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2512 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2513 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2514 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2515 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2516 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2517 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2518 tu6_emit_load_state(*pipeline, false);
2519
2520 /* we should have reserved enough space upfront such that the CS never
2521 * grows
2522 */
2523 assert((*pipeline)->cs.bo_count == 1);
2524
2525 return VK_SUCCESS;
2526 }
2527
2528 static void
2529 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2530 {
2531 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2532 if (!builder->shaders[i])
2533 continue;
2534 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2535 }
2536 }
2537
2538 static void
2539 tu_pipeline_builder_init_graphics(
2540 struct tu_pipeline_builder *builder,
2541 struct tu_device *dev,
2542 struct tu_pipeline_cache *cache,
2543 const VkGraphicsPipelineCreateInfo *create_info,
2544 const VkAllocationCallbacks *alloc)
2545 {
2546 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2547
2548 *builder = (struct tu_pipeline_builder) {
2549 .device = dev,
2550 .cache = cache,
2551 .create_info = create_info,
2552 .alloc = alloc,
2553 .layout = layout,
2554 };
2555
2556 builder->rasterizer_discard =
2557 create_info->pRasterizationState->rasterizerDiscardEnable;
2558
2559 if (builder->rasterizer_discard) {
2560 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2561 } else {
2562 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2563
2564 const struct tu_render_pass *pass =
2565 tu_render_pass_from_handle(create_info->renderPass);
2566 const struct tu_subpass *subpass =
2567 &pass->subpasses[create_info->subpass];
2568
2569 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2570 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2571 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2572
2573 assert(subpass->color_count == 0 ||
2574 !create_info->pColorBlendState ||
2575 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2576 builder->color_attachment_count = subpass->color_count;
2577 for (uint32_t i = 0; i < subpass->color_count; i++) {
2578 const uint32_t a = subpass->color_attachments[i].attachment;
2579 if (a == VK_ATTACHMENT_UNUSED)
2580 continue;
2581
2582 builder->color_attachment_formats[i] = pass->attachments[a].format;
2583 builder->use_color_attachments = true;
2584 }
2585 }
2586 }
2587
2588 static VkResult
2589 tu_graphics_pipeline_create(VkDevice device,
2590 VkPipelineCache pipelineCache,
2591 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2592 const VkAllocationCallbacks *pAllocator,
2593 VkPipeline *pPipeline)
2594 {
2595 TU_FROM_HANDLE(tu_device, dev, device);
2596 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2597
2598 struct tu_pipeline_builder builder;
2599 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2600 pCreateInfo, pAllocator);
2601
2602 struct tu_pipeline *pipeline = NULL;
2603 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2604 tu_pipeline_builder_finish(&builder);
2605
2606 if (result == VK_SUCCESS)
2607 *pPipeline = tu_pipeline_to_handle(pipeline);
2608 else
2609 *pPipeline = VK_NULL_HANDLE;
2610
2611 return result;
2612 }
2613
2614 VkResult
2615 tu_CreateGraphicsPipelines(VkDevice device,
2616 VkPipelineCache pipelineCache,
2617 uint32_t count,
2618 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2619 const VkAllocationCallbacks *pAllocator,
2620 VkPipeline *pPipelines)
2621 {
2622 VkResult final_result = VK_SUCCESS;
2623
2624 for (uint32_t i = 0; i < count; i++) {
2625 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2626 &pCreateInfos[i], pAllocator,
2627 &pPipelines[i]);
2628
2629 if (result != VK_SUCCESS)
2630 final_result = result;
2631 }
2632
2633 return final_result;
2634 }
2635
2636 static void
2637 tu6_emit_compute_program(struct tu_cs *cs,
2638 struct tu_shader *shader,
2639 const struct tu_bo *binary_bo)
2640 {
2641 const struct ir3_shader_variant *v = &shader->variants[0];
2642
2643 tu6_emit_cs_config(cs, shader, v);
2644
2645 /* The compute program is the only one in the pipeline, so 0 offset. */
2646 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2647
2648 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2649 }
2650
2651 static VkResult
2652 tu_compute_upload_shader(VkDevice device,
2653 struct tu_pipeline *pipeline,
2654 struct tu_shader *shader)
2655 {
2656 TU_FROM_HANDLE(tu_device, dev, device);
2657 struct tu_bo *bo = &pipeline->program.binary_bo;
2658 struct ir3_shader_variant *v = &shader->variants[0];
2659
2660 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2661 VkResult result =
2662 tu_bo_init_new(dev, bo, shader_size);
2663 if (result != VK_SUCCESS)
2664 return result;
2665
2666 result = tu_bo_map(dev, bo);
2667 if (result != VK_SUCCESS)
2668 return result;
2669
2670 memcpy(bo->map, shader->binary, shader_size);
2671
2672 return VK_SUCCESS;
2673 }
2674
2675
2676 static VkResult
2677 tu_compute_pipeline_create(VkDevice device,
2678 VkPipelineCache _cache,
2679 const VkComputePipelineCreateInfo *pCreateInfo,
2680 const VkAllocationCallbacks *pAllocator,
2681 VkPipeline *pPipeline)
2682 {
2683 TU_FROM_HANDLE(tu_device, dev, device);
2684 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2685 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2686 VkResult result;
2687
2688 struct tu_pipeline *pipeline;
2689
2690 *pPipeline = VK_NULL_HANDLE;
2691
2692 result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline);
2693 if (result != VK_SUCCESS)
2694 return result;
2695
2696 pipeline->layout = layout;
2697
2698 struct tu_shader_compile_options options;
2699 tu_shader_compile_options_init(&options, NULL);
2700
2701 struct tu_shader *shader =
2702 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2703 if (!shader) {
2704 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2705 goto fail;
2706 }
2707
2708 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2709 if (result != VK_SUCCESS)
2710 goto fail;
2711
2712 struct ir3_shader_variant *v = &shader->variants[0];
2713
2714 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2715 shader, v);
2716
2717 result = tu_compute_upload_shader(device, pipeline, shader);
2718 if (result != VK_SUCCESS)
2719 goto fail;
2720
2721 for (int i = 0; i < 3; i++)
2722 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2723
2724 struct tu_cs prog_cs;
2725 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2726 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2727 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2728
2729 tu6_emit_load_state(pipeline, true);
2730
2731 *pPipeline = tu_pipeline_to_handle(pipeline);
2732 return VK_SUCCESS;
2733
2734 fail:
2735 if (shader)
2736 tu_shader_destroy(dev, shader, pAllocator);
2737
2738 tu_pipeline_finish(pipeline, dev, pAllocator);
2739 vk_free2(&dev->alloc, pAllocator, pipeline);
2740
2741 return result;
2742 }
2743
2744 VkResult
2745 tu_CreateComputePipelines(VkDevice device,
2746 VkPipelineCache pipelineCache,
2747 uint32_t count,
2748 const VkComputePipelineCreateInfo *pCreateInfos,
2749 const VkAllocationCallbacks *pAllocator,
2750 VkPipeline *pPipelines)
2751 {
2752 VkResult final_result = VK_SUCCESS;
2753
2754 for (uint32_t i = 0; i < count; i++) {
2755 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2756 &pCreateInfos[i],
2757 pAllocator, &pPipelines[i]);
2758 if (result != VK_SUCCESS)
2759 final_result = result;
2760 }
2761
2762 return final_result;
2763 }
2764
2765 void
2766 tu_DestroyPipeline(VkDevice _device,
2767 VkPipeline _pipeline,
2768 const VkAllocationCallbacks *pAllocator)
2769 {
2770 TU_FROM_HANDLE(tu_device, dev, _device);
2771 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2772
2773 if (!_pipeline)
2774 return;
2775
2776 tu_pipeline_finish(pipeline, dev, pAllocator);
2777 vk_free2(&dev->alloc, pAllocator, pipeline);
2778 }