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turnip: implement VK_EXT_vertex_attribute_divisor
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static void
46 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
47 enum a6xx_state_block sb, unsigned base, unsigned offset,
48 unsigned count)
49 {
50 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
51 * clear if emitting more packets will even help anything. Presumably the
52 * descriptor cache is relatively small, and these packets stop doing
53 * anything when there are too many descriptors.
54 */
55 tu_cs_emit_pkt7(cs, opcode, 3);
56 tu_cs_emit(cs,
57 CP_LOAD_STATE6_0_STATE_TYPE(st) |
58 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
59 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
60 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
61 tu_cs_emit_qw(cs, offset | (base << 28));
62 }
63
64 static unsigned
65 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
66 {
67 const unsigned load_state_size = 4;
68 unsigned size = 0;
69 for (unsigned i = 0; i < layout->num_sets; i++) {
70 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
71 for (unsigned j = 0; j < set_layout->binding_count; j++) {
72 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
73 unsigned count = 0;
74 /* Note: some users, like amber for example, pass in
75 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
76 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
77 */
78 VkShaderStageFlags stages = compute ?
79 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
80 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
81 unsigned stage_count = util_bitcount(stages);
82 switch (binding->type) {
83 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
84 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
85 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
86 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
87 /* IBO-backed resources only need one packet for all graphics stages */
88 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
89 count += 1;
90 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
91 count += 1;
92 break;
93 case VK_DESCRIPTOR_TYPE_SAMPLER:
94 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
95 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
96 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
97 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
98 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
99 /* Textures and UBO's needs a packet for each stage */
100 count = stage_count;
101 break;
102 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
103 /* Because of how we pack combined images and samplers, we
104 * currently can't use one packet for the whole array.
105 */
106 count = stage_count * binding->array_size * 2;
107 break;
108 default:
109 unreachable("bad descriptor type");
110 }
111 size += count * load_state_size;
112 }
113 }
114 return size;
115 }
116
117 static void
118 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
119 {
120 unsigned size = tu6_load_state_size(pipeline->layout, compute);
121 if (size == 0)
122 return;
123
124 struct tu_cs cs;
125 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
126
127 struct tu_pipeline_layout *layout = pipeline->layout;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 /* From 13.2.7. Descriptor Set Binding:
130 *
131 * A compatible descriptor set must be bound for all set numbers that
132 * any shaders in a pipeline access, at the time that a draw or
133 * dispatch command is recorded to execute using that pipeline.
134 * However, if none of the shaders in a pipeline statically use any
135 * bindings with a particular set number, then no descriptor set need
136 * be bound for that set number, even if the pipeline layout includes
137 * a non-trivial descriptor set layout for that set number.
138 *
139 * This means that descriptor sets unused by the pipeline may have a
140 * garbage or 0 BINDLESS_BASE register, which will cause context faults
141 * when prefetching descriptors from these sets. Skip prefetching for
142 * descriptors from them to avoid this. This is also an optimization,
143 * since these prefetches would be useless.
144 */
145 if (!(pipeline->active_desc_sets & (1u << i)))
146 continue;
147
148 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
149 for (unsigned j = 0; j < set_layout->binding_count; j++) {
150 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
151 unsigned base = i;
152 unsigned offset = binding->offset / 4;
153 /* Note: some users, like amber for example, pass in
154 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
155 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
156 */
157 VkShaderStageFlags stages = compute ?
158 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
159 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
160 unsigned count = binding->array_size;
161 if (count == 0 || stages == 0)
162 continue;
163 switch (binding->type) {
164 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
165 base = MAX_SETS;
166 offset = (layout->set[i].dynamic_offset_start +
167 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
168 /* fallthrough */
169 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
170 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
171 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
172 /* IBO-backed resources only need one packet for all graphics stages */
173 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
174 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
175 base, offset, count);
176 }
177 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
178 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
179 base, offset, count);
180 }
181 break;
182 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
183 /* nothing - input attachment doesn't use bindless */
184 break;
185 case VK_DESCRIPTOR_TYPE_SAMPLER:
186 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
187 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
188 tu_foreach_stage(stage, stages) {
189 emit_load_state(&cs, tu6_stage2opcode(stage),
190 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
191 ST6_SHADER : ST6_CONSTANTS,
192 tu6_stage2texsb(stage), base, offset, count);
193 }
194 break;
195 }
196 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
197 base = MAX_SETS;
198 offset = (layout->set[i].dynamic_offset_start +
199 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
200 /* fallthrough */
201 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
202 tu_foreach_stage(stage, stages) {
203 emit_load_state(&cs, tu6_stage2opcode(stage), ST6_UBO,
204 tu6_stage2shadersb(stage), base, offset, count);
205 }
206 break;
207 }
208 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
209 tu_foreach_stage(stage, stages) {
210 /* TODO: We could emit less CP_LOAD_STATE6 if we used
211 * struct-of-arrays instead of array-of-structs.
212 */
213 for (unsigned i = 0; i < count; i++) {
214 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
215 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
216 emit_load_state(&cs, tu6_stage2opcode(stage),
217 ST6_CONSTANTS, tu6_stage2texsb(stage),
218 base, tex_offset, 1);
219 emit_load_state(&cs, tu6_stage2opcode(stage),
220 ST6_SHADER, tu6_stage2texsb(stage),
221 base, sam_offset, 1);
222 }
223 }
224 break;
225 }
226 default:
227 unreachable("bad descriptor type");
228 }
229 }
230 }
231
232 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
233 }
234
235 struct tu_pipeline_builder
236 {
237 struct tu_device *device;
238 struct tu_pipeline_cache *cache;
239 struct tu_pipeline_layout *layout;
240 const VkAllocationCallbacks *alloc;
241 const VkGraphicsPipelineCreateInfo *create_info;
242
243 struct tu_shader *shaders[MESA_SHADER_STAGES];
244 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
245 struct ir3_shader_variant *binning_variant;
246 uint64_t shader_iova[MESA_SHADER_STAGES];
247 uint64_t binning_vs_iova;
248
249 bool rasterizer_discard;
250 /* these states are affectd by rasterizer_discard */
251 VkSampleCountFlagBits samples;
252 bool use_color_attachments;
253 bool use_dual_src_blend;
254 uint32_t color_attachment_count;
255 VkFormat color_attachment_formats[MAX_RTS];
256 VkFormat depth_attachment_format;
257 uint32_t render_components;
258 };
259
260 static bool
261 tu_logic_op_reads_dst(VkLogicOp op)
262 {
263 switch (op) {
264 case VK_LOGIC_OP_CLEAR:
265 case VK_LOGIC_OP_COPY:
266 case VK_LOGIC_OP_COPY_INVERTED:
267 case VK_LOGIC_OP_SET:
268 return false;
269 default:
270 return true;
271 }
272 }
273
274 static VkBlendFactor
275 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
276 {
277 /* treat dst alpha as 1.0 and avoid reading it */
278 switch (factor) {
279 case VK_BLEND_FACTOR_DST_ALPHA:
280 return VK_BLEND_FACTOR_ONE;
281 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
282 return VK_BLEND_FACTOR_ZERO;
283 default:
284 return factor;
285 }
286 }
287
288 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
289 {
290 switch (factor) {
291 case VK_BLEND_FACTOR_SRC1_COLOR:
292 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
293 case VK_BLEND_FACTOR_SRC1_ALPHA:
294 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
295 return true;
296 default:
297 return false;
298 }
299 }
300
301 static bool
302 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
303 {
304 if (!info)
305 return false;
306
307 for (unsigned i = 0; i < info->attachmentCount; i++) {
308 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
309 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
310 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
311 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
312 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
313 return true;
314 }
315
316 return false;
317 }
318
319 void
320 tu6_emit_xs_config(struct tu_cs *cs,
321 gl_shader_stage stage, /* xs->type, but xs may be NULL */
322 const struct ir3_shader_variant *xs,
323 uint64_t binary_iova)
324 {
325 static const struct xs_config {
326 uint16_t reg_sp_xs_ctrl;
327 uint16_t reg_sp_xs_config;
328 uint16_t reg_hlsq_xs_ctrl;
329 uint16_t reg_sp_vs_obj_start;
330 } xs_config[] = {
331 [MESA_SHADER_VERTEX] = {
332 REG_A6XX_SP_VS_CTRL_REG0,
333 REG_A6XX_SP_VS_CONFIG,
334 REG_A6XX_HLSQ_VS_CNTL,
335 REG_A6XX_SP_VS_OBJ_START_LO,
336 },
337 [MESA_SHADER_TESS_CTRL] = {
338 REG_A6XX_SP_HS_CTRL_REG0,
339 REG_A6XX_SP_HS_CONFIG,
340 REG_A6XX_HLSQ_HS_CNTL,
341 REG_A6XX_SP_HS_OBJ_START_LO,
342 },
343 [MESA_SHADER_TESS_EVAL] = {
344 REG_A6XX_SP_DS_CTRL_REG0,
345 REG_A6XX_SP_DS_CONFIG,
346 REG_A6XX_HLSQ_DS_CNTL,
347 REG_A6XX_SP_DS_OBJ_START_LO,
348 },
349 [MESA_SHADER_GEOMETRY] = {
350 REG_A6XX_SP_GS_CTRL_REG0,
351 REG_A6XX_SP_GS_CONFIG,
352 REG_A6XX_HLSQ_GS_CNTL,
353 REG_A6XX_SP_GS_OBJ_START_LO,
354 },
355 [MESA_SHADER_FRAGMENT] = {
356 REG_A6XX_SP_FS_CTRL_REG0,
357 REG_A6XX_SP_FS_CONFIG,
358 REG_A6XX_HLSQ_FS_CNTL,
359 REG_A6XX_SP_FS_OBJ_START_LO,
360 },
361 [MESA_SHADER_COMPUTE] = {
362 REG_A6XX_SP_CS_CTRL_REG0,
363 REG_A6XX_SP_CS_CONFIG,
364 REG_A6XX_HLSQ_CS_CNTL,
365 REG_A6XX_SP_CS_OBJ_START_LO,
366 },
367 };
368 const struct xs_config *cfg = &xs_config[stage];
369
370 if (!xs) {
371 /* shader stage disabled */
372 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
373 tu_cs_emit(cs, 0);
374
375 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
376 tu_cs_emit(cs, 0);
377 return;
378 }
379
380 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
381 enum a3xx_threadsize threadsize = FOUR_QUADS;
382
383 /* TODO:
384 * the "threadsize" field may have nothing to do with threadsize,
385 * use a value that matches the blob until it is figured out
386 */
387 if (xs->type == MESA_SHADER_GEOMETRY)
388 threadsize = TWO_QUADS;
389
390 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
391 tu_cs_emit(cs,
392 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
393 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
394 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs->info.max_half_reg + 1) |
395 COND(xs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
396 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
397 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
398 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
399 /* only fragment shader sets VARYING bit */
400 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
401 /* unknown bit, seems unnecessary */
402 COND(is_fs, 0x1000000));
403
404 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
405 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
406 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
407 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
408 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
409 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
410 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
411 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
412 tu_cs_emit(cs, xs->instrlen);
413
414 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
415 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(xs->constlen, 4)) |
416 A6XX_HLSQ_VS_CNTL_ENABLED);
417
418 /* emit program binary
419 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
420 */
421
422 assert((binary_iova & 0x7f) == 0);
423
424 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
425 tu_cs_emit_qw(cs, binary_iova);
426
427 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
428 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
429 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
430 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
431 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
432 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
433 tu_cs_emit_qw(cs, binary_iova);
434
435 /* emit immediates */
436
437 const struct ir3_const_state *const_state = ir3_const_state(xs);
438 uint32_t base = const_state->offsets.immediate;
439 int size = const_state->immediates_count;
440
441 /* truncate size to avoid writing constants that shader
442 * does not use:
443 */
444 size = MIN2(size + base, xs->constlen) - base;
445
446 if (size <= 0)
447 return;
448
449 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + size * 4);
450 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
451 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
452 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
453 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
454 CP_LOAD_STATE6_0_NUM_UNIT(size));
455 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
456 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
457
458 for (unsigned i = 0; i < size; i++) {
459 tu_cs_emit(cs, const_state->immediates[i].val[0]);
460 tu_cs_emit(cs, const_state->immediates[i].val[1]);
461 tu_cs_emit(cs, const_state->immediates[i].val[2]);
462 tu_cs_emit(cs, const_state->immediates[i].val[3]);
463 }
464 }
465
466 static void
467 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
468 const struct ir3_shader_variant *v,
469 uint32_t binary_iova)
470 {
471 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
472 tu_cs_emit(cs, 0xff);
473
474 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
475
476 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
477 tu_cs_emit(cs, 0x41);
478
479 uint32_t local_invocation_id =
480 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
481 uint32_t work_group_id =
482 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
483
484 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
485 tu_cs_emit(cs,
486 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
487 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
488 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
489 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
490 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
491 }
492
493 static void
494 tu6_emit_vs_system_values(struct tu_cs *cs,
495 const struct ir3_shader_variant *vs,
496 const struct ir3_shader_variant *hs,
497 const struct ir3_shader_variant *ds,
498 const struct ir3_shader_variant *gs,
499 bool primid_passthru)
500 {
501 const uint32_t vertexid_regid =
502 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
503 const uint32_t instanceid_regid =
504 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
505 const uint32_t tess_coord_x_regid = hs ?
506 ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD) :
507 regid(63, 0);
508 const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ?
509 tess_coord_x_regid + 1 :
510 regid(63, 0);
511 const uint32_t hs_patch_regid = hs ?
512 ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
513 regid(63, 0);
514 const uint32_t ds_patch_regid = hs ?
515 ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
516 regid(63, 0);
517 const uint32_t hs_invocation_regid = hs ?
518 ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) :
519 regid(63, 0);
520 const uint32_t primitiveid_regid = gs ?
521 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
522 regid(63, 0);
523 const uint32_t gsheader_regid = gs ?
524 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
525 regid(63, 0);
526
527 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
528 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
529 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
530 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
531 0xfc000000);
532 tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
533 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
534 tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
535 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
536 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
537 0xfc);
538 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
539 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
540 0xfc00); /* VFD_CONTROL_5 */
541 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
542 }
543
544 /* Add any missing varyings needed for stream-out. Otherwise varyings not
545 * used by fragment shader will be stripped out.
546 */
547 static void
548 tu6_link_streamout(struct ir3_shader_linkage *l,
549 const struct ir3_shader_variant *v)
550 {
551 const struct ir3_stream_output_info *info = &v->shader->stream_output;
552
553 /*
554 * First, any stream-out varyings not already in linkage map (ie. also
555 * consumed by frag shader) need to be added:
556 */
557 for (unsigned i = 0; i < info->num_outputs; i++) {
558 const struct ir3_stream_output *out = &info->output[i];
559 unsigned compmask =
560 (1 << (out->num_components + out->start_component)) - 1;
561 unsigned k = out->register_index;
562 unsigned idx, nextloc = 0;
563
564 /* psize/pos need to be the last entries in linkage map, and will
565 * get added link_stream_out, so skip over them:
566 */
567 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
568 v->outputs[k].slot == VARYING_SLOT_POS)
569 continue;
570
571 for (idx = 0; idx < l->cnt; idx++) {
572 if (l->var[idx].regid == v->outputs[k].regid)
573 break;
574 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
575 }
576
577 /* add if not already in linkage map: */
578 if (idx == l->cnt)
579 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
580
581 /* expand component-mask if needed, ie streaming out all components
582 * but frag shader doesn't consume all components:
583 */
584 if (compmask & ~l->var[idx].compmask) {
585 l->var[idx].compmask |= compmask;
586 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
587 util_last_bit(l->var[idx].compmask));
588 }
589 }
590 }
591
592 static void
593 tu6_setup_streamout(struct tu_cs *cs,
594 const struct ir3_shader_variant *v,
595 struct ir3_shader_linkage *l)
596 {
597 const struct ir3_stream_output_info *info = &v->shader->stream_output;
598 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2] = {};
599 uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {};
600 uint32_t prog_count = align(l->max_loc, 2) / 2;
601
602 /* TODO: streamout state should be in a non-GMEM draw state */
603
604 /* no streamout: */
605 if (info->num_outputs == 0) {
606 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
607 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
608 tu_cs_emit(cs, 0);
609 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
610 tu_cs_emit(cs, 0);
611 return;
612 }
613
614 /* is there something to do with info->stride[i]? */
615
616 for (unsigned i = 0; i < info->num_outputs; i++) {
617 const struct ir3_stream_output *out = &info->output[i];
618 unsigned k = out->register_index;
619 unsigned idx;
620
621 /* Skip it, if there's an unused reg in the middle of outputs. */
622 if (v->outputs[k].regid == INVALID_REG)
623 continue;
624
625 ncomp[out->output_buffer] += out->num_components;
626
627 /* linkage map sorted by order frag shader wants things, so
628 * a bit less ideal here..
629 */
630 for (idx = 0; idx < l->cnt; idx++)
631 if (l->var[idx].regid == v->outputs[k].regid)
632 break;
633
634 debug_assert(idx < l->cnt);
635
636 for (unsigned j = 0; j < out->num_components; j++) {
637 unsigned c = j + out->start_component;
638 unsigned loc = l->var[idx].loc + c;
639 unsigned off = j + out->dst_offset; /* in dwords */
640
641 if (loc & 1) {
642 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
643 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
644 A6XX_VPC_SO_PROG_B_OFF(off * 4);
645 } else {
646 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
647 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
648 A6XX_VPC_SO_PROG_A_OFF(off * 4);
649 }
650 }
651 }
652
653 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count);
654 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
655 tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE |
656 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
657 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
658 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
659 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
660 for (uint32_t i = 0; i < 4; i++) {
661 tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
662 tu_cs_emit(cs, ncomp[i]);
663 }
664 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
665 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
666 tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
667 for (uint32_t i = 0; i < prog_count; i++) {
668 tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
669 tu_cs_emit(cs, prog[i]);
670 }
671 }
672
673 static void
674 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
675 enum a6xx_state_block block, uint32_t offset,
676 uint32_t size, uint32_t *dwords) {
677 assert(size % 4 == 0);
678
679 tu_cs_emit_pkt7(cs, opcode, 3 + size);
680 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
681 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
682 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
683 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
684 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
685
686 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
687 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
688 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
689
690 tu_cs_emit_array(cs, dwords, size);
691 }
692
693 static void
694 tu6_emit_link_map(struct tu_cs *cs,
695 const struct ir3_shader_variant *producer,
696 const struct ir3_shader_variant *consumer,
697 enum a6xx_state_block sb)
698 {
699 const struct ir3_const_state *const_state = ir3_const_state(consumer);
700 uint32_t base = const_state->offsets.primitive_map;
701 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
702 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
703 int size = DIV_ROUND_UP(num_loc, 4);
704
705 size = (MIN2(size + base, consumer->constlen) - base) * 4;
706 if (size <= 0)
707 return;
708
709 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, sb, 0, size,
710 patch_locs);
711 }
712
713 static uint16_t
714 gl_primitive_to_tess(uint16_t primitive) {
715 switch (primitive) {
716 case GL_POINTS:
717 return TESS_POINTS;
718 case GL_LINE_STRIP:
719 return TESS_LINES;
720 case GL_TRIANGLE_STRIP:
721 return TESS_CW_TRIS;
722 default:
723 unreachable("");
724 }
725 }
726
727 void
728 tu6_emit_vpc(struct tu_cs *cs,
729 const struct ir3_shader_variant *vs,
730 const struct ir3_shader_variant *hs,
731 const struct ir3_shader_variant *ds,
732 const struct ir3_shader_variant *gs,
733 const struct ir3_shader_variant *fs)
734 {
735 const struct ir3_shader_variant *last_shader;
736 if (gs) {
737 last_shader = gs;
738 } else if (hs) {
739 last_shader = ds;
740 } else {
741 last_shader = vs;
742 }
743 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
744 if (fs)
745 ir3_link_shaders(&linkage, last_shader, fs, true);
746
747 if (last_shader->shader->stream_output.num_outputs)
748 tu6_link_streamout(&linkage, last_shader);
749
750 /* We do this after linking shaders in order to know whether PrimID
751 * passthrough needs to be enabled.
752 */
753 bool primid_passthru = linkage.primid_loc != 0xff;
754 tu6_emit_vs_system_values(cs, vs, hs, ds, gs, primid_passthru);
755
756 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
757 tu_cs_emit(cs, ~linkage.varmask[0]);
758 tu_cs_emit(cs, ~linkage.varmask[1]);
759 tu_cs_emit(cs, ~linkage.varmask[2]);
760 tu_cs_emit(cs, ~linkage.varmask[3]);
761
762 /* a6xx finds position/pointsize at the end */
763 const uint32_t position_regid =
764 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
765 const uint32_t pointsize_regid =
766 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
767 const uint32_t layer_regid = gs ?
768 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
769
770 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
771 if (layer_regid != regid(63, 0)) {
772 layer_loc = linkage.max_loc;
773 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
774 }
775 if (position_regid != regid(63, 0)) {
776 position_loc = linkage.max_loc;
777 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
778 }
779 if (pointsize_regid != regid(63, 0)) {
780 pointsize_loc = linkage.max_loc;
781 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
782 }
783
784 tu6_setup_streamout(cs, last_shader, &linkage);
785
786 /* map outputs of the last shader to VPC */
787 assert(linkage.cnt <= 32);
788 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
789 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
790 uint32_t sp_out[16];
791 uint32_t sp_vpc_dst[8];
792 for (uint32_t i = 0; i < linkage.cnt; i++) {
793 ((uint16_t *) sp_out)[i] =
794 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
795 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
796 ((uint8_t *) sp_vpc_dst)[i] =
797 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
798 }
799
800 if (gs)
801 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
802 else if (hs)
803 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_OUT_REG(0), sp_out_count);
804 else
805 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
806 tu_cs_emit_array(cs, sp_out, sp_out_count);
807
808 if (gs)
809 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
810 else if (hs)
811 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_VPC_DST_REG(0), sp_vpc_dst_count);
812 else
813 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
814 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
815
816 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
817 tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
818
819 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
820 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
821 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
822 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
823 A6XX_VPC_CNTL_0_UNKLOC(0xff));
824
825 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
826 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
827 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
828 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
829
830 if (hs) {
831 shader_info *hs_info = &hs->shader->nir->info;
832 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
833 tu_cs_emit(cs, hs_info->tess.tcs_vertices_out);
834
835 /* Total attribute slots in HS incoming patch. */
836 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9801, 1);
837 tu_cs_emit(cs,
838 hs_info->tess.tcs_vertices_out * vs->output_size / 4);
839
840 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
841 tu_cs_emit(cs, vs->output_size);
842 /* In SPIR-V generated from GLSL, the tessellation primitive params are
843 * are specified in the tess eval shader, but in SPIR-V generated from
844 * HLSL, they are specified in the tess control shader. */
845 shader_info *tess_info =
846 ds->shader->nir->info.tess.spacing == TESS_SPACING_UNSPECIFIED ?
847 &hs->shader->nir->info : &ds->shader->nir->info;
848 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_CNTL, 1);
849 uint32_t output;
850 if (tess_info->tess.point_mode)
851 output = TESS_POINTS;
852 else if (tess_info->tess.primitive_mode == GL_ISOLINES)
853 output = TESS_LINES;
854 else if (tess_info->tess.ccw)
855 output = TESS_CCW_TRIS;
856 else
857 output = TESS_CW_TRIS;
858
859 enum a6xx_tess_spacing spacing;
860 switch (tess_info->tess.spacing) {
861 case TESS_SPACING_EQUAL:
862 spacing = TESS_EQUAL;
863 break;
864 case TESS_SPACING_FRACTIONAL_ODD:
865 spacing = TESS_FRACTIONAL_ODD;
866 break;
867 case TESS_SPACING_FRACTIONAL_EVEN:
868 spacing = TESS_FRACTIONAL_EVEN;
869 break;
870 case TESS_SPACING_UNSPECIFIED:
871 default:
872 unreachable("invalid tess spacing");
873 }
874 tu_cs_emit(cs, A6XX_PC_TESS_CNTL_SPACING(spacing) |
875 A6XX_PC_TESS_CNTL_OUTPUT(output));
876
877 /* xxx: Misc tess unknowns: */
878 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9103, 1);
879 tu_cs_emit(cs, 0x00ffff00);
880
881 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9106, 1);
882 tu_cs_emit(cs, 0x0000ffff);
883
884 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809D, 1);
885 tu_cs_emit(cs, 0x0);
886
887 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8002, 1);
888 tu_cs_emit(cs, 0x0);
889
890 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
891 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
892 A6XX_VPC_PACK_PSIZELOC(255) |
893 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
894
895 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_3, 1);
896 tu_cs_emit(cs, A6XX_VPC_PACK_3_POSITIONLOC(position_loc) |
897 A6XX_VPC_PACK_3_PSIZELOC(pointsize_loc) |
898 A6XX_VPC_PACK_3_STRIDE_IN_VPC(linkage.max_loc));
899
900 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
901 tu_cs_emit(cs, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(linkage.cnt));
902
903 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1);
904 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(linkage.max_loc) |
905 CONDREG(pointsize_regid, 0x100));
906
907 tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
908 tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER);
909 }
910
911
912 if (gs) {
913 uint32_t vertices_out, invocations, output, vec4_size;
914 /* this detects the tu_clear_blit path, which doesn't set ->nir */
915 if (gs->shader->nir) {
916 if (hs) {
917 tu6_emit_link_map(cs, ds, gs, SB6_GS_SHADER);
918 } else {
919 tu6_emit_link_map(cs, vs, gs, SB6_GS_SHADER);
920 }
921 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
922 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
923 invocations = gs->shader->nir->info.gs.invocations - 1;
924 /* Size of per-primitive alloction in ldlw memory in vec4s. */
925 vec4_size = gs->shader->nir->info.gs.vertices_in *
926 DIV_ROUND_UP(vs->output_size, 4);
927 } else {
928 vertices_out = 3;
929 output = TESS_CW_TRIS;
930 invocations = 0;
931 vec4_size = 0;
932 }
933
934 uint32_t primitive_regid =
935 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
936 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
937 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
938 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
939 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
940
941 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
942 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
943
944 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
945 tu_cs_emit(cs, CONDREG(layer_regid,
946 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
947
948 uint32_t flags_regid = ir3_find_output_regid(gs,
949 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
950
951 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
952 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
953 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
954
955 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
956 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
957 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
958 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
959 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
960
961 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
962 tu_cs_emit(cs,
963 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
964 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
965 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
966
967 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
968 tu_cs_emit(cs, 0);
969
970 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
971 tu_cs_emit(cs, 0);
972
973 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
974 tu_cs_emit(cs, 0xff);
975
976 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
977 tu_cs_emit(cs, 0xffff00);
978
979 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
980 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
981
982 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
983 tu_cs_emit(cs, 0);
984
985 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
986 tu_cs_emit(cs, vs->output_size);
987 }
988
989 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
990 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
991
992 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
993 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
994 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
995 }
996
997 static int
998 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
999 uint32_t index,
1000 uint8_t *interp_mode,
1001 uint8_t *ps_repl_mode)
1002 {
1003 enum
1004 {
1005 INTERP_SMOOTH = 0,
1006 INTERP_FLAT = 1,
1007 INTERP_ZERO = 2,
1008 INTERP_ONE = 3,
1009 };
1010 enum
1011 {
1012 PS_REPL_NONE = 0,
1013 PS_REPL_S = 1,
1014 PS_REPL_T = 2,
1015 PS_REPL_ONE_MINUS_T = 3,
1016 };
1017
1018 const uint32_t compmask = fs->inputs[index].compmask;
1019
1020 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1021 * fourth component occupy three consecutive varying slots
1022 */
1023 int shift = 0;
1024 *interp_mode = 0;
1025 *ps_repl_mode = 0;
1026 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1027 if (compmask & 0x1) {
1028 *ps_repl_mode |= PS_REPL_S << shift;
1029 shift += 2;
1030 }
1031 if (compmask & 0x2) {
1032 *ps_repl_mode |= PS_REPL_T << shift;
1033 shift += 2;
1034 }
1035 if (compmask & 0x4) {
1036 *interp_mode |= INTERP_ZERO << shift;
1037 shift += 2;
1038 }
1039 if (compmask & 0x8) {
1040 *interp_mode |= INTERP_ONE << 6;
1041 shift += 2;
1042 }
1043 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1044 fs->inputs[index].rasterflat) {
1045 for (int i = 0; i < 4; i++) {
1046 if (compmask & (1 << i)) {
1047 *interp_mode |= INTERP_FLAT << shift;
1048 shift += 2;
1049 }
1050 }
1051 }
1052
1053 return shift;
1054 }
1055
1056 static void
1057 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1058 const struct ir3_shader_variant *fs)
1059 {
1060 uint32_t interp_modes[8] = { 0 };
1061 uint32_t ps_repl_modes[8] = { 0 };
1062
1063 if (fs) {
1064 for (int i = -1;
1065 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1066
1067 /* get the mode for input i */
1068 uint8_t interp_mode;
1069 uint8_t ps_repl_mode;
1070 const int bits =
1071 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1072
1073 /* OR the mode into the array */
1074 const uint32_t inloc = fs->inputs[i].inloc * 2;
1075 uint32_t n = inloc / 32;
1076 uint32_t shift = inloc % 32;
1077 interp_modes[n] |= interp_mode << shift;
1078 ps_repl_modes[n] |= ps_repl_mode << shift;
1079 if (shift + bits > 32) {
1080 n++;
1081 shift = 32 - shift;
1082
1083 interp_modes[n] |= interp_mode >> shift;
1084 ps_repl_modes[n] |= ps_repl_mode >> shift;
1085 }
1086 }
1087 }
1088
1089 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1090 tu_cs_emit_array(cs, interp_modes, 8);
1091
1092 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1093 tu_cs_emit_array(cs, ps_repl_modes, 8);
1094 }
1095
1096 void
1097 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1098 {
1099 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1100 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
1101 uint32_t smask_in_regid;
1102
1103 bool sample_shading = fs->per_samp | fs->key.sample_shading;
1104 bool enable_varyings = fs->total_in > 0;
1105
1106 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1107 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1108 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1109 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1110 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1111 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1112 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1113 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1114 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1115
1116 if (fs->num_sampler_prefetch > 0) {
1117 assert(VALIDREG(ij_pix_regid));
1118 /* also, it seems like ij_pix is *required* to be r0.x */
1119 assert(ij_pix_regid == regid(0, 0));
1120 }
1121
1122 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1123 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1124 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1125 0x7000); // XXX);
1126 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1127 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1128 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1129 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1130 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1131 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1132 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1133 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1134 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1135 }
1136
1137 if (fs->num_sampler_prefetch > 0) {
1138 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1139 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1140 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1141 tu_cs_emit(cs,
1142 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1143 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1144 }
1145 }
1146
1147 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1148 tu_cs_emit(cs, 0x7);
1149 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1150 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1151 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1152 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1153 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1154 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1155 0xfc00fc00);
1156 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1157 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1158 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1159 0x0000fc00);
1160 tu_cs_emit(cs, 0xfc);
1161
1162 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1163 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1164
1165 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1166 tu_cs_emit(cs,
1167 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1168 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1169 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1170 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1171 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1172 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
1173 A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
1174 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1175
1176 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1177 tu_cs_emit(cs,
1178 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1179 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1180 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1181 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1182 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1183 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1184 COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
1185 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
1186 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1187 tu_cs_emit(cs,
1188 /* these two bits (UNK4/UNK5) relate to fragcoord
1189 * without them, fragcoord is the same for all samples
1190 */
1191 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) |
1192 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) |
1193 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1194 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1195 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1196 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1197
1198 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1199 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1200
1201 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1202 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1203
1204 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1205 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1206 }
1207
1208 static void
1209 tu6_emit_fs_outputs(struct tu_cs *cs,
1210 const struct ir3_shader_variant *fs,
1211 uint32_t mrt_count, bool dual_src_blend,
1212 uint32_t render_components)
1213 {
1214 uint32_t smask_regid, posz_regid;
1215
1216 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1217 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1218
1219 uint32_t fragdata_regid[8];
1220 if (fs->color0_mrt) {
1221 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1222 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1223 fragdata_regid[i] = fragdata_regid[0];
1224 } else {
1225 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1226 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1227 }
1228
1229 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1230 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1231 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1232 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
1233 0xfc000000);
1234 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1235
1236 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1237 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1238 // TODO we could have a mix of half and full precision outputs,
1239 // we really need to figure out half-precision from IR3_REG_HALF
1240 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1241 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1242 }
1243
1244 tu_cs_emit_regs(cs,
1245 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1246
1247 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1248 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1249 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1250 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1251 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1252
1253 tu_cs_emit_regs(cs,
1254 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1255
1256 enum a6xx_ztest_mode zmode;
1257
1258 if (fs->no_earlyz || fs->has_kill || fs->writes_pos) {
1259 zmode = A6XX_LATE_Z;
1260 } else {
1261 zmode = A6XX_EARLY_Z;
1262 }
1263
1264 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1265 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1266
1267 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1268 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1269 }
1270
1271 static void
1272 tu6_emit_geom_tess_consts(struct tu_cs *cs,
1273 const struct ir3_shader_variant *vs,
1274 const struct ir3_shader_variant *hs,
1275 const struct ir3_shader_variant *ds,
1276 const struct ir3_shader_variant *gs,
1277 uint32_t cps_per_patch)
1278 {
1279 uint32_t num_vertices =
1280 hs ? cps_per_patch : gs->shader->nir->info.gs.vertices_in;
1281
1282 uint32_t vs_params[4] = {
1283 vs->output_size * num_vertices * 4, /* vs primitive stride */
1284 vs->output_size * 4, /* vs vertex stride */
1285 0,
1286 0,
1287 };
1288 uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param;
1289 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1290 ARRAY_SIZE(vs_params), vs_params);
1291
1292 if (hs) {
1293 assert(ds->type != MESA_SHADER_NONE);
1294 uint32_t hs_params[4] = {
1295 vs->output_size * num_vertices * 4, /* hs primitive stride */
1296 vs->output_size * 4, /* hs vertex stride */
1297 hs->output_size,
1298 cps_per_patch,
1299 };
1300
1301 uint32_t hs_base = hs->const_state->offsets.primitive_param;
1302 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, hs_base, SB6_HS_SHADER, 0,
1303 ARRAY_SIZE(hs_params), hs_params);
1304 if (gs)
1305 num_vertices = gs->shader->nir->info.gs.vertices_in;
1306
1307 uint32_t ds_params[4] = {
1308 ds->output_size * num_vertices * 4, /* ds primitive stride */
1309 ds->output_size * 4, /* ds vertex stride */
1310 hs->output_size, /* hs vertex stride (dwords) */
1311 hs->shader->nir->info.tess.tcs_vertices_out
1312 };
1313
1314 uint32_t ds_base = ds->const_state->offsets.primitive_param;
1315 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, ds_base, SB6_DS_SHADER, 0,
1316 ARRAY_SIZE(ds_params), ds_params);
1317 }
1318
1319 if (gs) {
1320 const struct ir3_shader_variant *prev = ds ? ds : vs;
1321 uint32_t gs_params[4] = {
1322 prev->output_size * num_vertices * 4, /* gs primitive stride */
1323 prev->output_size * 4, /* gs vertex stride */
1324 0,
1325 0,
1326 };
1327 uint32_t gs_base = gs->const_state->offsets.primitive_param;
1328 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1329 ARRAY_SIZE(gs_params), gs_params);
1330 }
1331 }
1332
1333 static void
1334 tu6_emit_program(struct tu_cs *cs,
1335 struct tu_pipeline_builder *builder,
1336 bool binning_pass)
1337 {
1338 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
1339 const struct ir3_shader_variant *bs = builder->binning_variant;
1340 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
1341 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
1342 const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
1343 const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
1344 gl_shader_stage stage = MESA_SHADER_VERTEX;
1345
1346 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1347
1348 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1349 tu_cs_emit(cs, 0xff); /* XXX */
1350
1351 /* Don't use the binning pass variant when GS is present because we don't
1352 * support compiling correct binning pass variants with GS.
1353 */
1354 if (binning_pass && !gs) {
1355 vs = bs;
1356 tu6_emit_xs_config(cs, stage, bs, builder->binning_vs_iova);
1357 stage++;
1358 }
1359
1360 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1361 const struct ir3_shader_variant *xs = builder->variants[stage];
1362
1363 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1364 fs = xs = NULL;
1365
1366 tu6_emit_xs_config(cs, stage, xs, builder->shader_iova[stage]);
1367 }
1368
1369 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1370 tu_cs_emit(cs, 0);
1371
1372 tu6_emit_vpc(cs, vs, hs, ds, gs, fs);
1373 tu6_emit_vpc_varying_modes(cs, fs);
1374
1375 if (fs) {
1376 tu6_emit_fs_inputs(cs, fs);
1377 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1378 builder->use_dual_src_blend,
1379 builder->render_components);
1380 } else {
1381 /* TODO: check if these can be skipped if fs is disabled */
1382 struct ir3_shader_variant dummy_variant = {};
1383 tu6_emit_fs_inputs(cs, &dummy_variant);
1384 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1385 builder->use_dual_src_blend,
1386 builder->render_components);
1387 }
1388
1389 if (gs || hs) {
1390 uint32_t cps_per_patch = builder->create_info->pTessellationState ?
1391 builder->create_info->pTessellationState->patchControlPoints : 0;
1392 tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch);
1393 }
1394 }
1395
1396 static void
1397 tu6_emit_vertex_input(struct tu_cs *cs,
1398 const struct ir3_shader_variant *vs,
1399 const VkPipelineVertexInputStateCreateInfo *info,
1400 uint32_t *bindings_used)
1401 {
1402 uint32_t vfd_decode_idx = 0;
1403 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1404 uint32_t step_rate[MAX_VBS];
1405
1406 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1407 const VkVertexInputBindingDescription *binding =
1408 &info->pVertexBindingDescriptions[i];
1409
1410 tu_cs_emit_regs(cs,
1411 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1412
1413 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1414 binding_instanced |= 1 << binding->binding;
1415
1416 *bindings_used |= 1 << binding->binding;
1417 step_rate[binding->binding] = 1;
1418 }
1419
1420 const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_state =
1421 vk_find_struct_const(info->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1422 if (div_state) {
1423 for (uint32_t i = 0; i < div_state->vertexBindingDivisorCount; i++) {
1424 const VkVertexInputBindingDivisorDescriptionEXT *desc =
1425 &div_state->pVertexBindingDivisors[i];
1426 step_rate[desc->binding] = desc->divisor;
1427 }
1428 }
1429
1430 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1431
1432 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1433 const VkVertexInputAttributeDescription *attr =
1434 &info->pVertexAttributeDescriptions[i];
1435 uint32_t input_idx;
1436
1437 assert(*bindings_used & BIT(attr->binding));
1438
1439 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1440 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1441 break;
1442 }
1443
1444 /* attribute not used, skip it */
1445 if (input_idx == vs->inputs_count)
1446 continue;
1447
1448 const struct tu_native_format format = tu6_format_vtx(attr->format);
1449 tu_cs_emit_regs(cs,
1450 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1451 .idx = attr->binding,
1452 .offset = attr->offset,
1453 .instanced = binding_instanced & (1 << attr->binding),
1454 .format = format.fmt,
1455 .swap = format.swap,
1456 .unk30 = 1,
1457 ._float = !vk_format_is_int(attr->format)),
1458 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, step_rate[attr->binding]));
1459
1460 tu_cs_emit_regs(cs,
1461 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1462 .writemask = vs->inputs[input_idx].compmask,
1463 .regid = vs->inputs[input_idx].regid));
1464
1465 vfd_decode_idx++;
1466 }
1467
1468 tu_cs_emit_regs(cs,
1469 A6XX_VFD_CONTROL_0(
1470 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1471 .decode_cnt = vfd_decode_idx));
1472 }
1473
1474 static uint32_t
1475 tu6_guardband_adj(uint32_t v)
1476 {
1477 if (v > 256)
1478 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1479 else
1480 return 511;
1481 }
1482
1483 void
1484 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1485 {
1486 float offsets[3];
1487 float scales[3];
1488 scales[0] = viewport->width / 2.0f;
1489 scales[1] = viewport->height / 2.0f;
1490 scales[2] = viewport->maxDepth - viewport->minDepth;
1491 offsets[0] = viewport->x + scales[0];
1492 offsets[1] = viewport->y + scales[1];
1493 offsets[2] = viewport->minDepth;
1494
1495 VkOffset2D min;
1496 VkOffset2D max;
1497 min.x = (int32_t) viewport->x;
1498 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1499 if (viewport->height >= 0.0f) {
1500 min.y = (int32_t) viewport->y;
1501 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1502 } else {
1503 min.y = (int32_t)(viewport->y + viewport->height);
1504 max.y = (int32_t) ceilf(viewport->y);
1505 }
1506 /* the spec allows viewport->height to be 0.0f */
1507 if (min.y == max.y)
1508 max.y++;
1509 assert(min.x >= 0 && min.x < max.x);
1510 assert(min.y >= 0 && min.y < max.y);
1511
1512 VkExtent2D guardband_adj;
1513 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1514 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1515
1516 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1517 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1518 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1519 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1520 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1521 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1522 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1523
1524 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1525 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1526 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1527 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1528 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1529
1530 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1531 tu_cs_emit(cs,
1532 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1533 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1534
1535 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1536 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1537
1538 tu_cs_emit_regs(cs,
1539 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1540 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1541
1542 tu_cs_emit_regs(cs,
1543 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1544 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1545 }
1546
1547 void
1548 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1549 {
1550 const VkOffset2D min = scissor->offset;
1551 const VkOffset2D max = {
1552 scissor->offset.x + scissor->extent.width,
1553 scissor->offset.y + scissor->extent.height,
1554 };
1555
1556 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1557 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1558 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1559 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1560 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1561 }
1562
1563 void
1564 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1565 {
1566 if (!samp_loc) {
1567 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1568 tu_cs_emit(cs, 0);
1569
1570 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1571 tu_cs_emit(cs, 0);
1572
1573 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1574 tu_cs_emit(cs, 0);
1575 return;
1576 }
1577
1578 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1579 assert(samp_loc->sampleLocationGridSize.width == 1);
1580 assert(samp_loc->sampleLocationGridSize.height == 1);
1581
1582 uint32_t sample_config =
1583 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1584 uint32_t sample_locations = 0;
1585 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1586 sample_locations |=
1587 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1588 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1589 }
1590
1591 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1592 tu_cs_emit(cs, sample_config);
1593 tu_cs_emit(cs, sample_locations);
1594
1595 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1596 tu_cs_emit(cs, sample_config);
1597 tu_cs_emit(cs, sample_locations);
1598
1599 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1600 tu_cs_emit(cs, sample_config);
1601 tu_cs_emit(cs, sample_locations);
1602 }
1603
1604 static uint32_t
1605 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1606 VkSampleCountFlagBits samples)
1607 {
1608 uint32_t gras_su_cntl = 0;
1609
1610 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1611 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1612 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1613 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1614
1615 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1616 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1617
1618 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1619
1620 if (rast_info->depthBiasEnable)
1621 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1622
1623 if (samples > VK_SAMPLE_COUNT_1_BIT)
1624 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1625
1626 return gras_su_cntl;
1627 }
1628
1629 void
1630 tu6_emit_depth_bias(struct tu_cs *cs,
1631 float constant_factor,
1632 float clamp,
1633 float slope_factor)
1634 {
1635 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1636 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1637 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1638 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1639 }
1640
1641 static void
1642 tu6_emit_depth_control(struct tu_cs *cs,
1643 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1644 const VkPipelineRasterizationStateCreateInfo *rast_info)
1645 {
1646 uint32_t rb_depth_cntl = 0;
1647 if (ds_info->depthTestEnable) {
1648 rb_depth_cntl |=
1649 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1650 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1651 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
1652
1653 if (rast_info->depthClampEnable)
1654 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1655
1656 if (ds_info->depthWriteEnable)
1657 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1658 }
1659
1660 if (ds_info->depthBoundsTestEnable)
1661 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1662
1663 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1664 tu_cs_emit(cs, rb_depth_cntl);
1665 }
1666
1667 static void
1668 tu6_emit_stencil_control(struct tu_cs *cs,
1669 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1670 {
1671 uint32_t rb_stencil_control = 0;
1672 if (ds_info->stencilTestEnable) {
1673 const VkStencilOpState *front = &ds_info->front;
1674 const VkStencilOpState *back = &ds_info->back;
1675 rb_stencil_control |=
1676 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1677 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1678 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1679 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1680 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1681 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1682 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1683 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1684 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1685 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1686 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1687 }
1688
1689 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1690 tu_cs_emit(cs, rb_stencil_control);
1691 }
1692
1693 static uint32_t
1694 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1695 bool has_alpha)
1696 {
1697 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1698 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1699 has_alpha ? att->srcColorBlendFactor
1700 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1701 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1702 has_alpha ? att->dstColorBlendFactor
1703 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1704 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1705 const enum adreno_rb_blend_factor src_alpha_factor =
1706 tu6_blend_factor(att->srcAlphaBlendFactor);
1707 const enum adreno_rb_blend_factor dst_alpha_factor =
1708 tu6_blend_factor(att->dstAlphaBlendFactor);
1709
1710 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1711 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1712 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1713 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1714 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1715 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1716 }
1717
1718 static uint32_t
1719 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1720 uint32_t rb_mrt_control_rop,
1721 bool is_int,
1722 bool has_alpha)
1723 {
1724 uint32_t rb_mrt_control =
1725 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1726
1727 /* ignore blending and logic op for integer attachments */
1728 if (is_int) {
1729 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1730 return rb_mrt_control;
1731 }
1732
1733 rb_mrt_control |= rb_mrt_control_rop;
1734
1735 if (att->blendEnable) {
1736 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1737
1738 if (has_alpha)
1739 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1740 }
1741
1742 return rb_mrt_control;
1743 }
1744
1745 static void
1746 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1747 const VkPipelineColorBlendStateCreateInfo *blend_info,
1748 const VkFormat attachment_formats[MAX_RTS],
1749 uint32_t *blend_enable_mask)
1750 {
1751 *blend_enable_mask = 0;
1752
1753 bool rop_reads_dst = false;
1754 uint32_t rb_mrt_control_rop = 0;
1755 if (blend_info->logicOpEnable) {
1756 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1757 rb_mrt_control_rop =
1758 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1759 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1760 }
1761
1762 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1763 const VkPipelineColorBlendAttachmentState *att =
1764 &blend_info->pAttachments[i];
1765 const VkFormat format = attachment_formats[i];
1766
1767 uint32_t rb_mrt_control = 0;
1768 uint32_t rb_mrt_blend_control = 0;
1769 if (format != VK_FORMAT_UNDEFINED) {
1770 const bool is_int = vk_format_is_int(format);
1771 const bool has_alpha = vk_format_has_alpha(format);
1772
1773 rb_mrt_control =
1774 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1775 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1776
1777 if (att->blendEnable || rop_reads_dst)
1778 *blend_enable_mask |= 1 << i;
1779 }
1780
1781 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1782 tu_cs_emit(cs, rb_mrt_control);
1783 tu_cs_emit(cs, rb_mrt_blend_control);
1784 }
1785 }
1786
1787 static void
1788 tu6_emit_blend_control(struct tu_cs *cs,
1789 uint32_t blend_enable_mask,
1790 bool dual_src_blend,
1791 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1792 {
1793 const uint32_t sample_mask =
1794 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1795 : ((1 << msaa_info->rasterizationSamples) - 1);
1796
1797 tu_cs_emit_regs(cs,
1798 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1799 .dual_color_in_enable = dual_src_blend,
1800 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1801 .unk8 = true));
1802
1803 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1804 tu_cs_emit_regs(cs,
1805 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1806 .independent_blend = true,
1807 .sample_mask = sample_mask,
1808 .dual_color_in_enable = dual_src_blend,
1809 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1810 .alpha_to_one = msaa_info->alphaToOneEnable));
1811 }
1812
1813 static VkResult
1814 tu_pipeline_allocate_cs(struct tu_device *dev,
1815 struct tu_pipeline *pipeline,
1816 struct tu_pipeline_builder *builder,
1817 struct ir3_shader_variant *compute)
1818 {
1819 uint32_t size = 2048 + tu6_load_state_size(pipeline->layout, compute);
1820
1821 /* graphics case: */
1822 if (builder) {
1823 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1824 if (builder->variants[i])
1825 size += builder->variants[i]->info.sizedwords;
1826 }
1827
1828 size += builder->binning_variant->info.sizedwords;
1829 } else {
1830 size += compute->info.sizedwords;
1831 }
1832
1833 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, size);
1834
1835 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1836 * that LOAD_STATE can potentially take up a large amount of space so we
1837 * calculate its size explicitly.
1838 */
1839 return tu_cs_reserve_space(&pipeline->cs, size);
1840 }
1841
1842 static void
1843 tu_pipeline_shader_key_init(struct ir3_shader_key *key,
1844 const VkGraphicsPipelineCreateInfo *pipeline_info)
1845 {
1846 for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
1847 if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
1848 key->has_gs = true;
1849 break;
1850 }
1851 }
1852
1853 if (pipeline_info->pRasterizationState->rasterizerDiscardEnable)
1854 return;
1855
1856 const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
1857 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
1858 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1859 if (msaa_info->rasterizationSamples > 1 ||
1860 /* also set msaa key when sample location is not the default
1861 * since this affects varying interpolation */
1862 (sample_locations && sample_locations->sampleLocationsEnable)) {
1863 key->msaa = true;
1864 }
1865
1866 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1867 if (msaa_info->sampleShadingEnable)
1868 key->sample_shading = true;
1869
1870 /* We set this after we compile to NIR because we need the prim mode */
1871 key->tessellation = IR3_TESS_NONE;
1872 }
1873
1874 static uint32_t
1875 tu6_get_tessmode(struct tu_shader* shader)
1876 {
1877 uint32_t primitive_mode = shader->ir3_shader->nir->info.tess.primitive_mode;
1878 switch (primitive_mode) {
1879 case GL_ISOLINES:
1880 return IR3_TESS_ISOLINES;
1881 case GL_TRIANGLES:
1882 return IR3_TESS_TRIANGLES;
1883 case GL_QUADS:
1884 return IR3_TESS_QUADS;
1885 case GL_NONE:
1886 return IR3_TESS_NONE;
1887 default:
1888 unreachable("bad tessmode");
1889 }
1890 }
1891
1892 static uint64_t
1893 tu_upload_variant(struct tu_pipeline *pipeline,
1894 const struct ir3_shader_variant *variant)
1895 {
1896 struct tu_cs_memory memory;
1897
1898 if (!variant)
1899 return 0;
1900
1901 /* this expects to get enough alignment because shaders are allocated first
1902 * and sizedwords is always aligned correctly
1903 * note: an assert in tu6_emit_xs_config validates the alignment
1904 */
1905 tu_cs_alloc(&pipeline->cs, variant->info.sizedwords, 1, &memory);
1906
1907 memcpy(memory.map, variant->bin, sizeof(uint32_t) * variant->info.sizedwords);
1908 return memory.iova;
1909 }
1910
1911 static VkResult
1912 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
1913 struct tu_pipeline *pipeline)
1914 {
1915 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1916 NULL
1917 };
1918 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1919 gl_shader_stage stage =
1920 vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage);
1921 stage_infos[stage] = &builder->create_info->pStages[i];
1922 }
1923
1924 struct ir3_shader_key key = {};
1925 tu_pipeline_shader_key_init(&key, builder->create_info);
1926
1927 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1928 stage < MESA_SHADER_STAGES; stage++) {
1929 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1930 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
1931 continue;
1932
1933 struct tu_shader *shader =
1934 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1935 builder->alloc);
1936 if (!shader)
1937 return VK_ERROR_OUT_OF_HOST_MEMORY;
1938
1939 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
1940 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
1941 * the mode is specified in the tessellation control shader. */
1942 if ((stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_TESS_CTRL) &&
1943 key.tessellation == IR3_TESS_NONE) {
1944 key.tessellation = tu6_get_tessmode(shader);
1945 }
1946
1947 builder->shaders[stage] = shader;
1948 }
1949
1950 pipeline->tess.patch_type = key.tessellation;
1951
1952 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1953 stage > MESA_SHADER_NONE; stage--) {
1954 if (!builder->shaders[stage])
1955 continue;
1956
1957 bool created;
1958 builder->variants[stage] =
1959 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
1960 &key, false, &created);
1961 if (!builder->variants[stage])
1962 return VK_ERROR_OUT_OF_HOST_MEMORY;
1963 }
1964
1965 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1966 struct ir3_shader_variant *variant;
1967
1968 if (vs->ir3_shader->stream_output.num_outputs) {
1969 variant = builder->variants[MESA_SHADER_VERTEX];
1970 } else {
1971 bool created;
1972 variant = ir3_shader_get_variant(vs->ir3_shader, &key,
1973 true, &created);
1974 if (!variant)
1975 return VK_ERROR_OUT_OF_HOST_MEMORY;
1976 }
1977
1978 builder->binning_variant = variant;
1979
1980 if (builder->shaders[MESA_SHADER_TESS_CTRL]) {
1981 struct ir3_shader *hs =
1982 builder->shaders[MESA_SHADER_TESS_CTRL]->ir3_shader;
1983 assert(hs->type != MESA_SHADER_NONE);
1984
1985 /* Calculate and store the per-vertex and per-patch HS-output sizes. */
1986 uint32_t per_vertex_output_size = 0;
1987 uint32_t per_patch_output_size = 0;
1988 nir_foreach_variable (output, &hs->nir->outputs) {
1989 switch (output->data.location) {
1990 case VARYING_SLOT_TESS_LEVEL_OUTER:
1991 case VARYING_SLOT_TESS_LEVEL_INNER:
1992 continue;
1993 }
1994 uint32_t size = glsl_count_attribute_slots(output->type, false) * 4;
1995 if (output->data.patch)
1996 per_patch_output_size += size;
1997 else
1998 per_vertex_output_size += size;
1999 }
2000 pipeline->tess.per_vertex_output_size = per_vertex_output_size;
2001 pipeline->tess.per_patch_output_size = per_patch_output_size;
2002 }
2003
2004 return VK_SUCCESS;
2005 }
2006
2007 static void
2008 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2009 struct tu_pipeline *pipeline)
2010 {
2011 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2012 builder->create_info->pDynamicState;
2013
2014 if (!dynamic_info)
2015 return;
2016
2017 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2018 VkDynamicState state = dynamic_info->pDynamicStates[i];
2019 switch (state) {
2020 case VK_DYNAMIC_STATE_VIEWPORT ... VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2021 pipeline->dynamic_state_mask |= BIT(state);
2022 break;
2023 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
2024 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS);
2025 break;
2026 default:
2027 assert(!"unsupported dynamic state");
2028 break;
2029 }
2030 }
2031 }
2032
2033 static void
2034 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2035 struct tu_shader *shader,
2036 struct ir3_shader_variant *v)
2037 {
2038 link->const_state = *ir3_const_state(v);
2039 link->constlen = v->constlen;
2040 link->push_consts = shader->push_consts;
2041 }
2042
2043 static void
2044 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2045 struct tu_pipeline *pipeline)
2046 {
2047 struct tu_cs prog_cs;
2048 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2049 tu6_emit_program(&prog_cs, builder, false);
2050 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2051
2052 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2053 tu6_emit_program(&prog_cs, builder, true);
2054 pipeline->program.binning_state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2055
2056 VkShaderStageFlags stages = 0;
2057 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2058 stages |= builder->create_info->pStages[i].stage;
2059 }
2060 pipeline->active_stages = stages;
2061
2062 uint32_t desc_sets = 0;
2063 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2064 if (!builder->shaders[i])
2065 continue;
2066
2067 tu_pipeline_set_linkage(&pipeline->program.link[i],
2068 builder->shaders[i],
2069 builder->variants[i]);
2070 desc_sets |= builder->shaders[i]->active_desc_sets;
2071 }
2072 pipeline->active_desc_sets = desc_sets;
2073 }
2074
2075 static void
2076 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2077 struct tu_pipeline *pipeline)
2078 {
2079 const VkPipelineVertexInputStateCreateInfo *vi_info =
2080 builder->create_info->pVertexInputState;
2081 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
2082 const struct ir3_shader_variant *bs = builder->binning_variant;
2083
2084 struct tu_cs vi_cs;
2085 tu_cs_begin_sub_stream(&pipeline->cs,
2086 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2087 tu6_emit_vertex_input(&vi_cs, vs, vi_info,
2088 &pipeline->vi.bindings_used);
2089 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2090
2091 if (bs) {
2092 tu_cs_begin_sub_stream(&pipeline->cs,
2093 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2094 tu6_emit_vertex_input(
2095 &vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
2096 pipeline->vi.binning_state_ib =
2097 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2098 }
2099 }
2100
2101 static void
2102 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2103 struct tu_pipeline *pipeline)
2104 {
2105 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2106 builder->create_info->pInputAssemblyState;
2107
2108 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2109 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2110 }
2111
2112 static bool
2113 tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs,
2114 uint32_t id, uint32_t size)
2115 {
2116 struct tu_cs_memory memory;
2117
2118 if (pipeline->dynamic_state_mask & BIT(id))
2119 return false;
2120
2121 /* TODO: share this logc with tu_cmd_dynamic_state */
2122 tu_cs_alloc(&pipeline->cs, size, 1, &memory);
2123 tu_cs_init_external(cs, memory.map, memory.map + size);
2124 tu_cs_begin(cs);
2125 tu_cs_reserve_space(cs, size);
2126
2127 assert(id < ARRAY_SIZE(pipeline->dynamic_state));
2128 pipeline->dynamic_state[id].iova = memory.iova;
2129 pipeline->dynamic_state[id].size = size;
2130 return true;
2131 }
2132
2133 static void
2134 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder,
2135 struct tu_pipeline *pipeline)
2136 {
2137 const VkPipelineTessellationStateCreateInfo *tess_info =
2138 builder->create_info->pTessellationState;
2139
2140 if (!tess_info)
2141 return;
2142
2143 assert(pipeline->ia.primtype == DI_PT_PATCHES0);
2144 assert(tess_info->patchControlPoints <= 32);
2145 pipeline->ia.primtype += tess_info->patchControlPoints;
2146 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info =
2147 vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2148 pipeline->tess.upper_left_domain_origin = !domain_info ||
2149 domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
2150 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
2151 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
2152 pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1;
2153 pipeline->tess.ds_bo_regid = ds->const_state->offsets.primitive_param + 1;
2154 }
2155
2156 static void
2157 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2158 struct tu_pipeline *pipeline)
2159 {
2160 /* The spec says:
2161 *
2162 * pViewportState is a pointer to an instance of the
2163 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2164 * pipeline has rasterization disabled."
2165 *
2166 * We leave the relevant registers stale in that case.
2167 */
2168 if (builder->rasterizer_discard)
2169 return;
2170
2171 const VkPipelineViewportStateCreateInfo *vp_info =
2172 builder->create_info->pViewportState;
2173
2174 struct tu_cs cs;
2175
2176 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_VIEWPORT, 18))
2177 tu6_emit_viewport(&cs, vp_info->pViewports);
2178
2179 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_SCISSOR, 3))
2180 tu6_emit_scissor(&cs, vp_info->pScissors);
2181 }
2182
2183 static void
2184 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2185 struct tu_pipeline *pipeline)
2186 {
2187 const VkPipelineRasterizationStateCreateInfo *rast_info =
2188 builder->create_info->pRasterizationState;
2189
2190 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2191
2192 struct tu_cs cs;
2193 tu_cs_begin_sub_stream(&pipeline->cs, 7, &cs);
2194
2195 tu_cs_emit_regs(&cs,
2196 A6XX_GRAS_CL_CNTL(
2197 .znear_clip_disable = rast_info->depthClampEnable,
2198 .zfar_clip_disable = rast_info->depthClampEnable,
2199 .unk5 = rast_info->depthClampEnable,
2200 .zero_gb_scale_z = 1,
2201 .vp_clip_code_ignore = 1));
2202 /* move to hw ctx init? */
2203 tu_cs_emit_regs(&cs, A6XX_GRAS_UNKNOWN_8001());
2204 tu_cs_emit_regs(&cs,
2205 A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
2206 A6XX_GRAS_SU_POINT_SIZE(1.0f));
2207
2208 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2209
2210 pipeline->gras_su_cntl =
2211 tu6_gras_su_cntl(rast_info, builder->samples);
2212
2213 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_LINE_WIDTH, 2)) {
2214 pipeline->gras_su_cntl |=
2215 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info->lineWidth / 2.0f);
2216 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = pipeline->gras_su_cntl));
2217 }
2218
2219 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BIAS, 4)) {
2220 tu6_emit_depth_bias(&cs, rast_info->depthBiasConstantFactor,
2221 rast_info->depthBiasClamp,
2222 rast_info->depthBiasSlopeFactor);
2223 }
2224
2225 }
2226
2227 static void
2228 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2229 struct tu_pipeline *pipeline)
2230 {
2231 /* The spec says:
2232 *
2233 * pDepthStencilState is a pointer to an instance of the
2234 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2235 * the pipeline has rasterization disabled or if the subpass of the
2236 * render pass the pipeline is created against does not use a
2237 * depth/stencil attachment.
2238 *
2239 * Disable both depth and stencil tests if there is no ds attachment,
2240 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2241 * only the separate stencil attachment
2242 */
2243 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2244 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2245 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2246 ? builder->create_info->pDepthStencilState
2247 : &dummy_ds_info;
2248 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2249 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2250 ? ds_info : &dummy_ds_info;
2251
2252 struct tu_cs cs;
2253 tu_cs_begin_sub_stream(&pipeline->cs, 6, &cs);
2254
2255 /* move to hw ctx init? */
2256 tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
2257 tu6_emit_depth_control(&cs, ds_info_depth,
2258 builder->create_info->pRasterizationState);
2259 tu6_emit_stencil_control(&cs, ds_info);
2260
2261 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2262
2263 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
2264 tu_cs_emit_regs(&cs,
2265 A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
2266 A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
2267 }
2268
2269 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
2270 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
2271 .bfmask = ds_info->back.compareMask & 0xff));
2272 }
2273
2274 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2)) {
2275 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.wrmask = ds_info->front.writeMask & 0xff,
2276 .bfwrmask = ds_info->back.writeMask & 0xff));
2277 }
2278
2279 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2)) {
2280 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.ref = ds_info->front.reference & 0xff,
2281 .bfref = ds_info->back.reference & 0xff));
2282 }
2283 }
2284
2285 static void
2286 tu_pipeline_builder_parse_multisample_and_color_blend(
2287 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2288 {
2289 /* The spec says:
2290 *
2291 * pMultisampleState is a pointer to an instance of the
2292 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2293 * has rasterization disabled.
2294 *
2295 * Also,
2296 *
2297 * pColorBlendState is a pointer to an instance of the
2298 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2299 * pipeline has rasterization disabled or if the subpass of the render
2300 * pass the pipeline is created against does not use any color
2301 * attachments.
2302 *
2303 * We leave the relevant registers stale when rasterization is disabled.
2304 */
2305 if (builder->rasterizer_discard)
2306 return;
2307
2308 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2309 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2310 builder->create_info->pMultisampleState;
2311 const VkPipelineColorBlendStateCreateInfo *blend_info =
2312 builder->use_color_attachments ? builder->create_info->pColorBlendState
2313 : &dummy_blend_info;
2314
2315 struct tu_cs cs;
2316 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 4, &cs);
2317
2318 uint32_t blend_enable_mask;
2319 tu6_emit_rb_mrt_controls(&cs, blend_info,
2320 builder->color_attachment_formats,
2321 &blend_enable_mask);
2322
2323 tu6_emit_blend_control(&cs, blend_enable_mask,
2324 builder->use_dual_src_blend, msaa_info);
2325
2326 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2327
2328 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5)) {
2329 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2330 tu_cs_emit_array(&cs, (const uint32_t *) blend_info->blendConstants, 4);
2331 }
2332
2333 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2334 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2335 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2336
2337 if (sample_locations && sample_locations->sampleLocationsEnable)
2338 samp_loc = &sample_locations->sampleLocationsInfo;
2339
2340 if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
2341 samp_loc ? 9 : 6)) {
2342 tu6_emit_sample_locations(&cs, samp_loc);
2343 }
2344 }
2345
2346 static void
2347 tu_pipeline_finish(struct tu_pipeline *pipeline,
2348 struct tu_device *dev,
2349 const VkAllocationCallbacks *alloc)
2350 {
2351 tu_cs_finish(&pipeline->cs);
2352 }
2353
2354 static VkResult
2355 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2356 struct tu_pipeline **pipeline)
2357 {
2358 VkResult result;
2359
2360 *pipeline =
2361 vk_zalloc2(&builder->device->alloc, builder->alloc, sizeof(**pipeline),
2362 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2363 if (!*pipeline)
2364 return VK_ERROR_OUT_OF_HOST_MEMORY;
2365
2366 (*pipeline)->layout = builder->layout;
2367
2368 /* compile and upload shaders */
2369 result = tu_pipeline_builder_compile_shaders(builder, *pipeline);
2370 if (result != VK_SUCCESS) {
2371 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2372 return result;
2373 }
2374
2375 result = tu_pipeline_allocate_cs(builder->device, *pipeline, builder, NULL);
2376 if (result != VK_SUCCESS) {
2377 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2378 return result;
2379 }
2380
2381 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2382 builder->shader_iova[i] = tu_upload_variant(*pipeline, builder->variants[i]);
2383
2384 builder->binning_vs_iova =
2385 tu_upload_variant(*pipeline, builder->binning_variant);
2386
2387 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2388 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2389 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2390 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2391 tu_pipeline_builder_parse_tessellation(builder, *pipeline);
2392 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2393 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2394 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2395 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2396 tu6_emit_load_state(*pipeline, false);
2397
2398 /* we should have reserved enough space upfront such that the CS never
2399 * grows
2400 */
2401 assert((*pipeline)->cs.bo_count == 1);
2402
2403 return VK_SUCCESS;
2404 }
2405
2406 static void
2407 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2408 {
2409 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2410 if (!builder->shaders[i])
2411 continue;
2412 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2413 }
2414 }
2415
2416 static void
2417 tu_pipeline_builder_init_graphics(
2418 struct tu_pipeline_builder *builder,
2419 struct tu_device *dev,
2420 struct tu_pipeline_cache *cache,
2421 const VkGraphicsPipelineCreateInfo *create_info,
2422 const VkAllocationCallbacks *alloc)
2423 {
2424 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2425
2426 *builder = (struct tu_pipeline_builder) {
2427 .device = dev,
2428 .cache = cache,
2429 .create_info = create_info,
2430 .alloc = alloc,
2431 .layout = layout,
2432 };
2433
2434 builder->rasterizer_discard =
2435 create_info->pRasterizationState->rasterizerDiscardEnable;
2436
2437 if (builder->rasterizer_discard) {
2438 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2439 } else {
2440 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2441
2442 const struct tu_render_pass *pass =
2443 tu_render_pass_from_handle(create_info->renderPass);
2444 const struct tu_subpass *subpass =
2445 &pass->subpasses[create_info->subpass];
2446
2447 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2448 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2449 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2450
2451 assert(subpass->color_count == 0 ||
2452 !create_info->pColorBlendState ||
2453 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2454 builder->color_attachment_count = subpass->color_count;
2455 for (uint32_t i = 0; i < subpass->color_count; i++) {
2456 const uint32_t a = subpass->color_attachments[i].attachment;
2457 if (a == VK_ATTACHMENT_UNUSED)
2458 continue;
2459
2460 builder->color_attachment_formats[i] = pass->attachments[a].format;
2461 builder->use_color_attachments = true;
2462 builder->render_components |= 0xf << (i * 4);
2463 }
2464
2465 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2466 builder->color_attachment_count++;
2467 builder->use_dual_src_blend = true;
2468 /* dual source blending has an extra fs output in the 2nd slot */
2469 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2470 builder->render_components |= 0xf << 4;
2471 }
2472 }
2473 }
2474
2475 static VkResult
2476 tu_graphics_pipeline_create(VkDevice device,
2477 VkPipelineCache pipelineCache,
2478 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2479 const VkAllocationCallbacks *pAllocator,
2480 VkPipeline *pPipeline)
2481 {
2482 TU_FROM_HANDLE(tu_device, dev, device);
2483 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2484
2485 struct tu_pipeline_builder builder;
2486 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2487 pCreateInfo, pAllocator);
2488
2489 struct tu_pipeline *pipeline = NULL;
2490 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2491 tu_pipeline_builder_finish(&builder);
2492
2493 if (result == VK_SUCCESS)
2494 *pPipeline = tu_pipeline_to_handle(pipeline);
2495 else
2496 *pPipeline = VK_NULL_HANDLE;
2497
2498 return result;
2499 }
2500
2501 VkResult
2502 tu_CreateGraphicsPipelines(VkDevice device,
2503 VkPipelineCache pipelineCache,
2504 uint32_t count,
2505 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2506 const VkAllocationCallbacks *pAllocator,
2507 VkPipeline *pPipelines)
2508 {
2509 VkResult final_result = VK_SUCCESS;
2510
2511 for (uint32_t i = 0; i < count; i++) {
2512 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2513 &pCreateInfos[i], pAllocator,
2514 &pPipelines[i]);
2515
2516 if (result != VK_SUCCESS)
2517 final_result = result;
2518 }
2519
2520 return final_result;
2521 }
2522
2523 static VkResult
2524 tu_compute_pipeline_create(VkDevice device,
2525 VkPipelineCache _cache,
2526 const VkComputePipelineCreateInfo *pCreateInfo,
2527 const VkAllocationCallbacks *pAllocator,
2528 VkPipeline *pPipeline)
2529 {
2530 TU_FROM_HANDLE(tu_device, dev, device);
2531 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2532 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2533 VkResult result;
2534
2535 struct tu_pipeline *pipeline;
2536
2537 *pPipeline = VK_NULL_HANDLE;
2538
2539 pipeline =
2540 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
2541 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2542 if (!pipeline)
2543 return VK_ERROR_OUT_OF_HOST_MEMORY;
2544
2545 pipeline->layout = layout;
2546
2547 struct ir3_shader_key key = {};
2548
2549 struct tu_shader *shader =
2550 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2551 if (!shader) {
2552 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2553 goto fail;
2554 }
2555
2556 bool created;
2557 struct ir3_shader_variant *v =
2558 ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
2559 if (!v) {
2560 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2561 goto fail;
2562 }
2563
2564 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2565 shader, v);
2566
2567 result = tu_pipeline_allocate_cs(dev, pipeline, NULL, v);
2568 if (result != VK_SUCCESS)
2569 goto fail;
2570
2571 uint64_t shader_iova = tu_upload_variant(pipeline, v);
2572
2573 for (int i = 0; i < 3; i++)
2574 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2575
2576 struct tu_cs prog_cs;
2577 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2578 tu6_emit_cs_config(&prog_cs, shader, v, shader_iova);
2579 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2580
2581 tu6_emit_load_state(pipeline, true);
2582
2583 *pPipeline = tu_pipeline_to_handle(pipeline);
2584 return VK_SUCCESS;
2585
2586 fail:
2587 if (shader)
2588 tu_shader_destroy(dev, shader, pAllocator);
2589
2590 vk_free2(&dev->alloc, pAllocator, pipeline);
2591
2592 return result;
2593 }
2594
2595 VkResult
2596 tu_CreateComputePipelines(VkDevice device,
2597 VkPipelineCache pipelineCache,
2598 uint32_t count,
2599 const VkComputePipelineCreateInfo *pCreateInfos,
2600 const VkAllocationCallbacks *pAllocator,
2601 VkPipeline *pPipelines)
2602 {
2603 VkResult final_result = VK_SUCCESS;
2604
2605 for (uint32_t i = 0; i < count; i++) {
2606 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2607 &pCreateInfos[i],
2608 pAllocator, &pPipelines[i]);
2609 if (result != VK_SUCCESS)
2610 final_result = result;
2611 }
2612
2613 return final_result;
2614 }
2615
2616 void
2617 tu_DestroyPipeline(VkDevice _device,
2618 VkPipeline _pipeline,
2619 const VkAllocationCallbacks *pAllocator)
2620 {
2621 TU_FROM_HANDLE(tu_device, dev, _device);
2622 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2623
2624 if (!_pipeline)
2625 return;
2626
2627 tu_pipeline_finish(pipeline, dev, pAllocator);
2628 vk_free2(&dev->alloc, pAllocator, pipeline);
2629 }