2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
44 tu6_stage2opcode(gl_shader_stage stage
)
46 if (stage
== MESA_SHADER_FRAGMENT
|| stage
== MESA_SHADER_COMPUTE
)
47 return CP_LOAD_STATE6_FRAG
;
48 return CP_LOAD_STATE6_GEOM
;
51 static enum a6xx_state_block
52 tu6_stage2texsb(gl_shader_stage stage
)
54 return SB6_VS_TEX
+ stage
;
58 tu6_stage2shadersb(gl_shader_stage stage
)
60 return SB6_VS_SHADER
+ stage
;
63 /* Emit IB that preloads the descriptors that the shader uses */
66 emit_load_state(struct tu_cs
*cs
, unsigned opcode
, enum a6xx_state_type st
,
67 enum a6xx_state_block sb
, unsigned base
, unsigned offset
,
70 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
71 * clear if emitting more packets will even help anything. Presumably the
72 * descriptor cache is relatively small, and these packets stop doing
73 * anything when there are too many descriptors.
75 tu_cs_emit_pkt7(cs
, opcode
, 3);
77 CP_LOAD_STATE6_0_STATE_TYPE(st
) |
78 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS
) |
79 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
80 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count
, 1024-1)));
81 tu_cs_emit_qw(cs
, offset
| (base
<< 28));
85 tu6_load_state_size(struct tu_pipeline_layout
*layout
, bool compute
)
87 const unsigned load_state_size
= 4;
89 for (unsigned i
= 0; i
< layout
->num_sets
; i
++) {
90 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[i
].layout
;
91 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
92 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
94 /* Note: some users, like amber for example, pass in
95 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
96 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
98 VkShaderStageFlags stages
= compute
?
99 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
100 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
101 unsigned stage_count
= util_bitcount(stages
);
102 switch (binding
->type
) {
103 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
104 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
105 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
106 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
107 /* IBO-backed resources only need one packet for all graphics stages */
108 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
)
110 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)
113 case VK_DESCRIPTOR_TYPE_SAMPLER
:
114 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
115 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
116 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
117 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
118 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
119 /* Textures and UBO's needs a packet for each stage */
122 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
123 /* Because of how we pack combined images and samplers, we
124 * currently can't use one packet for the whole array.
126 count
= stage_count
* binding
->array_size
* 2;
129 unreachable("bad descriptor type");
131 size
+= count
* load_state_size
;
138 tu6_emit_load_state(struct tu_pipeline
*pipeline
, bool compute
)
140 unsigned size
= tu6_load_state_size(pipeline
->layout
, compute
);
145 tu_cs_begin_sub_stream(&pipeline
->cs
, size
, &cs
);
147 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
148 for (unsigned i
= 0; i
< layout
->num_sets
; i
++) {
149 /* From 13.2.7. Descriptor Set Binding:
151 * A compatible descriptor set must be bound for all set numbers that
152 * any shaders in a pipeline access, at the time that a draw or
153 * dispatch command is recorded to execute using that pipeline.
154 * However, if none of the shaders in a pipeline statically use any
155 * bindings with a particular set number, then no descriptor set need
156 * be bound for that set number, even if the pipeline layout includes
157 * a non-trivial descriptor set layout for that set number.
159 * This means that descriptor sets unused by the pipeline may have a
160 * garbage or 0 BINDLESS_BASE register, which will cause context faults
161 * when prefetching descriptors from these sets. Skip prefetching for
162 * descriptors from them to avoid this. This is also an optimization,
163 * since these prefetches would be useless.
165 if (!(pipeline
->active_desc_sets
& (1u << i
)))
168 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[i
].layout
;
169 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
170 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
172 unsigned offset
= binding
->offset
/ 4;
173 /* Note: some users, like amber for example, pass in
174 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
175 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
177 VkShaderStageFlags stages
= compute
?
178 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
179 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
180 unsigned count
= binding
->array_size
;
181 if (count
== 0 || stages
== 0)
183 switch (binding
->type
) {
184 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
186 offset
= (layout
->input_attachment_count
+
187 layout
->set
[i
].dynamic_offset_start
+
188 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
190 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
191 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
192 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
193 /* IBO-backed resources only need one packet for all graphics stages */
194 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
) {
195 emit_load_state(&cs
, CP_LOAD_STATE6
, ST6_SHADER
, SB6_IBO
,
196 base
, offset
, count
);
198 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
) {
199 emit_load_state(&cs
, CP_LOAD_STATE6_FRAG
, ST6_IBO
, SB6_CS_SHADER
,
200 base
, offset
, count
);
203 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
205 offset
= (layout
->set
[i
].input_attachment_start
+
206 binding
->input_attachment_offset
) * A6XX_TEX_CONST_DWORDS
;
207 case VK_DESCRIPTOR_TYPE_SAMPLER
:
208 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
209 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
: {
210 tu_foreach_stage(stage
, stages
) {
211 emit_load_state(&cs
, tu6_stage2opcode(stage
),
212 binding
->type
== VK_DESCRIPTOR_TYPE_SAMPLER
?
213 ST6_SHADER
: ST6_CONSTANTS
,
214 tu6_stage2texsb(stage
), base
, offset
, count
);
218 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
220 offset
= (layout
->input_attachment_count
+
221 layout
->set
[i
].dynamic_offset_start
+
222 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
224 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
: {
225 tu_foreach_stage(stage
, stages
) {
226 emit_load_state(&cs
, tu6_stage2opcode(stage
), ST6_UBO
,
227 tu6_stage2shadersb(stage
), base
, offset
, count
);
231 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
: {
232 tu_foreach_stage(stage
, stages
) {
233 /* TODO: We could emit less CP_LOAD_STATE6 if we used
234 * struct-of-arrays instead of array-of-structs.
236 for (unsigned i
= 0; i
< count
; i
++) {
237 unsigned tex_offset
= offset
+ 2 * i
* A6XX_TEX_CONST_DWORDS
;
238 unsigned sam_offset
= offset
+ (2 * i
+ 1) * A6XX_TEX_CONST_DWORDS
;
239 emit_load_state(&cs
, tu6_stage2opcode(stage
),
240 ST6_CONSTANTS
, tu6_stage2texsb(stage
),
241 base
, tex_offset
, 1);
242 emit_load_state(&cs
, tu6_stage2opcode(stage
),
243 ST6_SHADER
, tu6_stage2texsb(stage
),
244 base
, sam_offset
, 1);
250 unreachable("bad descriptor type");
255 pipeline
->load_state
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &cs
);
258 struct tu_pipeline_builder
260 struct tu_device
*device
;
261 struct tu_pipeline_cache
*cache
;
262 struct tu_pipeline_layout
*layout
;
263 const VkAllocationCallbacks
*alloc
;
264 const VkGraphicsPipelineCreateInfo
*create_info
;
266 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
267 struct ir3_shader_variant
*variants
[MESA_SHADER_STAGES
];
268 struct ir3_shader_variant
*binning_variant
;
269 uint32_t shader_offsets
[MESA_SHADER_STAGES
];
270 uint32_t binning_vs_offset
;
271 uint32_t shader_total_size
;
273 bool rasterizer_discard
;
274 /* these states are affectd by rasterizer_discard */
275 VkSampleCountFlagBits samples
;
276 bool use_color_attachments
;
277 bool use_dual_src_blend
;
278 uint32_t color_attachment_count
;
279 VkFormat color_attachment_formats
[MAX_RTS
];
280 VkFormat depth_attachment_format
;
281 uint32_t render_components
;
285 tu_logic_op_reads_dst(VkLogicOp op
)
288 case VK_LOGIC_OP_CLEAR
:
289 case VK_LOGIC_OP_COPY
:
290 case VK_LOGIC_OP_COPY_INVERTED
:
291 case VK_LOGIC_OP_SET
:
299 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
301 /* treat dst alpha as 1.0 and avoid reading it */
303 case VK_BLEND_FACTOR_DST_ALPHA
:
304 return VK_BLEND_FACTOR_ONE
;
305 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
306 return VK_BLEND_FACTOR_ZERO
;
312 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor
)
315 case VK_BLEND_FACTOR_SRC1_COLOR
:
316 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
317 case VK_BLEND_FACTOR_SRC1_ALPHA
:
318 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
326 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo
*info
)
331 for (unsigned i
= 0; i
< info
->attachmentCount
; i
++) {
332 const VkPipelineColorBlendAttachmentState
*blend
= &info
->pAttachments
[i
];
333 if (tu_blend_factor_is_dual_src(blend
->srcColorBlendFactor
) ||
334 tu_blend_factor_is_dual_src(blend
->dstColorBlendFactor
) ||
335 tu_blend_factor_is_dual_src(blend
->srcAlphaBlendFactor
) ||
336 tu_blend_factor_is_dual_src(blend
->dstAlphaBlendFactor
))
343 static enum pc_di_primtype
344 tu6_primtype(VkPrimitiveTopology topology
)
347 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
348 return DI_PT_POINTLIST
;
349 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
350 return DI_PT_LINELIST
;
351 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
352 return DI_PT_LINESTRIP
;
353 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
354 return DI_PT_TRILIST
;
355 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
356 return DI_PT_TRISTRIP
;
357 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
359 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
360 return DI_PT_LINE_ADJ
;
361 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
362 return DI_PT_LINESTRIP_ADJ
;
363 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
364 return DI_PT_TRI_ADJ
;
365 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
366 return DI_PT_TRISTRIP_ADJ
;
367 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
369 unreachable("invalid primitive topology");
374 static enum adreno_compare_func
375 tu6_compare_func(VkCompareOp op
)
378 case VK_COMPARE_OP_NEVER
:
380 case VK_COMPARE_OP_LESS
:
382 case VK_COMPARE_OP_EQUAL
:
384 case VK_COMPARE_OP_LESS_OR_EQUAL
:
386 case VK_COMPARE_OP_GREATER
:
388 case VK_COMPARE_OP_NOT_EQUAL
:
389 return FUNC_NOTEQUAL
;
390 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
392 case VK_COMPARE_OP_ALWAYS
:
395 unreachable("invalid VkCompareOp");
400 static enum adreno_stencil_op
401 tu6_stencil_op(VkStencilOp op
)
404 case VK_STENCIL_OP_KEEP
:
406 case VK_STENCIL_OP_ZERO
:
408 case VK_STENCIL_OP_REPLACE
:
409 return STENCIL_REPLACE
;
410 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
411 return STENCIL_INCR_CLAMP
;
412 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
413 return STENCIL_DECR_CLAMP
;
414 case VK_STENCIL_OP_INVERT
:
415 return STENCIL_INVERT
;
416 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
417 return STENCIL_INCR_WRAP
;
418 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
419 return STENCIL_DECR_WRAP
;
421 unreachable("invalid VkStencilOp");
426 static enum a3xx_rop_code
427 tu6_rop(VkLogicOp op
)
430 case VK_LOGIC_OP_CLEAR
:
432 case VK_LOGIC_OP_AND
:
434 case VK_LOGIC_OP_AND_REVERSE
:
435 return ROP_AND_REVERSE
;
436 case VK_LOGIC_OP_COPY
:
438 case VK_LOGIC_OP_AND_INVERTED
:
439 return ROP_AND_INVERTED
;
440 case VK_LOGIC_OP_NO_OP
:
442 case VK_LOGIC_OP_XOR
:
446 case VK_LOGIC_OP_NOR
:
448 case VK_LOGIC_OP_EQUIVALENT
:
450 case VK_LOGIC_OP_INVERT
:
452 case VK_LOGIC_OP_OR_REVERSE
:
453 return ROP_OR_REVERSE
;
454 case VK_LOGIC_OP_COPY_INVERTED
:
455 return ROP_COPY_INVERTED
;
456 case VK_LOGIC_OP_OR_INVERTED
:
457 return ROP_OR_INVERTED
;
458 case VK_LOGIC_OP_NAND
:
460 case VK_LOGIC_OP_SET
:
463 unreachable("invalid VkLogicOp");
468 static enum adreno_rb_blend_factor
469 tu6_blend_factor(VkBlendFactor factor
)
472 case VK_BLEND_FACTOR_ZERO
:
474 case VK_BLEND_FACTOR_ONE
:
476 case VK_BLEND_FACTOR_SRC_COLOR
:
477 return FACTOR_SRC_COLOR
;
478 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
479 return FACTOR_ONE_MINUS_SRC_COLOR
;
480 case VK_BLEND_FACTOR_DST_COLOR
:
481 return FACTOR_DST_COLOR
;
482 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
483 return FACTOR_ONE_MINUS_DST_COLOR
;
484 case VK_BLEND_FACTOR_SRC_ALPHA
:
485 return FACTOR_SRC_ALPHA
;
486 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
487 return FACTOR_ONE_MINUS_SRC_ALPHA
;
488 case VK_BLEND_FACTOR_DST_ALPHA
:
489 return FACTOR_DST_ALPHA
;
490 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
491 return FACTOR_ONE_MINUS_DST_ALPHA
;
492 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
493 return FACTOR_CONSTANT_COLOR
;
494 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
495 return FACTOR_ONE_MINUS_CONSTANT_COLOR
;
496 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
497 return FACTOR_CONSTANT_ALPHA
;
498 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
499 return FACTOR_ONE_MINUS_CONSTANT_ALPHA
;
500 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
501 return FACTOR_SRC_ALPHA_SATURATE
;
502 case VK_BLEND_FACTOR_SRC1_COLOR
:
503 return FACTOR_SRC1_COLOR
;
504 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
505 return FACTOR_ONE_MINUS_SRC1_COLOR
;
506 case VK_BLEND_FACTOR_SRC1_ALPHA
:
507 return FACTOR_SRC1_ALPHA
;
508 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
509 return FACTOR_ONE_MINUS_SRC1_ALPHA
;
511 unreachable("invalid VkBlendFactor");
516 static enum a3xx_rb_blend_opcode
517 tu6_blend_op(VkBlendOp op
)
520 case VK_BLEND_OP_ADD
:
521 return BLEND_DST_PLUS_SRC
;
522 case VK_BLEND_OP_SUBTRACT
:
523 return BLEND_SRC_MINUS_DST
;
524 case VK_BLEND_OP_REVERSE_SUBTRACT
:
525 return BLEND_DST_MINUS_SRC
;
526 case VK_BLEND_OP_MIN
:
527 return BLEND_MIN_DST_SRC
;
528 case VK_BLEND_OP_MAX
:
529 return BLEND_MAX_DST_SRC
;
531 unreachable("invalid VkBlendOp");
532 return BLEND_DST_PLUS_SRC
;
537 tu6_emit_xs_config(struct tu_cs
*cs
,
538 gl_shader_stage stage
, /* xs->type, but xs may be NULL */
539 const struct ir3_shader_variant
*xs
,
540 uint64_t binary_iova
)
542 static const struct xs_config
{
543 uint16_t reg_sp_xs_ctrl
;
544 uint16_t reg_sp_xs_config
;
545 uint16_t reg_hlsq_xs_ctrl
;
546 uint16_t reg_sp_vs_obj_start
;
548 [MESA_SHADER_VERTEX
] = {
549 REG_A6XX_SP_VS_CTRL_REG0
,
550 REG_A6XX_SP_VS_CONFIG
,
551 REG_A6XX_HLSQ_VS_CNTL
,
552 REG_A6XX_SP_VS_OBJ_START_LO
,
554 [MESA_SHADER_TESS_CTRL
] = {
555 REG_A6XX_SP_HS_CTRL_REG0
,
556 REG_A6XX_SP_HS_CONFIG
,
557 REG_A6XX_HLSQ_HS_CNTL
,
558 REG_A6XX_SP_HS_OBJ_START_LO
,
560 [MESA_SHADER_TESS_EVAL
] = {
561 REG_A6XX_SP_DS_CTRL_REG0
,
562 REG_A6XX_SP_DS_CONFIG
,
563 REG_A6XX_HLSQ_DS_CNTL
,
564 REG_A6XX_SP_DS_OBJ_START_LO
,
566 [MESA_SHADER_GEOMETRY
] = {
567 REG_A6XX_SP_GS_CTRL_REG0
,
568 REG_A6XX_SP_GS_CONFIG
,
569 REG_A6XX_HLSQ_GS_CNTL
,
570 REG_A6XX_SP_GS_OBJ_START_LO
,
572 [MESA_SHADER_FRAGMENT
] = {
573 REG_A6XX_SP_FS_CTRL_REG0
,
574 REG_A6XX_SP_FS_CONFIG
,
575 REG_A6XX_HLSQ_FS_CNTL
,
576 REG_A6XX_SP_FS_OBJ_START_LO
,
578 [MESA_SHADER_COMPUTE
] = {
579 REG_A6XX_SP_CS_CTRL_REG0
,
580 REG_A6XX_SP_CS_CONFIG
,
581 REG_A6XX_HLSQ_CS_CNTL
,
582 REG_A6XX_SP_CS_OBJ_START_LO
,
585 const struct xs_config
*cfg
= &xs_config
[stage
];
588 /* shader stage disabled */
589 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_config
, 1);
592 tu_cs_emit_pkt4(cs
, cfg
->reg_hlsq_xs_ctrl
, 1);
597 bool is_fs
= xs
->type
== MESA_SHADER_FRAGMENT
;
598 enum a3xx_threadsize threadsize
= FOUR_QUADS
;
601 * the "threadsize" field may have nothing to do with threadsize,
602 * use a value that matches the blob until it is figured out
604 if (xs
->type
== MESA_SHADER_GEOMETRY
)
605 threadsize
= TWO_QUADS
;
607 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_ctrl
, 1);
609 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize
) |
610 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs
->info
.max_reg
+ 1) |
611 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
612 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs
->branchstack
) |
613 COND(xs
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
) |
614 COND(xs
->need_fine_derivatives
, A6XX_SP_VS_CTRL_REG0_DIFF_FINE
) |
615 /* only fragment shader sets VARYING bit */
616 COND(xs
->total_in
&& is_fs
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
617 /* unknown bit, seems unnecessary */
618 COND(is_fs
, 0x1000000));
620 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_config
, 2);
621 tu_cs_emit(cs
, A6XX_SP_VS_CONFIG_ENABLED
|
622 COND(xs
->bindless_tex
, A6XX_SP_VS_CONFIG_BINDLESS_TEX
) |
623 COND(xs
->bindless_samp
, A6XX_SP_VS_CONFIG_BINDLESS_SAMP
) |
624 COND(xs
->bindless_ibo
, A6XX_SP_VS_CONFIG_BINDLESS_IBO
) |
625 COND(xs
->bindless_ubo
, A6XX_SP_VS_CONFIG_BINDLESS_UBO
) |
626 A6XX_SP_VS_CONFIG_NTEX(xs
->num_samp
) |
627 A6XX_SP_VS_CONFIG_NSAMP(xs
->num_samp
));
628 tu_cs_emit(cs
, xs
->instrlen
);
630 tu_cs_emit_pkt4(cs
, cfg
->reg_hlsq_xs_ctrl
, 1);
631 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(xs
->constlen
, 4)) |
632 A6XX_HLSQ_VS_CNTL_ENABLED
);
634 /* emit program binary
635 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
638 assert((binary_iova
& 0x7f) == 0);
640 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_vs_obj_start
, 2);
641 tu_cs_emit_qw(cs
, binary_iova
);
643 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(stage
), 3);
644 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
645 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
646 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
647 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage
)) |
648 CP_LOAD_STATE6_0_NUM_UNIT(xs
->instrlen
));
649 tu_cs_emit_qw(cs
, binary_iova
);
651 /* emit immediates */
653 const struct ir3_const_state
*const_state
= &xs
->shader
->const_state
;
654 uint32_t base
= const_state
->offsets
.immediate
;
655 int size
= const_state
->immediates_count
;
657 /* truncate size to avoid writing constants that shader
660 size
= MIN2(size
+ base
, xs
->constlen
) - base
;
665 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(stage
), 3 + size
* 4);
666 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
667 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
668 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
669 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage
)) |
670 CP_LOAD_STATE6_0_NUM_UNIT(size
));
671 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
672 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
674 for (unsigned i
= 0; i
< size
; i
++) {
675 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
676 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
677 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
678 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
683 tu6_emit_cs_config(struct tu_cs
*cs
, const struct tu_shader
*shader
,
684 const struct ir3_shader_variant
*v
,
685 uint32_t binary_iova
)
687 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
688 tu_cs_emit(cs
, 0xff);
690 tu6_emit_xs_config(cs
, MESA_SHADER_COMPUTE
, v
, binary_iova
);
692 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
693 tu_cs_emit(cs
, 0x41);
695 uint32_t local_invocation_id
=
696 ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
697 uint32_t work_group_id
=
698 ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
700 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
702 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
703 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
704 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
705 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
706 tu_cs_emit(cs
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
710 tu6_emit_vs_system_values(struct tu_cs
*cs
,
711 const struct ir3_shader_variant
*vs
,
712 const struct ir3_shader_variant
*gs
,
713 bool primid_passthru
)
715 const uint32_t vertexid_regid
=
716 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
717 const uint32_t instanceid_regid
=
718 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
719 const uint32_t primitiveid_regid
= gs
?
720 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
) :
722 const uint32_t gsheader_regid
= gs
?
723 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_GS_HEADER_IR3
) :
726 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
727 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
728 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
729 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid
) |
731 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_2 */
732 tu_cs_emit(cs
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
733 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
734 tu_cs_emit(cs
, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid
) |
735 0xfc00); /* VFD_CONTROL_5 */
736 tu_cs_emit(cs
, COND(primid_passthru
, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU
)); /* VFD_CONTROL_6 */
739 /* Add any missing varyings needed for stream-out. Otherwise varyings not
740 * used by fragment shader will be stripped out.
743 tu6_link_streamout(struct ir3_shader_linkage
*l
,
744 const struct ir3_shader_variant
*v
)
746 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
749 * First, any stream-out varyings not already in linkage map (ie. also
750 * consumed by frag shader) need to be added:
752 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
753 const struct ir3_stream_output
*out
= &info
->output
[i
];
755 (1 << (out
->num_components
+ out
->start_component
)) - 1;
756 unsigned k
= out
->register_index
;
757 unsigned idx
, nextloc
= 0;
759 /* psize/pos need to be the last entries in linkage map, and will
760 * get added link_stream_out, so skip over them:
762 if (v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
||
763 v
->outputs
[k
].slot
== VARYING_SLOT_POS
)
766 for (idx
= 0; idx
< l
->cnt
; idx
++) {
767 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
769 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
772 /* add if not already in linkage map: */
774 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
776 /* expand component-mask if needed, ie streaming out all components
777 * but frag shader doesn't consume all components:
779 if (compmask
& ~l
->var
[idx
].compmask
) {
780 l
->var
[idx
].compmask
|= compmask
;
781 l
->max_loc
= MAX2(l
->max_loc
, l
->var
[idx
].loc
+
782 util_last_bit(l
->var
[idx
].compmask
));
788 tu6_setup_streamout(const struct ir3_shader_variant
*v
,
789 struct ir3_shader_linkage
*l
, struct tu_streamout_state
*tf
)
791 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
793 memset(tf
, 0, sizeof(*tf
));
795 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
797 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
799 /* set stride info to the streamout state */
800 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
801 tf
->stride
[i
] = info
->stride
[i
];
803 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
804 const struct ir3_stream_output
*out
= &info
->output
[i
];
805 unsigned k
= out
->register_index
;
808 /* Skip it, if there's an unused reg in the middle of outputs. */
809 if (v
->outputs
[k
].regid
== INVALID_REG
)
812 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
814 /* linkage map sorted by order frag shader wants things, so
815 * a bit less ideal here..
817 for (idx
= 0; idx
< l
->cnt
; idx
++)
818 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
821 debug_assert(idx
< l
->cnt
);
823 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
824 unsigned c
= j
+ out
->start_component
;
825 unsigned loc
= l
->var
[idx
].loc
+ c
;
826 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
829 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
830 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
831 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
833 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
834 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
835 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
840 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
841 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
842 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
843 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
844 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
848 tu6_emit_const(struct tu_cs
*cs
, uint32_t opcode
, uint32_t base
,
849 enum a6xx_state_block block
, uint32_t offset
,
850 uint32_t size
, uint32_t *dwords
) {
851 assert(size
% 4 == 0);
853 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
);
854 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
855 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
856 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
857 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
858 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 4));
860 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
861 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
862 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
864 tu_cs_emit_array(cs
, dwords
, size
);
868 tu6_emit_link_map(struct tu_cs
*cs
,
869 const struct ir3_shader_variant
*producer
,
870 const struct ir3_shader_variant
*consumer
) {
871 const struct ir3_const_state
*const_state
= &consumer
->shader
->const_state
;
872 uint32_t base
= const_state
->offsets
.primitive_map
;
873 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
874 num_loc
= ir3_link_geometry_stages(producer
, consumer
, patch_locs
);
875 int size
= DIV_ROUND_UP(num_loc
, 4);
877 size
= (MIN2(size
+ base
, consumer
->constlen
) - base
) * 4;
881 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, base
, SB6_GS_SHADER
, 0, size
,
886 gl_primitive_to_tess(uint16_t primitive
) {
892 case GL_TRIANGLE_STRIP
:
900 tu6_emit_vpc(struct tu_cs
*cs
,
901 const struct ir3_shader_variant
*vs
,
902 const struct ir3_shader_variant
*gs
,
903 const struct ir3_shader_variant
*fs
,
904 struct tu_streamout_state
*tf
)
906 const struct ir3_shader_variant
*last_shader
= gs
?: vs
;
907 struct ir3_shader_linkage linkage
= { .primid_loc
= 0xff };
909 ir3_link_shaders(&linkage
, last_shader
, fs
, true);
911 if (last_shader
->shader
->stream_output
.num_outputs
)
912 tu6_link_streamout(&linkage
, last_shader
);
914 /* We do this after linking shaders in order to know whether PrimID
915 * passthrough needs to be enabled.
917 bool primid_passthru
= linkage
.primid_loc
!= 0xff;
918 tu6_emit_vs_system_values(cs
, vs
, gs
, primid_passthru
);
920 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
921 tu_cs_emit(cs
, ~linkage
.varmask
[0]);
922 tu_cs_emit(cs
, ~linkage
.varmask
[1]);
923 tu_cs_emit(cs
, ~linkage
.varmask
[2]);
924 tu_cs_emit(cs
, ~linkage
.varmask
[3]);
926 /* a6xx finds position/pointsize at the end */
927 const uint32_t position_regid
=
928 ir3_find_output_regid(last_shader
, VARYING_SLOT_POS
);
929 const uint32_t pointsize_regid
=
930 ir3_find_output_regid(last_shader
, VARYING_SLOT_PSIZ
);
931 const uint32_t layer_regid
= gs
?
932 ir3_find_output_regid(gs
, VARYING_SLOT_LAYER
) : regid(63, 0);
934 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff, layer_loc
= 0xff;
935 if (layer_regid
!= regid(63, 0)) {
936 layer_loc
= linkage
.max_loc
;
937 ir3_link_add(&linkage
, layer_regid
, 0x1, linkage
.max_loc
);
939 if (position_regid
!= regid(63, 0)) {
940 position_loc
= linkage
.max_loc
;
941 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
943 if (pointsize_regid
!= regid(63, 0)) {
944 pointsize_loc
= linkage
.max_loc
;
945 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
948 if (last_shader
->shader
->stream_output
.num_outputs
)
949 tu6_setup_streamout(last_shader
, &linkage
, tf
);
951 /* map outputs of the last shader to VPC */
952 assert(linkage
.cnt
<= 32);
953 const uint32_t sp_out_count
= DIV_ROUND_UP(linkage
.cnt
, 2);
954 const uint32_t sp_vpc_dst_count
= DIV_ROUND_UP(linkage
.cnt
, 4);
956 uint32_t sp_vpc_dst
[8];
957 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
958 ((uint16_t *) sp_out
)[i
] =
959 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
960 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
961 ((uint8_t *) sp_vpc_dst
)[i
] =
962 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
966 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count
);
968 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count
);
969 tu_cs_emit_array(cs
, sp_out
, sp_out_count
);
972 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count
);
974 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count
);
975 tu_cs_emit_array(cs
, sp_vpc_dst
, sp_vpc_dst_count
);
977 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMID_CNTL
, 1);
978 tu_cs_emit(cs
, COND(primid_passthru
, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU
));
980 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
981 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
? fs
->total_in
: 0) |
982 COND(fs
&& fs
->total_in
, A6XX_VPC_CNTL_0_VARYING
) |
983 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage
.primid_loc
) |
984 A6XX_VPC_CNTL_0_UNKLOC(0xff));
986 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
987 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
988 A6XX_VPC_PACK_PSIZELOC(pointsize_loc
) |
989 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
992 uint32_t vertices_out
, invocations
, output
, vec4_size
;
993 /* this detects the tu_clear_blit path, which doesn't set ->nir */
994 if (gs
->shader
->nir
) {
995 tu6_emit_link_map(cs
, vs
, gs
);
996 vertices_out
= gs
->shader
->nir
->info
.gs
.vertices_out
- 1;
997 output
= gl_primitive_to_tess(gs
->shader
->nir
->info
.gs
.output_primitive
);
998 invocations
= gs
->shader
->nir
->info
.gs
.invocations
- 1;
999 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1000 vec4_size
= gs
->shader
->nir
->info
.gs
.vertices_in
*
1001 DIV_ROUND_UP(vs
->shader
->output_size
, 4);
1004 output
= TESS_CW_TRIS
;
1009 uint32_t primitive_regid
=
1010 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
);
1011 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK_GS
, 1);
1012 tu_cs_emit(cs
, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc
) |
1013 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc
) |
1014 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage
.max_loc
));
1016 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9105
, 1);
1017 tu_cs_emit(cs
, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc
) | 0xff00);
1019 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_809C
, 1);
1020 tu_cs_emit(cs
, CONDREG(layer_regid
,
1021 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER
));
1023 uint32_t flags_regid
= ir3_find_output_regid(gs
,
1024 VARYING_SLOT_GS_VERTEX_FLAGS_IR3
);
1026 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL_GS
, 1);
1027 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage
.cnt
) |
1028 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid
));
1030 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_2
, 1);
1031 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage
.max_loc
) |
1032 CONDREG(pointsize_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE
) |
1033 CONDREG(layer_regid
, A6XX_PC_PRIMITIVE_CNTL_2_LAYER
) |
1034 CONDREG(primitive_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID
));
1036 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_5
, 1);
1038 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out
) |
1039 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output
) |
1040 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations
));
1042 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_3
, 1);
1045 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8003
, 1);
1048 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9100
, 1);
1049 tu_cs_emit(cs
, 0xff);
1051 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9102
, 1);
1052 tu_cs_emit(cs
, 0xffff00);
1054 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
1055 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size
));
1057 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 1);
1060 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_PRIM_SIZE
, 1);
1061 tu_cs_emit(cs
, vs
->shader
->output_size
);
1064 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
1065 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage
.cnt
));
1067 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
1068 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage
.max_loc
) |
1069 (last_shader
->writes_psize
? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
: 0));
1073 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
1075 uint8_t *interp_mode
,
1076 uint8_t *ps_repl_mode
)
1090 PS_REPL_ONE_MINUS_T
= 3,
1093 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
1095 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1096 * fourth component occupy three consecutive varying slots
1101 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
1102 if (compmask
& 0x1) {
1103 *ps_repl_mode
|= PS_REPL_S
<< shift
;
1106 if (compmask
& 0x2) {
1107 *ps_repl_mode
|= PS_REPL_T
<< shift
;
1110 if (compmask
& 0x4) {
1111 *interp_mode
|= INTERP_ZERO
<< shift
;
1114 if (compmask
& 0x8) {
1115 *interp_mode
|= INTERP_ONE
<< 6;
1118 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
1119 fs
->inputs
[index
].rasterflat
) {
1120 for (int i
= 0; i
< 4; i
++) {
1121 if (compmask
& (1 << i
)) {
1122 *interp_mode
|= INTERP_FLAT
<< shift
;
1132 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
1133 const struct ir3_shader_variant
*fs
)
1135 uint32_t interp_modes
[8] = { 0 };
1136 uint32_t ps_repl_modes
[8] = { 0 };
1140 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
1142 /* get the mode for input i */
1143 uint8_t interp_mode
;
1144 uint8_t ps_repl_mode
;
1146 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
1148 /* OR the mode into the array */
1149 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
1150 uint32_t n
= inloc
/ 32;
1151 uint32_t shift
= inloc
% 32;
1152 interp_modes
[n
] |= interp_mode
<< shift
;
1153 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
1154 if (shift
+ bits
> 32) {
1158 interp_modes
[n
] |= interp_mode
>> shift
;
1159 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
1164 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1165 tu_cs_emit_array(cs
, interp_modes
, 8);
1167 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1168 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
1172 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
1174 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
1175 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
1176 uint32_t smask_in_regid
;
1178 bool sample_shading
= fs
->per_samp
; /* TODO | key->sample_shading; */
1179 bool enable_varyings
= fs
->total_in
> 0;
1181 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
1182 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
1183 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
1184 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
1185 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
1186 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
1187 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
1188 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
1189 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
1191 if (fs
->num_sampler_prefetch
> 0) {
1192 assert(VALIDREG(ij_pix_regid
));
1193 /* also, it seems like ij_pix is *required* to be r0.x */
1194 assert(ij_pix_regid
== regid(0, 0));
1197 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
1198 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
1199 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1201 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1202 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1203 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
1204 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
1205 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
1206 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
1207 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
1208 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
1209 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
1212 if (fs
->num_sampler_prefetch
> 0) {
1213 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs
->num_sampler_prefetch
);
1214 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1215 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1217 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_bindless_id
) |
1218 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch
->tex_bindless_id
));
1222 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
1223 tu_cs_emit(cs
, 0x7);
1224 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
1225 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
1226 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
1227 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
1228 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
1229 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
1231 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
1232 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
1233 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
1235 tu_cs_emit(cs
, 0xfc);
1237 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
1238 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
1240 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
1242 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
1243 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
1244 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
1245 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
1246 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
1247 COND(fs
->fragcoord_compmask
!= 0, A6XX_GRAS_CNTL_SIZE
|
1248 A6XX_GRAS_CNTL_COORD_MASK(fs
->fragcoord_compmask
)) |
1249 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
1251 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
1253 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
1254 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
1255 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
1256 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
1257 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
1258 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
1259 COND(fs
->fragcoord_compmask
!= 0, A6XX_RB_RENDER_CONTROL0_SIZE
|
1260 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs
->fragcoord_compmask
)) |
1261 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
1263 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
1264 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
1265 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
1266 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
1268 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
1269 tu_cs_emit(cs
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
1271 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
1272 tu_cs_emit(cs
, COND(sample_shading
, 0x6)); // XXX
1274 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
1275 tu_cs_emit(cs
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
1279 tu6_emit_fs_outputs(struct tu_cs
*cs
,
1280 const struct ir3_shader_variant
*fs
,
1281 uint32_t mrt_count
, bool dual_src_blend
,
1282 uint32_t render_components
)
1284 uint32_t smask_regid
, posz_regid
;
1286 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
1287 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
1289 uint32_t fragdata_regid
[8];
1290 if (fs
->color0_mrt
) {
1291 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
1292 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1293 fragdata_regid
[i
] = fragdata_regid
[0];
1295 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1296 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
1299 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
1300 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
1301 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
1302 COND(dual_src_blend
, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE
) |
1304 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1306 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1307 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
1308 // TODO we could have a mix of half and full precision outputs,
1309 // we really need to figure out half-precision from IR3_REG_HALF
1310 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
1311 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
1315 A6XX_SP_FS_RENDER_COMPONENTS(.dword
= render_components
));
1317 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
1318 tu_cs_emit(cs
, COND(fs
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
) |
1319 COND(fs
->writes_smask
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK
) |
1320 COND(dual_src_blend
, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE
));
1321 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1324 A6XX_RB_RENDER_COMPONENTS(.dword
= render_components
));
1326 enum a6xx_ztest_mode zmode
;
1328 if (fs
->no_earlyz
|| fs
->has_kill
|| fs
->writes_pos
) {
1329 zmode
= A6XX_LATE_Z
;
1331 zmode
= A6XX_EARLY_Z
;
1334 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
1335 tu_cs_emit(cs
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode
));
1337 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
1338 tu_cs_emit(cs
, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode
));
1342 tu6_emit_geometry_consts(struct tu_cs
*cs
,
1343 const struct ir3_shader_variant
*vs
,
1344 const struct ir3_shader_variant
*gs
) {
1345 unsigned num_vertices
= gs
->shader
->nir
->info
.gs
.vertices_in
;
1347 uint32_t params
[4] = {
1348 vs
->shader
->output_size
* num_vertices
* 4, /* primitive stride */
1349 vs
->shader
->output_size
* 4, /* vertex stride */
1353 uint32_t vs_base
= vs
->shader
->const_state
.offsets
.primitive_param
;
1354 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, vs_base
, SB6_VS_SHADER
, 0,
1355 ARRAY_SIZE(params
), params
);
1357 uint32_t gs_base
= gs
->shader
->const_state
.offsets
.primitive_param
;
1358 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, gs_base
, SB6_GS_SHADER
, 0,
1359 ARRAY_SIZE(params
), params
);
1363 tu6_emit_program(struct tu_cs
*cs
,
1364 struct tu_pipeline_builder
*builder
,
1365 const struct tu_bo
*binary_bo
,
1367 struct tu_streamout_state
*tf
)
1369 const struct ir3_shader_variant
*vs
= builder
->variants
[MESA_SHADER_VERTEX
];
1370 const struct ir3_shader_variant
*bs
= builder
->binning_variant
;
1371 const struct ir3_shader_variant
*gs
= builder
->variants
[MESA_SHADER_GEOMETRY
];
1372 const struct ir3_shader_variant
*fs
= builder
->variants
[MESA_SHADER_FRAGMENT
];
1373 gl_shader_stage stage
= MESA_SHADER_VERTEX
;
1375 STATIC_ASSERT(MESA_SHADER_VERTEX
== 0);
1377 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
1378 tu_cs_emit(cs
, 0xff); /* XXX */
1380 /* Don't use the binning pass variant when GS is present because we don't
1381 * support compiling correct binning pass variants with GS.
1383 if (binning_pass
&& !gs
) {
1385 tu6_emit_xs_config(cs
, stage
, bs
,
1386 binary_bo
->iova
+ builder
->binning_vs_offset
);
1390 for (; stage
< ARRAY_SIZE(builder
->shaders
); stage
++) {
1391 const struct ir3_shader_variant
*xs
= builder
->variants
[stage
];
1393 if (stage
== MESA_SHADER_FRAGMENT
&& binning_pass
)
1396 tu6_emit_xs_config(cs
, stage
, xs
,
1397 binary_bo
->iova
+ builder
->shader_offsets
[stage
]);
1400 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
1403 tu6_emit_vpc(cs
, vs
, gs
, fs
, tf
);
1404 tu6_emit_vpc_varying_modes(cs
, fs
);
1407 tu6_emit_fs_inputs(cs
, fs
);
1408 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
,
1409 builder
->use_dual_src_blend
,
1410 builder
->render_components
);
1412 /* TODO: check if these can be skipped if fs is disabled */
1413 struct ir3_shader_variant dummy_variant
= {};
1414 tu6_emit_fs_inputs(cs
, &dummy_variant
);
1415 tu6_emit_fs_outputs(cs
, &dummy_variant
, builder
->color_attachment_count
,
1416 builder
->use_dual_src_blend
,
1417 builder
->render_components
);
1421 tu6_emit_geometry_consts(cs
, vs
, gs
);
1425 tu6_emit_vertex_input(struct tu_cs
*cs
,
1426 const struct ir3_shader_variant
*vs
,
1427 const VkPipelineVertexInputStateCreateInfo
*info
,
1428 uint32_t *bindings_used
)
1430 uint32_t vfd_decode_idx
= 0;
1431 uint32_t binding_instanced
= 0; /* bitmask of instanced bindings */
1433 for (uint32_t i
= 0; i
< info
->vertexBindingDescriptionCount
; i
++) {
1434 const VkVertexInputBindingDescription
*binding
=
1435 &info
->pVertexBindingDescriptions
[i
];
1438 A6XX_VFD_FETCH_STRIDE(binding
->binding
, binding
->stride
));
1440 if (binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1441 binding_instanced
|= 1 << binding
->binding
;
1443 *bindings_used
|= 1 << binding
->binding
;
1446 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1448 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
1449 const VkVertexInputAttributeDescription
*attr
=
1450 &info
->pVertexAttributeDescriptions
[i
];
1453 for (input_idx
= 0; input_idx
< vs
->inputs_count
; input_idx
++) {
1454 if ((vs
->inputs
[input_idx
].slot
- VERT_ATTRIB_GENERIC0
) == attr
->location
)
1458 /* attribute not used, skip it */
1459 if (input_idx
== vs
->inputs_count
)
1462 const struct tu_native_format format
= tu6_format_vtx(attr
->format
);
1464 A6XX_VFD_DECODE_INSTR(vfd_decode_idx
,
1465 .idx
= attr
->binding
,
1466 .offset
= attr
->offset
,
1467 .instanced
= binding_instanced
& (1 << attr
->binding
),
1468 .format
= format
.fmt
,
1469 .swap
= format
.swap
,
1471 ._float
= !vk_format_is_int(attr
->format
)),
1472 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx
, 1));
1475 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx
,
1476 .writemask
= vs
->inputs
[input_idx
].compmask
,
1477 .regid
= vs
->inputs
[input_idx
].regid
));
1484 .fetch_cnt
= vfd_decode_idx
, /* decode_cnt for binning pass ? */
1485 .decode_cnt
= vfd_decode_idx
));
1489 tu6_guardband_adj(uint32_t v
)
1492 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1498 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1502 scales
[0] = viewport
->width
/ 2.0f
;
1503 scales
[1] = viewport
->height
/ 2.0f
;
1504 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1505 offsets
[0] = viewport
->x
+ scales
[0];
1506 offsets
[1] = viewport
->y
+ scales
[1];
1507 offsets
[2] = viewport
->minDepth
;
1511 min
.x
= (int32_t) viewport
->x
;
1512 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1513 if (viewport
->height
>= 0.0f
) {
1514 min
.y
= (int32_t) viewport
->y
;
1515 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1517 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1518 max
.y
= (int32_t) ceilf(viewport
->y
);
1520 /* the spec allows viewport->height to be 0.0f */
1523 assert(min
.x
>= 0 && min
.x
< max
.x
);
1524 assert(min
.y
>= 0 && min
.y
< max
.y
);
1526 VkExtent2D guardband_adj
;
1527 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1528 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1530 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
1531 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets
[0]).value
);
1532 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XSCALE_0(scales
[0]).value
);
1533 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets
[1]).value
);
1534 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YSCALE_0(scales
[1]).value
);
1535 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets
[2]).value
);
1536 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales
[2]).value
);
1538 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
1539 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min
.x
) |
1540 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min
.y
));
1541 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max
.x
- 1) |
1542 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max
.y
- 1));
1544 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1546 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1547 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1549 float z_clamp_min
= MIN2(viewport
->minDepth
, viewport
->maxDepth
);
1550 float z_clamp_max
= MAX2(viewport
->minDepth
, viewport
->maxDepth
);
1553 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min
),
1554 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max
));
1557 A6XX_RB_Z_CLAMP_MIN(z_clamp_min
),
1558 A6XX_RB_Z_CLAMP_MAX(z_clamp_max
));
1562 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1564 const VkOffset2D min
= scissor
->offset
;
1565 const VkOffset2D max
= {
1566 scissor
->offset
.x
+ scissor
->extent
.width
,
1567 scissor
->offset
.y
+ scissor
->extent
.height
,
1570 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
1571 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min
.x
) |
1572 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min
.y
));
1573 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max
.x
- 1) |
1574 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max
.y
- 1));
1578 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
)
1581 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 1);
1584 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 1);
1587 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 1);
1592 assert(samp_loc
->sampleLocationsPerPixel
== samp_loc
->sampleLocationsCount
);
1593 assert(samp_loc
->sampleLocationGridSize
.width
== 1);
1594 assert(samp_loc
->sampleLocationGridSize
.height
== 1);
1596 uint32_t sample_config
=
1597 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE
;
1598 uint32_t sample_locations
= 0;
1599 for (uint32_t i
= 0; i
< samp_loc
->sampleLocationsCount
; i
++) {
1601 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc
->pSampleLocations
[i
].x
) |
1602 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc
->pSampleLocations
[i
].y
)) << i
*8;
1605 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 2);
1606 tu_cs_emit(cs
, sample_config
);
1607 tu_cs_emit(cs
, sample_locations
);
1609 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 2);
1610 tu_cs_emit(cs
, sample_config
);
1611 tu_cs_emit(cs
, sample_locations
);
1613 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 2);
1614 tu_cs_emit(cs
, sample_config
);
1615 tu_cs_emit(cs
, sample_locations
);
1619 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1620 VkSampleCountFlagBits samples
)
1622 uint32_t gras_su_cntl
= 0;
1624 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1625 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1626 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1627 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1629 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1630 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1632 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1634 if (rast_info
->depthBiasEnable
)
1635 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1637 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1638 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1640 return gras_su_cntl
;
1644 tu6_emit_depth_bias(struct tu_cs
*cs
,
1645 float constant_factor
,
1649 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1650 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
).value
);
1651 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
).value
);
1652 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
).value
);
1656 tu6_emit_depth_control(struct tu_cs
*cs
,
1657 const VkPipelineDepthStencilStateCreateInfo
*ds_info
,
1658 const VkPipelineRasterizationStateCreateInfo
*rast_info
)
1660 assert(!ds_info
->depthBoundsTestEnable
);
1662 uint32_t rb_depth_cntl
= 0;
1663 if (ds_info
->depthTestEnable
) {
1665 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1666 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1667 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1669 if (rast_info
->depthClampEnable
)
1670 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE
;
1672 if (ds_info
->depthWriteEnable
)
1673 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1676 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1677 tu_cs_emit(cs
, rb_depth_cntl
);
1681 tu6_emit_stencil_control(struct tu_cs
*cs
,
1682 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1684 uint32_t rb_stencil_control
= 0;
1685 if (ds_info
->stencilTestEnable
) {
1686 const VkStencilOpState
*front
= &ds_info
->front
;
1687 const VkStencilOpState
*back
= &ds_info
->back
;
1688 rb_stencil_control
|=
1689 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1690 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1691 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1692 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1693 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1694 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1695 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1696 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1697 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1698 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1699 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1702 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1703 tu_cs_emit(cs
, rb_stencil_control
);
1707 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1710 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1711 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1712 has_alpha
? att
->srcColorBlendFactor
1713 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1714 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1715 has_alpha
? att
->dstColorBlendFactor
1716 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1717 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1718 const enum adreno_rb_blend_factor src_alpha_factor
=
1719 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1720 const enum adreno_rb_blend_factor dst_alpha_factor
=
1721 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1723 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1724 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1725 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1726 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1727 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1728 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1732 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1733 uint32_t rb_mrt_control_rop
,
1737 uint32_t rb_mrt_control
=
1738 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1740 /* ignore blending and logic op for integer attachments */
1742 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1743 return rb_mrt_control
;
1746 rb_mrt_control
|= rb_mrt_control_rop
;
1748 if (att
->blendEnable
) {
1749 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1752 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1755 return rb_mrt_control
;
1759 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1760 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1761 const VkFormat attachment_formats
[MAX_RTS
],
1762 uint32_t *blend_enable_mask
)
1764 *blend_enable_mask
= 0;
1766 bool rop_reads_dst
= false;
1767 uint32_t rb_mrt_control_rop
= 0;
1768 if (blend_info
->logicOpEnable
) {
1769 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1770 rb_mrt_control_rop
=
1771 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1772 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1775 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
1776 const VkPipelineColorBlendAttachmentState
*att
=
1777 &blend_info
->pAttachments
[i
];
1778 const VkFormat format
= attachment_formats
[i
];
1780 uint32_t rb_mrt_control
= 0;
1781 uint32_t rb_mrt_blend_control
= 0;
1782 if (format
!= VK_FORMAT_UNDEFINED
) {
1783 const bool is_int
= vk_format_is_int(format
);
1784 const bool has_alpha
= vk_format_has_alpha(format
);
1787 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
1788 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
1790 if (att
->blendEnable
|| rop_reads_dst
)
1791 *blend_enable_mask
|= 1 << i
;
1794 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1795 tu_cs_emit(cs
, rb_mrt_control
);
1796 tu_cs_emit(cs
, rb_mrt_blend_control
);
1801 tu6_emit_blend_control(struct tu_cs
*cs
,
1802 uint32_t blend_enable_mask
,
1803 bool dual_src_blend
,
1804 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
1806 const uint32_t sample_mask
=
1807 msaa_info
->pSampleMask
? (*msaa_info
->pSampleMask
& 0xffff)
1808 : ((1 << msaa_info
->rasterizationSamples
) - 1);
1811 A6XX_SP_BLEND_CNTL(.enabled
= blend_enable_mask
,
1812 .dual_color_in_enable
= dual_src_blend
,
1813 .alpha_to_coverage
= msaa_info
->alphaToCoverageEnable
,
1816 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1818 A6XX_RB_BLEND_CNTL(.enable_blend
= blend_enable_mask
,
1819 .independent_blend
= true,
1820 .sample_mask
= sample_mask
,
1821 .dual_color_in_enable
= dual_src_blend
,
1822 .alpha_to_coverage
= msaa_info
->alphaToCoverageEnable
,
1823 .alpha_to_one
= msaa_info
->alphaToOneEnable
));
1827 tu_pipeline_create(struct tu_device
*dev
,
1828 struct tu_pipeline_layout
*layout
,
1830 const VkAllocationCallbacks
*pAllocator
,
1831 struct tu_pipeline
**out_pipeline
)
1833 struct tu_pipeline
*pipeline
=
1834 vk_zalloc2(&dev
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1835 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1837 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1839 tu_cs_init(&pipeline
->cs
, dev
, TU_CS_MODE_SUB_STREAM
, 2048);
1841 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1842 * that LOAD_STATE can potentially take up a large amount of space so we
1843 * calculate its size explicitly.
1845 unsigned load_state_size
= tu6_load_state_size(layout
, compute
);
1846 VkResult result
= tu_cs_reserve_space(&pipeline
->cs
, 2048 + load_state_size
);
1847 if (result
!= VK_SUCCESS
) {
1848 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
1852 *out_pipeline
= pipeline
;
1858 tu_pipeline_shader_key_init(struct ir3_shader_key
*key
,
1859 const VkGraphicsPipelineCreateInfo
*pipeline_info
)
1861 bool has_gs
= false;
1863 if (pipeline_info
) {
1864 for (uint32_t i
= 0; i
< pipeline_info
->stageCount
; i
++) {
1865 if (pipeline_info
->pStages
[i
].stage
== VK_SHADER_STAGE_GEOMETRY_BIT
) {
1871 const VkPipelineMultisampleStateCreateInfo
*msaa_info
= pipeline_info
->pMultisampleState
;
1872 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
1873 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1874 if (!pipeline_info
->pRasterizationState
->rasterizerDiscardEnable
&&
1875 (msaa_info
->rasterizationSamples
> 1 ||
1876 /* also set msaa key when sample location is not the default
1877 * since this affects varying interpolation */
1878 (sample_locations
&& sample_locations
->sampleLocationsEnable
))) {
1883 /* TODO: Populate the remaining fields of ir3_shader_key. */
1884 *key
= (struct ir3_shader_key
) {
1891 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
)
1893 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
1896 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1897 gl_shader_stage stage
=
1898 vk_to_mesa_shader_stage(builder
->create_info
->pStages
[i
].stage
);
1899 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
1902 struct ir3_shader_key key
;
1903 tu_pipeline_shader_key_init(&key
, builder
->create_info
);
1905 for (gl_shader_stage stage
= MESA_SHADER_VERTEX
;
1906 stage
< MESA_SHADER_STAGES
; stage
++) {
1907 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
1908 if (!stage_info
&& stage
!= MESA_SHADER_FRAGMENT
)
1911 struct tu_shader
*shader
=
1912 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->layout
,
1915 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1917 builder
->shaders
[stage
] = shader
;
1920 for (gl_shader_stage stage
= MESA_SHADER_STAGES
- 1;
1921 stage
> MESA_SHADER_NONE
; stage
--) {
1922 if (!builder
->shaders
[stage
])
1926 builder
->variants
[stage
] =
1927 ir3_shader_get_variant(builder
->shaders
[stage
]->ir3_shader
,
1928 &key
, false, &created
);
1929 if (!builder
->variants
[stage
])
1930 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1932 builder
->shader_offsets
[stage
] = builder
->shader_total_size
;
1933 builder
->shader_total_size
+=
1934 sizeof(uint32_t) * builder
->variants
[stage
]->info
.sizedwords
;
1937 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1938 struct ir3_shader_variant
*variant
;
1940 if (vs
->ir3_shader
->stream_output
.num_outputs
) {
1941 variant
= builder
->variants
[MESA_SHADER_VERTEX
];
1944 variant
= ir3_shader_get_variant(vs
->ir3_shader
, &key
,
1947 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1950 builder
->binning_vs_offset
= builder
->shader_total_size
;
1951 builder
->shader_total_size
+=
1952 sizeof(uint32_t) * variant
->info
.sizedwords
;
1953 builder
->binning_variant
= variant
;
1959 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder
*builder
,
1960 struct tu_pipeline
*pipeline
)
1962 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
1965 tu_bo_init_new(builder
->device
, bo
, builder
->shader_total_size
);
1966 if (result
!= VK_SUCCESS
)
1969 result
= tu_bo_map(builder
->device
, bo
);
1970 if (result
!= VK_SUCCESS
)
1973 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1974 const struct ir3_shader_variant
*variant
= builder
->variants
[i
];
1978 memcpy(bo
->map
+ builder
->shader_offsets
[i
], variant
->bin
,
1979 sizeof(uint32_t) * variant
->info
.sizedwords
);
1982 if (builder
->binning_variant
) {
1983 const struct ir3_shader_variant
*variant
= builder
->binning_variant
;
1984 memcpy(bo
->map
+ builder
->binning_vs_offset
, variant
->bin
,
1985 sizeof(uint32_t) * variant
->info
.sizedwords
);
1992 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
1993 struct tu_pipeline
*pipeline
)
1995 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
1996 builder
->create_info
->pDynamicState
;
2001 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
2002 VkDynamicState state
= dynamic_info
->pDynamicStates
[i
];
2004 case VK_DYNAMIC_STATE_VIEWPORT
... VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2005 pipeline
->dynamic_state_mask
|= BIT(state
);
2007 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
2008 pipeline
->dynamic_state_mask
|= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
);
2011 assert(!"unsupported dynamic state");
2018 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage
*link
,
2019 struct tu_shader
*shader
,
2020 struct ir3_shader_variant
*v
)
2022 link
->ubo_state
= v
->shader
->ubo_state
;
2023 link
->const_state
= v
->shader
->const_state
;
2024 link
->constlen
= v
->constlen
;
2025 link
->push_consts
= shader
->push_consts
;
2029 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
2030 struct tu_pipeline
*pipeline
)
2032 struct tu_cs prog_cs
;
2033 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2034 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, false, &pipeline
->streamout
);
2035 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2037 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2038 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, true, &pipeline
->streamout
);
2039 pipeline
->program
.binning_state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2041 VkShaderStageFlags stages
= 0;
2042 for (unsigned i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
2043 stages
|= builder
->create_info
->pStages
[i
].stage
;
2045 pipeline
->active_stages
= stages
;
2047 uint32_t desc_sets
= 0;
2048 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2049 if (!builder
->shaders
[i
])
2052 tu_pipeline_set_linkage(&pipeline
->program
.link
[i
],
2053 builder
->shaders
[i
],
2054 builder
->variants
[i
]);
2055 desc_sets
|= builder
->shaders
[i
]->active_desc_sets
;
2057 pipeline
->active_desc_sets
= desc_sets
;
2059 if (builder
->shaders
[MESA_SHADER_FRAGMENT
]) {
2060 memcpy(pipeline
->program
.input_attachment_idx
,
2061 builder
->shaders
[MESA_SHADER_FRAGMENT
]->attachment_idx
,
2062 sizeof(pipeline
->program
.input_attachment_idx
));
2067 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
2068 struct tu_pipeline
*pipeline
)
2070 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
2071 builder
->create_info
->pVertexInputState
;
2072 const struct ir3_shader_variant
*vs
= builder
->variants
[MESA_SHADER_VERTEX
];
2073 const struct ir3_shader_variant
*bs
= builder
->binning_variant
;
2076 tu_cs_begin_sub_stream(&pipeline
->cs
,
2077 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2078 tu6_emit_vertex_input(&vi_cs
, vs
, vi_info
,
2079 &pipeline
->vi
.bindings_used
);
2080 pipeline
->vi
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
2083 tu_cs_begin_sub_stream(&pipeline
->cs
,
2084 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2085 tu6_emit_vertex_input(
2086 &vi_cs
, bs
, vi_info
, &pipeline
->vi
.bindings_used
);
2087 pipeline
->vi
.binning_state_ib
=
2088 tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
2093 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
2094 struct tu_pipeline
*pipeline
)
2096 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
2097 builder
->create_info
->pInputAssemblyState
;
2099 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
2100 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
2104 tu_pipeline_static_state(struct tu_pipeline
*pipeline
, struct tu_cs
*cs
,
2105 uint32_t id
, uint32_t size
)
2107 struct ts_cs_memory memory
;
2109 if (pipeline
->dynamic_state_mask
& BIT(id
))
2112 /* TODO: share this logc with tu_cmd_dynamic_state */
2113 tu_cs_alloc(&pipeline
->cs
, size
, 1, &memory
);
2114 tu_cs_init_external(cs
, memory
.map
, memory
.map
+ size
);
2116 tu_cs_reserve_space(cs
, size
);
2118 assert(id
< ARRAY_SIZE(pipeline
->dynamic_state
));
2119 pipeline
->dynamic_state
[id
].iova
= memory
.iova
;
2120 pipeline
->dynamic_state
[id
].size
= size
;
2125 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
2126 struct tu_pipeline
*pipeline
)
2130 * pViewportState is a pointer to an instance of the
2131 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2132 * pipeline has rasterization disabled."
2134 * We leave the relevant registers stale in that case.
2136 if (builder
->rasterizer_discard
)
2139 const VkPipelineViewportStateCreateInfo
*vp_info
=
2140 builder
->create_info
->pViewportState
;
2144 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_VIEWPORT
, 18))
2145 tu6_emit_viewport(&cs
, vp_info
->pViewports
);
2147 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_SCISSOR
, 3))
2148 tu6_emit_scissor(&cs
, vp_info
->pScissors
);
2152 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
2153 struct tu_pipeline
*pipeline
)
2155 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
2156 builder
->create_info
->pRasterizationState
;
2158 assert(rast_info
->polygonMode
== VK_POLYGON_MODE_FILL
);
2161 tu_cs_begin_sub_stream(&pipeline
->cs
, 7, &cs
);
2163 tu_cs_emit_regs(&cs
,
2165 .znear_clip_disable
= rast_info
->depthClampEnable
,
2166 .zfar_clip_disable
= rast_info
->depthClampEnable
,
2167 .unk5
= rast_info
->depthClampEnable
,
2168 .zero_gb_scale_z
= 1,
2169 .vp_clip_code_ignore
= 1));
2170 /* move to hw ctx init? */
2171 tu_cs_emit_regs(&cs
, A6XX_GRAS_UNKNOWN_8001());
2172 tu_cs_emit_regs(&cs
,
2173 A6XX_GRAS_SU_POINT_MINMAX(.min
= 1.0f
/ 16.0f
, .max
= 4092.0f
),
2174 A6XX_GRAS_SU_POINT_SIZE(1.0f
));
2176 pipeline
->rast
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &cs
);
2178 pipeline
->gras_su_cntl
=
2179 tu6_gras_su_cntl(rast_info
, builder
->samples
);
2181 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2)) {
2182 pipeline
->gras_su_cntl
|=
2183 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info
->lineWidth
/ 2.0f
);
2184 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= pipeline
->gras_su_cntl
));
2187 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4)) {
2188 tu6_emit_depth_bias(&cs
, rast_info
->depthBiasConstantFactor
,
2189 rast_info
->depthBiasClamp
,
2190 rast_info
->depthBiasSlopeFactor
);
2196 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
2197 struct tu_pipeline
*pipeline
)
2201 * pDepthStencilState is a pointer to an instance of the
2202 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2203 * the pipeline has rasterization disabled or if the subpass of the
2204 * render pass the pipeline is created against does not use a
2205 * depth/stencil attachment.
2207 * Disable both depth and stencil tests if there is no ds attachment,
2208 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2209 * only the separate stencil attachment
2211 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
2212 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
2213 builder
->depth_attachment_format
!= VK_FORMAT_UNDEFINED
2214 ? builder
->create_info
->pDepthStencilState
2216 const VkPipelineDepthStencilStateCreateInfo
*ds_info_depth
=
2217 builder
->depth_attachment_format
!= VK_FORMAT_S8_UINT
2218 ? ds_info
: &dummy_ds_info
;
2221 tu_cs_begin_sub_stream(&pipeline
->cs
, 6, &cs
);
2223 /* move to hw ctx init? */
2224 tu_cs_emit_regs(&cs
, A6XX_RB_ALPHA_CONTROL());
2225 tu6_emit_depth_control(&cs
, ds_info_depth
,
2226 builder
->create_info
->pRasterizationState
);
2227 tu6_emit_stencil_control(&cs
, ds_info
);
2229 pipeline
->ds
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &cs
);
2231 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2)) {
2232 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.mask
= ds_info
->front
.compareMask
& 0xff,
2233 .bfmask
= ds_info
->back
.compareMask
& 0xff));
2236 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2)) {
2237 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.wrmask
= ds_info
->front
.writeMask
& 0xff,
2238 .bfwrmask
= ds_info
->back
.writeMask
& 0xff));
2241 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2)) {
2242 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.ref
= ds_info
->front
.reference
& 0xff,
2243 .bfref
= ds_info
->back
.reference
& 0xff));
2248 tu_pipeline_builder_parse_multisample_and_color_blend(
2249 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
2253 * pMultisampleState is a pointer to an instance of the
2254 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2255 * has rasterization disabled.
2259 * pColorBlendState is a pointer to an instance of the
2260 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2261 * pipeline has rasterization disabled or if the subpass of the render
2262 * pass the pipeline is created against does not use any color
2265 * We leave the relevant registers stale when rasterization is disabled.
2267 if (builder
->rasterizer_discard
)
2270 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
2271 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
2272 builder
->create_info
->pMultisampleState
;
2273 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
2274 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
2275 : &dummy_blend_info
;
2278 tu_cs_begin_sub_stream(&pipeline
->cs
, MAX_RTS
* 3 + 4, &cs
);
2280 uint32_t blend_enable_mask
;
2281 tu6_emit_rb_mrt_controls(&cs
, blend_info
,
2282 builder
->color_attachment_formats
,
2283 &blend_enable_mask
);
2285 tu6_emit_blend_control(&cs
, blend_enable_mask
,
2286 builder
->use_dual_src_blend
, msaa_info
);
2288 pipeline
->blend
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &cs
);
2290 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5)) {
2291 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2292 tu_cs_emit_array(&cs
, (const uint32_t *) blend_info
->blendConstants
, 4);
2295 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
2296 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
2297 const VkSampleLocationsInfoEXT
*samp_loc
= NULL
;
2299 if (sample_locations
&& sample_locations
->sampleLocationsEnable
)
2300 samp_loc
= &sample_locations
->sampleLocationsInfo
;
2302 if (tu_pipeline_static_state(pipeline
, &cs
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
,
2303 samp_loc
? 9 : 6)) {
2304 tu6_emit_sample_locations(&cs
, samp_loc
);
2309 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
2310 struct tu_device
*dev
,
2311 const VkAllocationCallbacks
*alloc
)
2313 tu_cs_finish(&pipeline
->cs
);
2315 if (pipeline
->program
.binary_bo
.gem_handle
)
2316 tu_bo_finish(dev
, &pipeline
->program
.binary_bo
);
2320 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
2321 struct tu_pipeline
**pipeline
)
2323 VkResult result
= tu_pipeline_create(builder
->device
, builder
->layout
,
2324 false, builder
->alloc
, pipeline
);
2325 if (result
!= VK_SUCCESS
)
2328 (*pipeline
)->layout
= builder
->layout
;
2330 /* compile and upload shaders */
2331 result
= tu_pipeline_builder_compile_shaders(builder
);
2332 if (result
== VK_SUCCESS
)
2333 result
= tu_pipeline_builder_upload_shaders(builder
, *pipeline
);
2334 if (result
!= VK_SUCCESS
) {
2335 tu_pipeline_finish(*pipeline
, builder
->device
, builder
->alloc
);
2336 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
2337 *pipeline
= VK_NULL_HANDLE
;
2342 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
2343 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
2344 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
2345 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
2346 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
2347 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
2348 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
2349 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
2350 tu6_emit_load_state(*pipeline
, false);
2352 /* we should have reserved enough space upfront such that the CS never
2355 assert((*pipeline
)->cs
.bo_count
== 1);
2361 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
2363 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2364 if (!builder
->shaders
[i
])
2366 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
2371 tu_pipeline_builder_init_graphics(
2372 struct tu_pipeline_builder
*builder
,
2373 struct tu_device
*dev
,
2374 struct tu_pipeline_cache
*cache
,
2375 const VkGraphicsPipelineCreateInfo
*create_info
,
2376 const VkAllocationCallbacks
*alloc
)
2378 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, create_info
->layout
);
2380 *builder
= (struct tu_pipeline_builder
) {
2383 .create_info
= create_info
,
2388 builder
->rasterizer_discard
=
2389 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
2391 if (builder
->rasterizer_discard
) {
2392 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
2394 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
2396 const struct tu_render_pass
*pass
=
2397 tu_render_pass_from_handle(create_info
->renderPass
);
2398 const struct tu_subpass
*subpass
=
2399 &pass
->subpasses
[create_info
->subpass
];
2401 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
2402 builder
->depth_attachment_format
= (a
!= VK_ATTACHMENT_UNUSED
) ?
2403 pass
->attachments
[a
].format
: VK_FORMAT_UNDEFINED
;
2405 assert(subpass
->color_count
== 0 ||
2406 !create_info
->pColorBlendState
||
2407 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
2408 builder
->color_attachment_count
= subpass
->color_count
;
2409 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
2410 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
2411 if (a
== VK_ATTACHMENT_UNUSED
)
2414 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
2415 builder
->use_color_attachments
= true;
2416 builder
->render_components
|= 0xf << (i
* 4);
2419 if (tu_blend_state_is_dual_src(create_info
->pColorBlendState
)) {
2420 builder
->color_attachment_count
++;
2421 builder
->use_dual_src_blend
= true;
2422 /* dual source blending has an extra fs output in the 2nd slot */
2423 if (subpass
->color_attachments
[0].attachment
!= VK_ATTACHMENT_UNUSED
)
2424 builder
->render_components
|= 0xf << 4;
2430 tu_graphics_pipeline_create(VkDevice device
,
2431 VkPipelineCache pipelineCache
,
2432 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2433 const VkAllocationCallbacks
*pAllocator
,
2434 VkPipeline
*pPipeline
)
2436 TU_FROM_HANDLE(tu_device
, dev
, device
);
2437 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
2439 struct tu_pipeline_builder builder
;
2440 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
2441 pCreateInfo
, pAllocator
);
2443 struct tu_pipeline
*pipeline
= NULL
;
2444 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
2445 tu_pipeline_builder_finish(&builder
);
2447 if (result
== VK_SUCCESS
)
2448 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2450 *pPipeline
= VK_NULL_HANDLE
;
2456 tu_CreateGraphicsPipelines(VkDevice device
,
2457 VkPipelineCache pipelineCache
,
2459 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
2460 const VkAllocationCallbacks
*pAllocator
,
2461 VkPipeline
*pPipelines
)
2463 VkResult final_result
= VK_SUCCESS
;
2465 for (uint32_t i
= 0; i
< count
; i
++) {
2466 VkResult result
= tu_graphics_pipeline_create(device
, pipelineCache
,
2467 &pCreateInfos
[i
], pAllocator
,
2470 if (result
!= VK_SUCCESS
)
2471 final_result
= result
;
2474 return final_result
;
2478 tu_compute_upload_shader(VkDevice device
,
2479 struct tu_pipeline
*pipeline
,
2480 struct ir3_shader_variant
*v
)
2482 TU_FROM_HANDLE(tu_device
, dev
, device
);
2483 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
2485 uint32_t shader_size
= sizeof(uint32_t) * v
->info
.sizedwords
;
2487 tu_bo_init_new(dev
, bo
, shader_size
);
2488 if (result
!= VK_SUCCESS
)
2491 result
= tu_bo_map(dev
, bo
);
2492 if (result
!= VK_SUCCESS
)
2495 memcpy(bo
->map
, v
->bin
, shader_size
);
2502 tu_compute_pipeline_create(VkDevice device
,
2503 VkPipelineCache _cache
,
2504 const VkComputePipelineCreateInfo
*pCreateInfo
,
2505 const VkAllocationCallbacks
*pAllocator
,
2506 VkPipeline
*pPipeline
)
2508 TU_FROM_HANDLE(tu_device
, dev
, device
);
2509 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, pCreateInfo
->layout
);
2510 const VkPipelineShaderStageCreateInfo
*stage_info
= &pCreateInfo
->stage
;
2513 struct tu_pipeline
*pipeline
;
2515 *pPipeline
= VK_NULL_HANDLE
;
2517 result
= tu_pipeline_create(dev
, layout
, true, pAllocator
, &pipeline
);
2518 if (result
!= VK_SUCCESS
)
2521 pipeline
->layout
= layout
;
2523 struct ir3_shader_key key
;
2524 tu_pipeline_shader_key_init(&key
, NULL
);
2526 struct tu_shader
*shader
=
2527 tu_shader_create(dev
, MESA_SHADER_COMPUTE
, stage_info
, layout
, pAllocator
);
2529 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2534 struct ir3_shader_variant
*v
=
2535 ir3_shader_get_variant(shader
->ir3_shader
, &key
, false, &created
);
2539 tu_pipeline_set_linkage(&pipeline
->program
.link
[MESA_SHADER_COMPUTE
],
2542 result
= tu_compute_upload_shader(device
, pipeline
, v
);
2543 if (result
!= VK_SUCCESS
)
2546 for (int i
= 0; i
< 3; i
++)
2547 pipeline
->compute
.local_size
[i
] = v
->shader
->nir
->info
.cs
.local_size
[i
];
2549 struct tu_cs prog_cs
;
2550 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2551 tu6_emit_cs_config(&prog_cs
, shader
, v
, pipeline
->program
.binary_bo
.iova
);
2552 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2554 tu6_emit_load_state(pipeline
, true);
2556 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2561 tu_shader_destroy(dev
, shader
, pAllocator
);
2563 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2564 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
2570 tu_CreateComputePipelines(VkDevice device
,
2571 VkPipelineCache pipelineCache
,
2573 const VkComputePipelineCreateInfo
*pCreateInfos
,
2574 const VkAllocationCallbacks
*pAllocator
,
2575 VkPipeline
*pPipelines
)
2577 VkResult final_result
= VK_SUCCESS
;
2579 for (uint32_t i
= 0; i
< count
; i
++) {
2580 VkResult result
= tu_compute_pipeline_create(device
, pipelineCache
,
2582 pAllocator
, &pPipelines
[i
]);
2583 if (result
!= VK_SUCCESS
)
2584 final_result
= result
;
2587 return final_result
;
2591 tu_DestroyPipeline(VkDevice _device
,
2592 VkPipeline _pipeline
,
2593 const VkAllocationCallbacks
*pAllocator
)
2595 TU_FROM_HANDLE(tu_device
, dev
, _device
);
2596 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2601 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2602 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);