2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "main/menums.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
42 struct tu_pipeline_builder
44 struct tu_device
*device
;
45 struct tu_pipeline_cache
*cache
;
46 const VkAllocationCallbacks
*alloc
;
47 const VkGraphicsPipelineCreateInfo
*create_info
;
49 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
50 uint32_t shader_offsets
[MESA_SHADER_STAGES
];
51 uint32_t binning_vs_offset
;
52 uint32_t shader_total_size
;
54 bool rasterizer_discard
;
55 /* these states are affectd by rasterizer_discard */
56 VkSampleCountFlagBits samples
;
57 bool use_depth_stencil_attachment
;
58 bool use_color_attachments
;
59 uint32_t color_attachment_count
;
60 VkFormat color_attachment_formats
[MAX_RTS
];
63 static enum tu_dynamic_state_bits
64 tu_dynamic_state_bit(VkDynamicState state
)
67 case VK_DYNAMIC_STATE_VIEWPORT
:
68 return TU_DYNAMIC_VIEWPORT
;
69 case VK_DYNAMIC_STATE_SCISSOR
:
70 return TU_DYNAMIC_SCISSOR
;
71 case VK_DYNAMIC_STATE_LINE_WIDTH
:
72 return TU_DYNAMIC_LINE_WIDTH
;
73 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
74 return TU_DYNAMIC_DEPTH_BIAS
;
75 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
76 return TU_DYNAMIC_BLEND_CONSTANTS
;
77 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
78 return TU_DYNAMIC_DEPTH_BOUNDS
;
79 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
80 return TU_DYNAMIC_STENCIL_COMPARE_MASK
;
81 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
82 return TU_DYNAMIC_STENCIL_WRITE_MASK
;
83 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
84 return TU_DYNAMIC_STENCIL_REFERENCE
;
86 unreachable("invalid dynamic state");
91 static gl_shader_stage
92 tu_shader_stage(VkShaderStageFlagBits stage
)
95 case VK_SHADER_STAGE_VERTEX_BIT
:
96 return MESA_SHADER_VERTEX
;
97 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
98 return MESA_SHADER_TESS_CTRL
;
99 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
100 return MESA_SHADER_TESS_EVAL
;
101 case VK_SHADER_STAGE_GEOMETRY_BIT
:
102 return MESA_SHADER_GEOMETRY
;
103 case VK_SHADER_STAGE_FRAGMENT_BIT
:
104 return MESA_SHADER_FRAGMENT
;
105 case VK_SHADER_STAGE_COMPUTE_BIT
:
106 return MESA_SHADER_COMPUTE
;
108 unreachable("invalid VkShaderStageFlagBits");
109 return MESA_SHADER_NONE
;
113 static const VkVertexInputAttributeDescription
*
114 tu_find_vertex_input_attribute(
115 const VkPipelineVertexInputStateCreateInfo
*vi_info
, uint32_t slot
)
117 assert(slot
>= VERT_ATTRIB_GENERIC0
);
118 slot
-= VERT_ATTRIB_GENERIC0
;
119 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
120 if (vi_info
->pVertexAttributeDescriptions
[i
].location
== slot
)
121 return &vi_info
->pVertexAttributeDescriptions
[i
];
126 static const VkVertexInputBindingDescription
*
127 tu_find_vertex_input_binding(
128 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
129 const VkVertexInputAttributeDescription
*vi_attr
)
132 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
133 if (vi_info
->pVertexBindingDescriptions
[i
].binding
== vi_attr
->binding
)
134 return &vi_info
->pVertexBindingDescriptions
[i
];
140 tu_logic_op_reads_dst(VkLogicOp op
)
143 case VK_LOGIC_OP_CLEAR
:
144 case VK_LOGIC_OP_COPY
:
145 case VK_LOGIC_OP_COPY_INVERTED
:
146 case VK_LOGIC_OP_SET
:
154 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
156 /* treat dst alpha as 1.0 and avoid reading it */
158 case VK_BLEND_FACTOR_DST_ALPHA
:
159 return VK_BLEND_FACTOR_ONE
;
160 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
161 return VK_BLEND_FACTOR_ZERO
;
167 static enum pc_di_primtype
168 tu6_primtype(VkPrimitiveTopology topology
)
171 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
172 return DI_PT_POINTLIST
;
173 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
174 return DI_PT_LINELIST
;
175 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
176 return DI_PT_LINESTRIP
;
177 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
178 return DI_PT_TRILIST
;
179 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
180 return DI_PT_TRISTRIP
;
181 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
184 return DI_PT_LINE_ADJ
;
185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
186 return DI_PT_LINESTRIP_ADJ
;
187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
188 return DI_PT_TRI_ADJ
;
189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
190 return DI_PT_TRISTRIP_ADJ
;
191 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
193 unreachable("invalid primitive topology");
198 static enum adreno_compare_func
199 tu6_compare_func(VkCompareOp op
)
202 case VK_COMPARE_OP_NEVER
:
204 case VK_COMPARE_OP_LESS
:
206 case VK_COMPARE_OP_EQUAL
:
208 case VK_COMPARE_OP_LESS_OR_EQUAL
:
210 case VK_COMPARE_OP_GREATER
:
212 case VK_COMPARE_OP_NOT_EQUAL
:
213 return FUNC_NOTEQUAL
;
214 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
216 case VK_COMPARE_OP_ALWAYS
:
219 unreachable("invalid VkCompareOp");
224 static enum adreno_stencil_op
225 tu6_stencil_op(VkStencilOp op
)
228 case VK_STENCIL_OP_KEEP
:
230 case VK_STENCIL_OP_ZERO
:
232 case VK_STENCIL_OP_REPLACE
:
233 return STENCIL_REPLACE
;
234 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
235 return STENCIL_INCR_CLAMP
;
236 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
237 return STENCIL_DECR_CLAMP
;
238 case VK_STENCIL_OP_INVERT
:
239 return STENCIL_INVERT
;
240 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
241 return STENCIL_INCR_WRAP
;
242 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
243 return STENCIL_DECR_WRAP
;
245 unreachable("invalid VkStencilOp");
250 static enum a3xx_rop_code
251 tu6_rop(VkLogicOp op
)
254 case VK_LOGIC_OP_CLEAR
:
256 case VK_LOGIC_OP_AND
:
258 case VK_LOGIC_OP_AND_REVERSE
:
259 return ROP_AND_REVERSE
;
260 case VK_LOGIC_OP_COPY
:
262 case VK_LOGIC_OP_AND_INVERTED
:
263 return ROP_AND_INVERTED
;
264 case VK_LOGIC_OP_NO_OP
:
266 case VK_LOGIC_OP_XOR
:
270 case VK_LOGIC_OP_NOR
:
272 case VK_LOGIC_OP_EQUIVALENT
:
274 case VK_LOGIC_OP_INVERT
:
276 case VK_LOGIC_OP_OR_REVERSE
:
277 return ROP_OR_REVERSE
;
278 case VK_LOGIC_OP_COPY_INVERTED
:
279 return ROP_COPY_INVERTED
;
280 case VK_LOGIC_OP_OR_INVERTED
:
281 return ROP_OR_INVERTED
;
282 case VK_LOGIC_OP_NAND
:
284 case VK_LOGIC_OP_SET
:
287 unreachable("invalid VkLogicOp");
292 static enum adreno_rb_blend_factor
293 tu6_blend_factor(VkBlendFactor factor
)
296 case VK_BLEND_FACTOR_ZERO
:
298 case VK_BLEND_FACTOR_ONE
:
300 case VK_BLEND_FACTOR_SRC_COLOR
:
301 return FACTOR_SRC_COLOR
;
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
303 return FACTOR_ONE_MINUS_SRC_COLOR
;
304 case VK_BLEND_FACTOR_DST_COLOR
:
305 return FACTOR_DST_COLOR
;
306 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
307 return FACTOR_ONE_MINUS_DST_COLOR
;
308 case VK_BLEND_FACTOR_SRC_ALPHA
:
309 return FACTOR_SRC_ALPHA
;
310 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
311 return FACTOR_ONE_MINUS_SRC_ALPHA
;
312 case VK_BLEND_FACTOR_DST_ALPHA
:
313 return FACTOR_DST_ALPHA
;
314 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
315 return FACTOR_ONE_MINUS_DST_ALPHA
;
316 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
317 return FACTOR_CONSTANT_COLOR
;
318 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
319 return FACTOR_ONE_MINUS_CONSTANT_COLOR
;
320 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
321 return FACTOR_CONSTANT_ALPHA
;
322 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
323 return FACTOR_ONE_MINUS_CONSTANT_ALPHA
;
324 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
325 return FACTOR_SRC_ALPHA_SATURATE
;
326 case VK_BLEND_FACTOR_SRC1_COLOR
:
327 return FACTOR_SRC1_COLOR
;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
329 return FACTOR_ONE_MINUS_SRC1_COLOR
;
330 case VK_BLEND_FACTOR_SRC1_ALPHA
:
331 return FACTOR_SRC1_ALPHA
;
332 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
333 return FACTOR_ONE_MINUS_SRC1_ALPHA
;
335 unreachable("invalid VkBlendFactor");
340 static enum a3xx_rb_blend_opcode
341 tu6_blend_op(VkBlendOp op
)
344 case VK_BLEND_OP_ADD
:
345 return BLEND_DST_PLUS_SRC
;
346 case VK_BLEND_OP_SUBTRACT
:
347 return BLEND_SRC_MINUS_DST
;
348 case VK_BLEND_OP_REVERSE_SUBTRACT
:
349 return BLEND_DST_MINUS_SRC
;
350 case VK_BLEND_OP_MIN
:
351 return BLEND_MIN_DST_SRC
;
352 case VK_BLEND_OP_MAX
:
353 return BLEND_MAX_DST_SRC
;
355 unreachable("invalid VkBlendOp");
356 return BLEND_DST_PLUS_SRC
;
361 tu6_emit_vs_config(struct tu_cs
*cs
, const struct ir3_shader_variant
*vs
)
363 uint32_t sp_vs_ctrl
=
364 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
365 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
366 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
367 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
);
369 sp_vs_ctrl
|= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
;
371 uint32_t sp_vs_config
= A6XX_SP_VS_CONFIG_NTEX(vs
->num_samp
) |
372 A6XX_SP_VS_CONFIG_NSAMP(vs
->num_samp
);
374 sp_vs_config
|= A6XX_SP_VS_CONFIG_ENABLED
;
376 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
377 tu_cs_emit(cs
, sp_vs_ctrl
);
379 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_CONFIG
, 2);
380 tu_cs_emit(cs
, sp_vs_config
);
381 tu_cs_emit(cs
, vs
->instrlen
);
383 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_VS_CNTL
, 1);
384 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs
->constlen
, 4)) |
385 A6XX_HLSQ_VS_CNTL_ENABLED
);
389 tu6_emit_hs_config(struct tu_cs
*cs
, const struct ir3_shader_variant
*hs
)
391 uint32_t sp_hs_config
= 0;
393 sp_hs_config
|= A6XX_SP_HS_CONFIG_ENABLED
;
395 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
398 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_CONFIG
, 2);
399 tu_cs_emit(cs
, sp_hs_config
);
400 tu_cs_emit(cs
, hs
->instrlen
);
402 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_HS_CNTL
, 1);
403 tu_cs_emit(cs
, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs
->constlen
, 4)));
407 tu6_emit_ds_config(struct tu_cs
*cs
, const struct ir3_shader_variant
*ds
)
409 uint32_t sp_ds_config
= 0;
411 sp_ds_config
|= A6XX_SP_DS_CONFIG_ENABLED
;
413 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_CONFIG
, 2);
414 tu_cs_emit(cs
, sp_ds_config
);
415 tu_cs_emit(cs
, ds
->instrlen
);
417 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_DS_CNTL
, 1);
418 tu_cs_emit(cs
, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds
->constlen
, 4)));
422 tu6_emit_gs_config(struct tu_cs
*cs
, const struct ir3_shader_variant
*gs
)
424 uint32_t sp_gs_config
= 0;
426 sp_gs_config
|= A6XX_SP_GS_CONFIG_ENABLED
;
428 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
431 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CONFIG
, 2);
432 tu_cs_emit(cs
, sp_gs_config
);
433 tu_cs_emit(cs
, gs
->instrlen
);
435 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_GS_CNTL
, 1);
436 tu_cs_emit(cs
, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs
->constlen
, 4)));
440 tu6_emit_fs_config(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
442 uint32_t sp_fs_ctrl
=
443 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) | 0x1000000 |
444 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
445 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
446 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
);
447 if (fs
->total_in
> 0 || fs
->frag_coord
)
448 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_VARYING
;
450 sp_fs_ctrl
|= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
;
452 uint32_t sp_fs_config
= A6XX_SP_FS_CONFIG_NTEX(fs
->num_samp
) |
453 A6XX_SP_FS_CONFIG_NSAMP(fs
->num_samp
);
455 sp_fs_config
|= A6XX_SP_FS_CONFIG_ENABLED
;
457 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_A99E
, 1);
460 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
463 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
466 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
467 tu_cs_emit(cs
, sp_fs_ctrl
);
469 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_CONFIG
, 2);
470 tu_cs_emit(cs
, sp_fs_config
);
471 tu_cs_emit(cs
, fs
->instrlen
);
473 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_FS_CNTL
, 1);
474 tu_cs_emit(cs
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs
->constlen
, 4)) |
475 A6XX_HLSQ_FS_CNTL_ENABLED
);
479 tu6_emit_vs_system_values(struct tu_cs
*cs
,
480 const struct ir3_shader_variant
*vs
)
482 const uint32_t vertexid_regid
=
483 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
484 const uint32_t instanceid_regid
=
485 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
487 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
488 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
489 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
491 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_2 */
492 tu_cs_emit(cs
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
493 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
494 tu_cs_emit(cs
, 0x0000fcfc); /* VFD_CONTROL_5 */
495 tu_cs_emit(cs
, 0x00000000); /* VFD_CONTROL_6 */
499 tu6_emit_vpc(struct tu_cs
*cs
,
500 const struct ir3_shader_variant
*vs
,
501 const struct ir3_shader_variant
*fs
,
504 struct ir3_shader_linkage linkage
= { 0 };
505 ir3_link_shaders(&linkage
, vs
, fs
);
507 if (vs
->shader
->stream_output
.num_outputs
&& !binning_pass
)
508 tu_finishme("stream output");
510 BITSET_DECLARE(vpc_var_enables
, 128) = { 0 };
511 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
512 const uint32_t comp_count
= util_last_bit(linkage
.var
[i
].compmask
);
513 for (uint32_t j
= 0; j
< comp_count
; j
++)
514 BITSET_SET(vpc_var_enables
, linkage
.var
[i
].loc
+ j
);
517 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
518 tu_cs_emit(cs
, ~vpc_var_enables
[0]);
519 tu_cs_emit(cs
, ~vpc_var_enables
[1]);
520 tu_cs_emit(cs
, ~vpc_var_enables
[2]);
521 tu_cs_emit(cs
, ~vpc_var_enables
[3]);
523 /* a6xx finds position/pointsize at the end */
524 const uint32_t position_regid
=
525 ir3_find_output_regid(vs
, VARYING_SLOT_POS
);
526 const uint32_t pointsize_regid
=
527 ir3_find_output_regid(vs
, VARYING_SLOT_PSIZ
);
528 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff;
529 if (position_regid
!= regid(63, 0)) {
530 position_loc
= linkage
.max_loc
;
531 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
533 if (pointsize_regid
!= regid(63, 0)) {
534 pointsize_loc
= linkage
.max_loc
;
535 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
538 /* map vs outputs to VPC */
539 assert(linkage
.cnt
<= 32);
540 const uint32_t sp_vs_out_count
= (linkage
.cnt
+ 1) / 2;
541 const uint32_t sp_vs_vpc_dst_count
= (linkage
.cnt
+ 3) / 4;
542 uint32_t sp_vs_out
[16];
543 uint32_t sp_vs_vpc_dst
[8];
544 sp_vs_out
[sp_vs_out_count
- 1] = 0;
545 sp_vs_vpc_dst
[sp_vs_vpc_dst_count
- 1] = 0;
546 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
547 ((uint16_t *) sp_vs_out
)[i
] =
548 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
549 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
550 ((uint8_t *) sp_vs_vpc_dst
)[i
] =
551 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
554 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count
);
555 tu_cs_emit_array(cs
, sp_vs_out
, sp_vs_out_count
);
557 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count
);
558 tu_cs_emit_array(cs
, sp_vs_vpc_dst
, sp_vs_vpc_dst_count
);
560 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
561 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
562 (fs
->total_in
> 0 ? A6XX_VPC_CNTL_0_VARYING
: 0) |
565 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
566 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
567 A6XX_VPC_PACK_PSIZELOC(pointsize_loc
) |
568 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
570 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
571 tu_cs_emit(cs
, 0x0000ffff); /* XXX */
573 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
574 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage
.cnt
));
576 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
577 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage
.max_loc
) |
578 (vs
->writes_psize
? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
: 0));
582 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
584 uint8_t *interp_mode
,
585 uint8_t *ps_repl_mode
)
599 PS_REPL_ONE_MINUS_T
= 3,
602 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
604 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
605 * fourth component occupy three consecutive varying slots
610 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
611 if (compmask
& 0x1) {
612 *ps_repl_mode
|= PS_REPL_S
<< shift
;
615 if (compmask
& 0x2) {
616 *ps_repl_mode
|= PS_REPL_T
<< shift
;
619 if (compmask
& 0x4) {
620 *interp_mode
|= INTERP_ZERO
<< shift
;
623 if (compmask
& 0x8) {
624 *interp_mode
|= INTERP_ONE
<< 6;
627 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
628 fs
->inputs
[index
].rasterflat
) {
629 for (int i
= 0; i
< 4; i
++) {
630 if (compmask
& (1 << i
)) {
631 *interp_mode
|= INTERP_FLAT
<< shift
;
641 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
642 const struct ir3_shader_variant
*fs
,
645 uint32_t interp_modes
[8] = { 0 };
646 uint32_t ps_repl_modes
[8] = { 0 };
650 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
652 /* get the mode for input i */
654 uint8_t ps_repl_mode
;
656 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
658 /* OR the mode into the array */
659 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
660 uint32_t n
= inloc
/ 32;
661 uint32_t shift
= inloc
% 32;
662 interp_modes
[n
] |= interp_mode
<< shift
;
663 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
664 if (shift
+ bits
> 32) {
668 interp_modes
[n
] |= interp_mode
>> shift
;
669 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
674 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
675 tu_cs_emit_array(cs
, interp_modes
, 8);
677 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
678 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
681 #define VALIDREG(r) ((r) != regid(63,0))
682 #define CONDREG(r, val) COND(VALIDREG(r), (val))
685 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
687 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
688 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
689 uint32_t smask_in_regid
;
691 bool sample_shading
= fs
->per_samp
; /* TODO | key->sample_shading; */
692 bool enable_varyings
= fs
->total_in
> 0;
694 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
695 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
696 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
697 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
698 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
699 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
);
700 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SAMPLE
);
701 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_CENTROID
);
702 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SIZE
);
704 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
706 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
707 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
708 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
709 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
710 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
711 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
713 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
714 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
715 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
717 tu_cs_emit(cs
, 0xfc);
719 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
720 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
722 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_UNKNOWN_A982
, 1);
723 tu_cs_emit(cs
, 0); /* XXX */
725 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
726 tu_cs_emit(cs
, 0xff); /* XXX */
728 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
730 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
731 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
732 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
733 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
734 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
736 A6XX_GRAS_CNTL_SIZE
|
737 A6XX_GRAS_CNTL_XCOORD
|
738 A6XX_GRAS_CNTL_YCOORD
|
739 A6XX_GRAS_CNTL_ZCOORD
|
740 A6XX_GRAS_CNTL_WCOORD
) |
741 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
743 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
745 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
746 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
747 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
748 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
749 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
750 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
752 A6XX_RB_RENDER_CONTROL0_SIZE
|
753 A6XX_RB_RENDER_CONTROL0_XCOORD
|
754 A6XX_RB_RENDER_CONTROL0_YCOORD
|
755 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
756 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
757 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
759 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
760 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
761 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
762 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
766 tu6_emit_fs_outputs(struct tu_cs
*cs
,
767 const struct ir3_shader_variant
*fs
,
770 uint32_t smask_regid
, posz_regid
;
772 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
773 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
775 uint32_t fragdata_regid
[8];
776 if (fs
->color0_mrt
) {
777 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
778 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
779 fragdata_regid
[i
] = fragdata_regid
[0];
781 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
782 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
785 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
786 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
787 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
789 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
791 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
792 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
793 // TODO we could have a mix of half and full precision outputs,
794 // we really need to figure out half-precision from IR3_REG_HALF
795 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
796 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
799 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
800 tu_cs_emit(cs
, fs
->writes_pos
? A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
: 0);
801 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
803 uint32_t gras_su_depth_plane_cntl
= 0;
804 uint32_t rb_depth_plane_cntl
= 0;
805 if (fs
->no_earlyz
| fs
->writes_pos
) {
806 gras_su_depth_plane_cntl
|= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
807 rb_depth_plane_cntl
|= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
;
810 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
811 tu_cs_emit(cs
, gras_su_depth_plane_cntl
);
813 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
814 tu_cs_emit(cs
, rb_depth_plane_cntl
);
818 tu6_emit_shader_object(struct tu_cs
*cs
,
819 gl_shader_stage stage
,
820 const struct ir3_shader_variant
*variant
,
821 const struct tu_bo
*binary_bo
,
822 uint32_t binary_offset
)
826 enum a6xx_state_block sb
;
828 case MESA_SHADER_VERTEX
:
829 reg
= REG_A6XX_SP_VS_OBJ_START_LO
;
830 opcode
= CP_LOAD_STATE6_GEOM
;
833 case MESA_SHADER_TESS_CTRL
:
834 reg
= REG_A6XX_SP_HS_OBJ_START_LO
;
835 opcode
= CP_LOAD_STATE6_GEOM
;
838 case MESA_SHADER_TESS_EVAL
:
839 reg
= REG_A6XX_SP_DS_OBJ_START_LO
;
840 opcode
= CP_LOAD_STATE6_GEOM
;
843 case MESA_SHADER_GEOMETRY
:
844 reg
= REG_A6XX_SP_GS_OBJ_START_LO
;
845 opcode
= CP_LOAD_STATE6_GEOM
;
848 case MESA_SHADER_FRAGMENT
:
849 reg
= REG_A6XX_SP_FS_OBJ_START_LO
;
850 opcode
= CP_LOAD_STATE6_FRAG
;
853 case MESA_SHADER_COMPUTE
:
854 reg
= REG_A6XX_SP_CS_OBJ_START_LO
;
855 opcode
= CP_LOAD_STATE6_FRAG
;
859 unreachable("invalid gl_shader_stage");
860 opcode
= CP_LOAD_STATE6_GEOM
;
865 if (!variant
->instrlen
) {
866 tu_cs_emit_pkt4(cs
, reg
, 2);
867 tu_cs_emit_qw(cs
, 0);
871 assert(variant
->type
== stage
);
873 const uint64_t binary_iova
= binary_bo
->iova
+ binary_offset
;
874 assert((binary_iova
& 0x3) == 0);
876 tu_cs_emit_pkt4(cs
, reg
, 2);
877 tu_cs_emit_qw(cs
, binary_iova
);
879 /* always indirect */
880 const bool indirect
= true;
882 tu_cs_emit_pkt7(cs
, opcode
, 3);
883 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
884 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
885 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
886 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
887 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
888 tu_cs_emit_qw(cs
, binary_iova
);
890 const void *binary
= binary_bo
->map
+ binary_offset
;
892 tu_cs_emit_pkt7(cs
, opcode
, 3 + variant
->info
.sizedwords
);
893 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
894 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
895 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
896 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
897 CP_LOAD_STATE6_0_NUM_UNIT(variant
->instrlen
));
898 tu_cs_emit_qw(cs
, 0);
899 tu_cs_emit_array(cs
, binary
, variant
->info
.sizedwords
);
904 tu6_emit_immediates(struct tu_cs
*cs
, const struct ir3_shader_variant
*v
,
905 uint32_t opcode
, enum a6xx_state_block block
)
907 const struct ir3_const_state
*const_state
= &v
->shader
->const_state
;
908 uint32_t base
= const_state
->offsets
.immediate
;
909 int size
= const_state
->immediates_count
;
911 /* truncate size to avoid writing constants that shader
914 size
= MIN2(size
+ base
, v
->constlen
) - base
;
919 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
* 4);
920 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
921 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
922 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
923 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_SHADER
) |
924 CP_LOAD_STATE6_0_NUM_UNIT(size
));
925 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
926 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
928 for (unsigned i
= 0; i
< size
; i
++) {
929 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
930 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
931 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
932 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
937 tu6_emit_program(struct tu_cs
*cs
,
938 const struct tu_pipeline_builder
*builder
,
939 const struct tu_bo
*binary_bo
,
942 static const struct ir3_shader_variant dummy_variant
= {
943 .type
= MESA_SHADER_NONE
945 assert(builder
->shaders
[MESA_SHADER_VERTEX
]);
946 const struct ir3_shader_variant
*vs
=
947 &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[0];
948 const struct ir3_shader_variant
*hs
=
949 builder
->shaders
[MESA_SHADER_TESS_CTRL
]
950 ? &builder
->shaders
[MESA_SHADER_TESS_CTRL
]->variants
[0]
952 const struct ir3_shader_variant
*ds
=
953 builder
->shaders
[MESA_SHADER_TESS_EVAL
]
954 ? &builder
->shaders
[MESA_SHADER_TESS_EVAL
]->variants
[0]
956 const struct ir3_shader_variant
*gs
=
957 builder
->shaders
[MESA_SHADER_GEOMETRY
]
958 ? &builder
->shaders
[MESA_SHADER_GEOMETRY
]->variants
[0]
960 const struct ir3_shader_variant
*fs
=
961 builder
->shaders
[MESA_SHADER_FRAGMENT
]
962 ? &builder
->shaders
[MESA_SHADER_FRAGMENT
]->variants
[0]
966 vs
= &builder
->shaders
[MESA_SHADER_VERTEX
]->variants
[1];
970 tu6_emit_vs_config(cs
, vs
);
971 tu6_emit_hs_config(cs
, hs
);
972 tu6_emit_ds_config(cs
, ds
);
973 tu6_emit_gs_config(cs
, gs
);
974 tu6_emit_fs_config(cs
, fs
);
976 tu6_emit_vs_system_values(cs
, vs
);
977 tu6_emit_vpc(cs
, vs
, fs
, binning_pass
);
978 tu6_emit_vpc_varying_modes(cs
, fs
, binning_pass
);
979 tu6_emit_fs_inputs(cs
, fs
);
980 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
);
982 tu6_emit_shader_object(cs
, MESA_SHADER_VERTEX
, vs
, binary_bo
,
983 builder
->shader_offsets
[MESA_SHADER_VERTEX
]);
985 tu6_emit_shader_object(cs
, MESA_SHADER_FRAGMENT
, fs
, binary_bo
,
986 builder
->shader_offsets
[MESA_SHADER_FRAGMENT
]);
988 tu6_emit_immediates(cs
, vs
, CP_LOAD_STATE6_GEOM
, SB6_VS_SHADER
);
990 tu6_emit_immediates(cs
, fs
, CP_LOAD_STATE6_FRAG
, SB6_FS_SHADER
);
994 tu6_emit_vertex_input(struct tu_cs
*cs
,
995 const struct ir3_shader_variant
*vs
,
996 const VkPipelineVertexInputStateCreateInfo
*vi_info
,
997 uint8_t bindings
[MAX_VERTEX_ATTRIBS
],
998 uint16_t strides
[MAX_VERTEX_ATTRIBS
],
999 uint16_t offsets
[MAX_VERTEX_ATTRIBS
],
1002 uint32_t vfd_decode_idx
= 0;
1004 for (uint32_t i
= 0; i
< vs
->inputs_count
; i
++) {
1005 if (vs
->inputs
[i
].sysval
|| !vs
->inputs
[i
].compmask
)
1008 const VkVertexInputAttributeDescription
*vi_attr
=
1009 tu_find_vertex_input_attribute(vi_info
, vs
->inputs
[i
].slot
);
1010 const VkVertexInputBindingDescription
*vi_binding
=
1011 tu_find_vertex_input_binding(vi_info
, vi_attr
);
1012 assert(vi_attr
&& vi_binding
);
1014 const struct tu_native_format
*format
=
1015 tu6_get_native_format(vi_attr
->format
);
1016 assert(format
&& format
->vtx
>= 0);
1018 uint32_t vfd_decode
= A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx
) |
1019 A6XX_VFD_DECODE_INSTR_FORMAT(format
->vtx
) |
1020 A6XX_VFD_DECODE_INSTR_SWAP(format
->swap
) |
1021 A6XX_VFD_DECODE_INSTR_UNK30
;
1022 if (vi_binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1023 vfd_decode
|= A6XX_VFD_DECODE_INSTR_INSTANCED
;
1024 if (!vk_format_is_int(vi_attr
->format
))
1025 vfd_decode
|= A6XX_VFD_DECODE_INSTR_FLOAT
;
1027 const uint32_t vfd_decode_step_rate
= 1;
1029 const uint32_t vfd_dest_cntl
=
1030 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs
->inputs
[i
].compmask
) |
1031 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs
->inputs
[i
].regid
);
1033 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DECODE(vfd_decode_idx
), 2);
1034 tu_cs_emit(cs
, vfd_decode
);
1035 tu_cs_emit(cs
, vfd_decode_step_rate
);
1037 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx
), 1);
1038 tu_cs_emit(cs
, vfd_dest_cntl
);
1040 bindings
[vfd_decode_idx
] = vi_binding
->binding
;
1041 strides
[vfd_decode_idx
] = vi_binding
->stride
;
1042 offsets
[vfd_decode_idx
] = vi_attr
->offset
;
1045 assert(vfd_decode_idx
<= MAX_VERTEX_ATTRIBS
);
1048 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_0
, 1);
1050 cs
, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx
) | (vfd_decode_idx
<< 8));
1052 *count
= vfd_decode_idx
;
1056 tu6_guardband_adj(uint32_t v
)
1059 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1065 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1069 scales
[0] = viewport
->width
/ 2.0f
;
1070 scales
[1] = viewport
->height
/ 2.0f
;
1071 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1072 offsets
[0] = viewport
->x
+ scales
[0];
1073 offsets
[1] = viewport
->y
+ scales
[1];
1074 offsets
[2] = viewport
->minDepth
;
1078 min
.x
= (int32_t) viewport
->x
;
1079 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1080 if (viewport
->height
>= 0.0f
) {
1081 min
.y
= (int32_t) viewport
->y
;
1082 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1084 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1085 max
.y
= (int32_t) ceilf(viewport
->y
);
1087 /* the spec allows viewport->height to be 0.0f */
1090 assert(min
.x
>= 0 && min
.x
< max
.x
);
1091 assert(min
.y
>= 0 && min
.y
< max
.y
);
1093 VkExtent2D guardband_adj
;
1094 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1095 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1097 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
1098 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets
[0]));
1099 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XSCALE_0(scales
[0]));
1100 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets
[1]));
1101 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YSCALE_0(scales
[1]));
1102 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets
[2]));
1103 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales
[2]));
1105 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
1106 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min
.x
) |
1107 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min
.y
));
1108 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max
.x
- 1) |
1109 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max
.y
- 1));
1111 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1113 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1114 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1118 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1120 const VkOffset2D min
= scissor
->offset
;
1121 const VkOffset2D max
= {
1122 scissor
->offset
.x
+ scissor
->extent
.width
,
1123 scissor
->offset
.y
+ scissor
->extent
.height
,
1126 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
1127 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min
.x
) |
1128 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min
.y
));
1129 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max
.x
- 1) |
1130 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max
.y
- 1));
1134 tu6_emit_gras_unknowns(struct tu_cs
*cs
)
1136 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8000
, 1);
1137 tu_cs_emit(cs
, 0x80);
1138 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8001
, 1);
1139 tu_cs_emit(cs
, 0x0);
1140 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8004
, 1);
1141 tu_cs_emit(cs
, 0x0);
1145 tu6_emit_point_size(struct tu_cs
*cs
)
1147 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POINT_MINMAX
, 2);
1148 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f
/ 16.0f
) |
1149 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f
));
1150 tu_cs_emit(cs
, A6XX_GRAS_SU_POINT_SIZE(1.0f
));
1154 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1155 VkSampleCountFlagBits samples
)
1157 uint32_t gras_su_cntl
= 0;
1159 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1160 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1161 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1162 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1164 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1165 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1167 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1169 if (rast_info
->depthBiasEnable
)
1170 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1172 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1173 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1175 return gras_su_cntl
;
1179 tu6_emit_gras_su_cntl(struct tu_cs
*cs
,
1180 uint32_t gras_su_cntl
,
1183 assert((gras_su_cntl
& A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
) == 0);
1184 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width
/ 2.0f
);
1186 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_CNTL
, 1);
1187 tu_cs_emit(cs
, gras_su_cntl
);
1191 tu6_emit_depth_bias(struct tu_cs
*cs
,
1192 float constant_factor
,
1196 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1197 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
));
1198 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
));
1199 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
));
1203 tu6_emit_alpha_control_disable(struct tu_cs
*cs
)
1205 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_ALPHA_CONTROL
, 1);
1210 tu6_emit_depth_control(struct tu_cs
*cs
,
1211 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1213 assert(!ds_info
->depthBoundsTestEnable
);
1215 uint32_t rb_depth_cntl
= 0;
1216 if (ds_info
->depthTestEnable
) {
1218 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1219 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1220 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1222 if (ds_info
->depthWriteEnable
)
1223 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1226 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1227 tu_cs_emit(cs
, rb_depth_cntl
);
1231 tu6_emit_stencil_control(struct tu_cs
*cs
,
1232 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1234 uint32_t rb_stencil_control
= 0;
1235 if (ds_info
->stencilTestEnable
) {
1236 const VkStencilOpState
*front
= &ds_info
->front
;
1237 const VkStencilOpState
*back
= &ds_info
->back
;
1238 rb_stencil_control
|=
1239 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1240 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1241 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1242 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1243 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1244 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1245 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1246 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1247 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1248 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1249 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1252 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1253 tu_cs_emit(cs
, rb_stencil_control
);
1257 tu6_emit_stencil_compare_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1259 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILMASK
, 1);
1261 cs
, A6XX_RB_STENCILMASK_MASK(front
) | A6XX_RB_STENCILMASK_BFMASK(back
));
1265 tu6_emit_stencil_write_mask(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1267 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILWRMASK
, 1);
1268 tu_cs_emit(cs
, A6XX_RB_STENCILWRMASK_WRMASK(front
) |
1269 A6XX_RB_STENCILWRMASK_BFWRMASK(back
));
1273 tu6_emit_stencil_reference(struct tu_cs
*cs
, uint32_t front
, uint32_t back
)
1275 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCILREF
, 1);
1277 A6XX_RB_STENCILREF_REF(front
) | A6XX_RB_STENCILREF_BFREF(back
));
1281 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1284 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1285 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1286 has_alpha
? att
->srcColorBlendFactor
1287 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1288 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1289 has_alpha
? att
->dstColorBlendFactor
1290 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1291 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1292 const enum adreno_rb_blend_factor src_alpha_factor
=
1293 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1294 const enum adreno_rb_blend_factor dst_alpha_factor
=
1295 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1297 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1298 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1299 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1300 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1301 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1302 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1306 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1307 uint32_t rb_mrt_control_rop
,
1311 uint32_t rb_mrt_control
=
1312 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1314 /* ignore blending and logic op for integer attachments */
1316 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1317 return rb_mrt_control
;
1320 rb_mrt_control
|= rb_mrt_control_rop
;
1322 if (att
->blendEnable
) {
1323 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1326 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1329 return rb_mrt_control
;
1333 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1334 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1335 const VkFormat attachment_formats
[MAX_RTS
],
1336 uint32_t *blend_enable_mask
)
1338 *blend_enable_mask
= 0;
1340 bool rop_reads_dst
= false;
1341 uint32_t rb_mrt_control_rop
= 0;
1342 if (blend_info
->logicOpEnable
) {
1343 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1344 rb_mrt_control_rop
=
1345 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1346 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1349 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
1350 const VkPipelineColorBlendAttachmentState
*att
=
1351 &blend_info
->pAttachments
[i
];
1352 const VkFormat format
= attachment_formats
[i
];
1354 uint32_t rb_mrt_control
= 0;
1355 uint32_t rb_mrt_blend_control
= 0;
1356 if (format
!= VK_FORMAT_UNDEFINED
) {
1357 const bool is_int
= vk_format_is_int(format
);
1358 const bool has_alpha
= vk_format_has_alpha(format
);
1361 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
1362 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
1364 if (att
->blendEnable
|| rop_reads_dst
)
1365 *blend_enable_mask
|= 1 << i
;
1368 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1369 tu_cs_emit(cs
, rb_mrt_control
);
1370 tu_cs_emit(cs
, rb_mrt_blend_control
);
1373 for (uint32_t i
= blend_info
->attachmentCount
; i
< MAX_RTS
; i
++) {
1374 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1381 tu6_emit_blend_control(struct tu_cs
*cs
,
1382 uint32_t blend_enable_mask
,
1383 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
1385 assert(!msaa_info
->sampleShadingEnable
);
1386 assert(!msaa_info
->alphaToOneEnable
);
1388 uint32_t sp_blend_cntl
= A6XX_SP_BLEND_CNTL_UNK8
;
1389 if (blend_enable_mask
)
1390 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ENABLED
;
1391 if (msaa_info
->alphaToCoverageEnable
)
1392 sp_blend_cntl
|= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1394 const uint32_t sample_mask
=
1395 msaa_info
->pSampleMask
? *msaa_info
->pSampleMask
1396 : ((1 << msaa_info
->rasterizationSamples
) - 1);
1398 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1399 uint32_t rb_blend_cntl
=
1400 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask
) |
1401 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND
|
1402 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask
);
1403 if (msaa_info
->alphaToCoverageEnable
)
1404 rb_blend_cntl
|= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE
;
1406 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_BLEND_CNTL
, 1);
1407 tu_cs_emit(cs
, sp_blend_cntl
);
1409 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_CNTL
, 1);
1410 tu_cs_emit(cs
, rb_blend_cntl
);
1414 tu6_emit_blend_constants(struct tu_cs
*cs
, const float constants
[4])
1416 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
1417 tu_cs_emit_array(cs
, (const uint32_t *) constants
, 4);
1421 tu_pipeline_builder_create_pipeline(struct tu_pipeline_builder
*builder
,
1422 struct tu_pipeline
**out_pipeline
)
1424 struct tu_device
*dev
= builder
->device
;
1426 struct tu_pipeline
*pipeline
=
1427 vk_zalloc2(&dev
->alloc
, builder
->alloc
, sizeof(*pipeline
), 8,
1428 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1430 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1432 tu_cs_init(&pipeline
->cs
, TU_CS_MODE_SUB_STREAM
, 2048);
1434 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1435 VkResult result
= tu_cs_reserve_space(dev
, &pipeline
->cs
, 2048);
1436 if (result
!= VK_SUCCESS
) {
1437 vk_free2(&dev
->alloc
, builder
->alloc
, pipeline
);
1441 *out_pipeline
= pipeline
;
1447 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
)
1449 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
1452 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1453 gl_shader_stage stage
=
1454 tu_shader_stage(builder
->create_info
->pStages
[i
].stage
);
1455 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
1458 struct tu_shader_compile_options options
;
1459 tu_shader_compile_options_init(&options
, builder
->create_info
);
1461 /* compile shaders in reverse order */
1462 struct tu_shader
*next_stage_shader
= NULL
;
1463 for (gl_shader_stage stage
= MESA_SHADER_STAGES
- 1;
1464 stage
> MESA_SHADER_NONE
; stage
--) {
1465 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
1469 struct tu_shader
*shader
=
1470 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->alloc
);
1472 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1475 tu_shader_compile(builder
->device
, shader
, next_stage_shader
,
1476 &options
, builder
->alloc
);
1477 if (result
!= VK_SUCCESS
)
1480 builder
->shaders
[stage
] = shader
;
1481 builder
->shader_offsets
[stage
] = builder
->shader_total_size
;
1482 builder
->shader_total_size
+=
1483 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
;
1485 next_stage_shader
= shader
;
1488 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1489 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1490 builder
->binning_vs_offset
= builder
->shader_total_size
;
1491 builder
->shader_total_size
+=
1492 sizeof(uint32_t) * vs
->variants
[1].info
.sizedwords
;
1499 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder
*builder
,
1500 struct tu_pipeline
*pipeline
)
1502 struct tu_bo
*bo
= &pipeline
->program
.binary_bo
;
1505 tu_bo_init_new(builder
->device
, bo
, builder
->shader_total_size
);
1506 if (result
!= VK_SUCCESS
)
1509 result
= tu_bo_map(builder
->device
, bo
);
1510 if (result
!= VK_SUCCESS
)
1513 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1514 const struct tu_shader
*shader
= builder
->shaders
[i
];
1518 memcpy(bo
->map
+ builder
->shader_offsets
[i
], shader
->binary
,
1519 sizeof(uint32_t) * shader
->variants
[0].info
.sizedwords
);
1522 if (builder
->shaders
[MESA_SHADER_VERTEX
]->has_binning_pass
) {
1523 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1524 memcpy(bo
->map
+ builder
->binning_vs_offset
, vs
->binning_binary
,
1525 sizeof(uint32_t) * vs
->variants
[1].info
.sizedwords
);
1532 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
1533 struct tu_pipeline
*pipeline
)
1535 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
1536 builder
->create_info
->pDynamicState
;
1541 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
1542 pipeline
->dynamic_state
.mask
|=
1543 tu_dynamic_state_bit(dynamic_info
->pDynamicStates
[i
]);
1548 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
1549 struct tu_pipeline
*pipeline
)
1551 struct tu_cs prog_cs
;
1552 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 512, &prog_cs
);
1553 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, false);
1554 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1556 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 512, &prog_cs
);
1557 tu6_emit_program(&prog_cs
, builder
, &pipeline
->program
.binary_bo
, true);
1558 pipeline
->program
.binning_state_ib
=
1559 tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
1561 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1562 if (!builder
->shaders
[i
])
1565 struct tu_program_descriptor_linkage
*link
= &pipeline
->program
.link
[i
];
1566 struct ir3_shader
*shader
= builder
->shaders
[i
]->variants
[0].shader
;
1568 link
->ubo_state
= shader
->ubo_state
;
1569 link
->constlen
= builder
->shaders
[i
]->variants
[0].constlen
;
1570 link
->offset_ubo
= shader
->const_state
.offsets
.ubo
;
1571 link
->num_ubo
= shader
->const_state
.num_ubos
;
1572 link
->texture_map
= builder
->shaders
[i
]->texture_map
;
1573 link
->sampler_map
= builder
->shaders
[i
]->sampler_map
;
1574 link
->ubo_map
= builder
->shaders
[i
]->ubo_map
;
1579 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
1580 struct tu_pipeline
*pipeline
)
1582 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1583 builder
->create_info
->pVertexInputState
;
1584 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1587 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
,
1588 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
1589 tu6_emit_vertex_input(&vi_cs
, &vs
->variants
[0], vi_info
,
1590 pipeline
->vi
.bindings
, pipeline
->vi
.strides
,
1591 pipeline
->vi
.offsets
, &pipeline
->vi
.count
);
1592 pipeline
->vi
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
1594 if (vs
->has_binning_pass
) {
1595 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
,
1596 MAX_VERTEX_ATTRIBS
* 5 + 2, &vi_cs
);
1597 tu6_emit_vertex_input(
1598 &vi_cs
, &vs
->variants
[1], vi_info
, pipeline
->vi
.binning_bindings
,
1599 pipeline
->vi
.binning_strides
, pipeline
->vi
.binning_offsets
,
1600 &pipeline
->vi
.binning_count
);
1601 pipeline
->vi
.binning_state_ib
=
1602 tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
1607 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
1608 struct tu_pipeline
*pipeline
)
1610 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1611 builder
->create_info
->pInputAssemblyState
;
1613 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
1614 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
1618 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
1619 struct tu_pipeline
*pipeline
)
1623 * pViewportState is a pointer to an instance of the
1624 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1625 * pipeline has rasterization disabled."
1627 * We leave the relevant registers stale in that case.
1629 if (builder
->rasterizer_discard
)
1632 const VkPipelineViewportStateCreateInfo
*vp_info
=
1633 builder
->create_info
->pViewportState
;
1636 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 15, &vp_cs
);
1638 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_VIEWPORT
)) {
1639 assert(vp_info
->viewportCount
== 1);
1640 tu6_emit_viewport(&vp_cs
, vp_info
->pViewports
);
1643 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_SCISSOR
)) {
1644 assert(vp_info
->scissorCount
== 1);
1645 tu6_emit_scissor(&vp_cs
, vp_info
->pScissors
);
1648 pipeline
->vp
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vp_cs
);
1652 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
1653 struct tu_pipeline
*pipeline
)
1655 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
1656 builder
->create_info
->pRasterizationState
;
1658 assert(!rast_info
->depthClampEnable
);
1659 assert(rast_info
->polygonMode
== VK_POLYGON_MODE_FILL
);
1661 struct tu_cs rast_cs
;
1662 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 20, &rast_cs
);
1664 /* move to hw ctx init? */
1665 tu6_emit_gras_unknowns(&rast_cs
);
1666 tu6_emit_point_size(&rast_cs
);
1668 const uint32_t gras_su_cntl
=
1669 tu6_gras_su_cntl(rast_info
, builder
->samples
);
1671 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
))
1672 tu6_emit_gras_su_cntl(&rast_cs
, gras_su_cntl
, rast_info
->lineWidth
);
1674 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_DEPTH_BIAS
)) {
1675 tu6_emit_depth_bias(&rast_cs
, rast_info
->depthBiasConstantFactor
,
1676 rast_info
->depthBiasClamp
,
1677 rast_info
->depthBiasSlopeFactor
);
1680 pipeline
->rast
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &rast_cs
);
1682 pipeline
->rast
.gras_su_cntl
= gras_su_cntl
;
1686 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
1687 struct tu_pipeline
*pipeline
)
1691 * pDepthStencilState is a pointer to an instance of the
1692 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1693 * the pipeline has rasterization disabled or if the subpass of the
1694 * render pass the pipeline is created against does not use a
1695 * depth/stencil attachment.
1697 * We disable both depth and stenil tests in those cases.
1699 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
1700 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
1701 builder
->use_depth_stencil_attachment
1702 ? builder
->create_info
->pDepthStencilState
1706 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, 12, &ds_cs
);
1708 /* move to hw ctx init? */
1709 tu6_emit_alpha_control_disable(&ds_cs
);
1711 tu6_emit_depth_control(&ds_cs
, ds_info
);
1712 tu6_emit_stencil_control(&ds_cs
, ds_info
);
1714 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
1715 tu6_emit_stencil_compare_mask(&ds_cs
, ds_info
->front
.compareMask
,
1716 ds_info
->back
.compareMask
);
1718 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
1719 tu6_emit_stencil_write_mask(&ds_cs
, ds_info
->front
.writeMask
,
1720 ds_info
->back
.writeMask
);
1722 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
1723 tu6_emit_stencil_reference(&ds_cs
, ds_info
->front
.reference
,
1724 ds_info
->back
.reference
);
1727 pipeline
->ds
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &ds_cs
);
1731 tu_pipeline_builder_parse_multisample_and_color_blend(
1732 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
1736 * pMultisampleState is a pointer to an instance of the
1737 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1738 * has rasterization disabled.
1742 * pColorBlendState is a pointer to an instance of the
1743 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1744 * pipeline has rasterization disabled or if the subpass of the render
1745 * pass the pipeline is created against does not use any color
1748 * We leave the relevant registers stale when rasterization is disabled.
1750 if (builder
->rasterizer_discard
)
1753 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
1754 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
1755 builder
->create_info
->pMultisampleState
;
1756 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
1757 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
1758 : &dummy_blend_info
;
1760 struct tu_cs blend_cs
;
1761 tu_cs_begin_sub_stream(builder
->device
, &pipeline
->cs
, MAX_RTS
* 3 + 9,
1764 uint32_t blend_enable_mask
;
1765 tu6_emit_rb_mrt_controls(&blend_cs
, blend_info
,
1766 builder
->color_attachment_formats
,
1767 &blend_enable_mask
);
1769 if (!(pipeline
->dynamic_state
.mask
& TU_DYNAMIC_BLEND_CONSTANTS
))
1770 tu6_emit_blend_constants(&blend_cs
, blend_info
->blendConstants
);
1772 tu6_emit_blend_control(&blend_cs
, blend_enable_mask
, msaa_info
);
1774 pipeline
->blend
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &blend_cs
);
1778 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
1779 struct tu_device
*dev
,
1780 const VkAllocationCallbacks
*alloc
)
1782 tu_cs_finish(dev
, &pipeline
->cs
);
1784 if (pipeline
->program
.binary_bo
.gem_handle
)
1785 tu_bo_finish(dev
, &pipeline
->program
.binary_bo
);
1789 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
1790 struct tu_pipeline
**pipeline
)
1792 VkResult result
= tu_pipeline_builder_create_pipeline(builder
, pipeline
);
1793 if (result
!= VK_SUCCESS
)
1796 /* compile and upload shaders */
1797 result
= tu_pipeline_builder_compile_shaders(builder
);
1798 if (result
== VK_SUCCESS
)
1799 result
= tu_pipeline_builder_upload_shaders(builder
, *pipeline
);
1800 if (result
!= VK_SUCCESS
) {
1801 tu_pipeline_finish(*pipeline
, builder
->device
, builder
->alloc
);
1802 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
1803 *pipeline
= VK_NULL_HANDLE
;
1808 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
1809 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
1810 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
1811 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
1812 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
1813 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
1814 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
1815 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
1817 /* we should have reserved enough space upfront such that the CS never
1820 assert((*pipeline
)->cs
.bo_count
== 1);
1826 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
1828 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1829 if (!builder
->shaders
[i
])
1831 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
1836 tu_pipeline_builder_init_graphics(
1837 struct tu_pipeline_builder
*builder
,
1838 struct tu_device
*dev
,
1839 struct tu_pipeline_cache
*cache
,
1840 const VkGraphicsPipelineCreateInfo
*create_info
,
1841 const VkAllocationCallbacks
*alloc
)
1843 *builder
= (struct tu_pipeline_builder
) {
1846 .create_info
= create_info
,
1850 builder
->rasterizer_discard
=
1851 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
1853 if (builder
->rasterizer_discard
) {
1854 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
1856 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
1858 const struct tu_render_pass
*pass
=
1859 tu_render_pass_from_handle(create_info
->renderPass
);
1860 const struct tu_subpass
*subpass
=
1861 &pass
->subpasses
[create_info
->subpass
];
1863 builder
->use_depth_stencil_attachment
=
1864 subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
;
1866 assert(subpass
->color_count
== 0 ||
1867 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
1868 builder
->color_attachment_count
= subpass
->color_count
;
1869 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
1870 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
1871 if (a
== VK_ATTACHMENT_UNUSED
)
1874 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
1875 builder
->use_color_attachments
= true;
1881 tu_CreateGraphicsPipelines(VkDevice device
,
1882 VkPipelineCache pipelineCache
,
1884 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
1885 const VkAllocationCallbacks
*pAllocator
,
1886 VkPipeline
*pPipelines
)
1888 TU_FROM_HANDLE(tu_device
, dev
, device
);
1889 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
1890 VkResult final_result
= VK_SUCCESS
;
1892 for (uint32_t i
= 0; i
< count
; i
++) {
1893 struct tu_pipeline_builder builder
;
1894 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
1895 &pCreateInfos
[i
], pAllocator
);
1897 struct tu_pipeline
*pipeline
= NULL
;
1898 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
1899 tu_pipeline_builder_finish(&builder
);
1901 if (result
== VK_SUCCESS
) {
1902 pPipelines
[i
] = tu_pipeline_to_handle(pipeline
);
1904 pPipelines
[i
] = NULL
;
1905 final_result
= result
;
1909 return final_result
;
1913 tu_compute_pipeline_create(VkDevice _device
,
1914 VkPipelineCache _cache
,
1915 const VkComputePipelineCreateInfo
*pCreateInfo
,
1916 const VkAllocationCallbacks
*pAllocator
,
1917 VkPipeline
*pPipeline
)
1923 tu_CreateComputePipelines(VkDevice _device
,
1924 VkPipelineCache pipelineCache
,
1926 const VkComputePipelineCreateInfo
*pCreateInfos
,
1927 const VkAllocationCallbacks
*pAllocator
,
1928 VkPipeline
*pPipelines
)
1930 VkResult result
= VK_SUCCESS
;
1933 for (; i
< count
; i
++) {
1935 r
= tu_compute_pipeline_create(_device
, pipelineCache
, &pCreateInfos
[i
],
1936 pAllocator
, &pPipelines
[i
]);
1937 if (r
!= VK_SUCCESS
) {
1940 pPipelines
[i
] = VK_NULL_HANDLE
;
1947 tu_DestroyPipeline(VkDevice _device
,
1948 VkPipeline _pipeline
,
1949 const VkAllocationCallbacks
*pAllocator
)
1951 TU_FROM_HANDLE(tu_device
, dev
, _device
);
1952 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
1957 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
1958 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);