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tu: Remove tu_shader_compile_options
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 uint32_t
44 tu6_stage2opcode(gl_shader_stage stage)
45 {
46 if (stage == MESA_SHADER_FRAGMENT || stage == MESA_SHADER_COMPUTE)
47 return CP_LOAD_STATE6_FRAG;
48 return CP_LOAD_STATE6_GEOM;
49 }
50
51 static enum a6xx_state_block
52 tu6_stage2texsb(gl_shader_stage stage)
53 {
54 return SB6_VS_TEX + stage;
55 }
56
57 enum a6xx_state_block
58 tu6_stage2shadersb(gl_shader_stage stage)
59 {
60 return SB6_VS_SHADER + stage;
61 }
62
63 /* Emit IB that preloads the descriptors that the shader uses */
64
65 static void
66 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
67 enum a6xx_state_block sb, unsigned base, unsigned offset,
68 unsigned count)
69 {
70 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
71 * clear if emitting more packets will even help anything. Presumably the
72 * descriptor cache is relatively small, and these packets stop doing
73 * anything when there are too many descriptors.
74 */
75 tu_cs_emit_pkt7(cs, opcode, 3);
76 tu_cs_emit(cs,
77 CP_LOAD_STATE6_0_STATE_TYPE(st) |
78 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
79 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
80 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
81 tu_cs_emit_qw(cs, offset | (base << 28));
82 }
83
84 static unsigned
85 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
86 {
87 const unsigned load_state_size = 4;
88 unsigned size = 0;
89 for (unsigned i = 0; i < layout->num_sets; i++) {
90 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
91 for (unsigned j = 0; j < set_layout->binding_count; j++) {
92 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
93 unsigned count = 0;
94 /* Note: some users, like amber for example, pass in
95 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
96 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
97 */
98 VkShaderStageFlags stages = compute ?
99 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
100 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
101 unsigned stage_count = util_bitcount(stages);
102 switch (binding->type) {
103 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
104 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
105 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
106 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
107 /* IBO-backed resources only need one packet for all graphics stages */
108 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
109 count += 1;
110 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
111 count += 1;
112 break;
113 case VK_DESCRIPTOR_TYPE_SAMPLER:
114 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
115 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
116 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
117 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
118 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
119 /* Textures and UBO's needs a packet for each stage */
120 count = stage_count;
121 break;
122 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
123 /* Because of how we pack combined images and samplers, we
124 * currently can't use one packet for the whole array.
125 */
126 count = stage_count * binding->array_size * 2;
127 break;
128 default:
129 unreachable("bad descriptor type");
130 }
131 size += count * load_state_size;
132 }
133 }
134 return size;
135 }
136
137 static void
138 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
139 {
140 unsigned size = tu6_load_state_size(pipeline->layout, compute);
141 if (size == 0)
142 return;
143
144 struct tu_cs cs;
145 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
146
147 struct tu_pipeline_layout *layout = pipeline->layout;
148 for (unsigned i = 0; i < layout->num_sets; i++) {
149 /* From 13.2.7. Descriptor Set Binding:
150 *
151 * A compatible descriptor set must be bound for all set numbers that
152 * any shaders in a pipeline access, at the time that a draw or
153 * dispatch command is recorded to execute using that pipeline.
154 * However, if none of the shaders in a pipeline statically use any
155 * bindings with a particular set number, then no descriptor set need
156 * be bound for that set number, even if the pipeline layout includes
157 * a non-trivial descriptor set layout for that set number.
158 *
159 * This means that descriptor sets unused by the pipeline may have a
160 * garbage or 0 BINDLESS_BASE register, which will cause context faults
161 * when prefetching descriptors from these sets. Skip prefetching for
162 * descriptors from them to avoid this. This is also an optimization,
163 * since these prefetches would be useless.
164 */
165 if (!(pipeline->active_desc_sets & (1u << i)))
166 continue;
167
168 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
169 for (unsigned j = 0; j < set_layout->binding_count; j++) {
170 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
171 unsigned base = i;
172 unsigned offset = binding->offset / 4;
173 /* Note: some users, like amber for example, pass in
174 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
175 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
176 */
177 VkShaderStageFlags stages = compute ?
178 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
179 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
180 unsigned count = binding->array_size;
181 if (count == 0 || stages == 0)
182 continue;
183 switch (binding->type) {
184 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
185 base = MAX_SETS;
186 offset = (layout->input_attachment_count +
187 layout->set[i].dynamic_offset_start +
188 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
189 /* fallthrough */
190 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
191 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
192 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
193 /* IBO-backed resources only need one packet for all graphics stages */
194 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
195 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
196 base, offset, count);
197 }
198 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
199 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
200 base, offset, count);
201 }
202 break;
203 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
204 base = MAX_SETS;
205 offset = (layout->set[i].input_attachment_start +
206 binding->input_attachment_offset) * A6XX_TEX_CONST_DWORDS;
207 case VK_DESCRIPTOR_TYPE_SAMPLER:
208 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
209 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
210 tu_foreach_stage(stage, stages) {
211 emit_load_state(&cs, tu6_stage2opcode(stage),
212 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
213 ST6_SHADER : ST6_CONSTANTS,
214 tu6_stage2texsb(stage), base, offset, count);
215 }
216 break;
217 }
218 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
219 base = MAX_SETS;
220 offset = (layout->input_attachment_count +
221 layout->set[i].dynamic_offset_start +
222 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
223 /* fallthrough */
224 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
225 tu_foreach_stage(stage, stages) {
226 emit_load_state(&cs, tu6_stage2opcode(stage), ST6_UBO,
227 tu6_stage2shadersb(stage), base, offset, count);
228 }
229 break;
230 }
231 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
232 tu_foreach_stage(stage, stages) {
233 /* TODO: We could emit less CP_LOAD_STATE6 if we used
234 * struct-of-arrays instead of array-of-structs.
235 */
236 for (unsigned i = 0; i < count; i++) {
237 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
238 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
239 emit_load_state(&cs, tu6_stage2opcode(stage),
240 ST6_CONSTANTS, tu6_stage2texsb(stage),
241 base, tex_offset, 1);
242 emit_load_state(&cs, tu6_stage2opcode(stage),
243 ST6_SHADER, tu6_stage2texsb(stage),
244 base, sam_offset, 1);
245 }
246 }
247 break;
248 }
249 default:
250 unreachable("bad descriptor type");
251 }
252 }
253 }
254
255 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
256 }
257
258 struct tu_pipeline_builder
259 {
260 struct tu_device *device;
261 struct tu_pipeline_cache *cache;
262 struct tu_pipeline_layout *layout;
263 const VkAllocationCallbacks *alloc;
264 const VkGraphicsPipelineCreateInfo *create_info;
265
266 struct tu_shader *shaders[MESA_SHADER_STAGES];
267 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
268 struct ir3_shader_variant *binning_variant;
269 uint32_t shader_offsets[MESA_SHADER_STAGES];
270 uint32_t binning_vs_offset;
271 uint32_t shader_total_size;
272
273 bool rasterizer_discard;
274 /* these states are affectd by rasterizer_discard */
275 VkSampleCountFlagBits samples;
276 bool use_color_attachments;
277 bool use_dual_src_blend;
278 uint32_t color_attachment_count;
279 VkFormat color_attachment_formats[MAX_RTS];
280 VkFormat depth_attachment_format;
281 uint32_t render_components;
282 };
283
284 static enum tu_dynamic_state_bits
285 tu_dynamic_state_bit(VkDynamicState state)
286 {
287 switch (state) {
288 case VK_DYNAMIC_STATE_VIEWPORT:
289 return TU_DYNAMIC_VIEWPORT;
290 case VK_DYNAMIC_STATE_SCISSOR:
291 return TU_DYNAMIC_SCISSOR;
292 case VK_DYNAMIC_STATE_LINE_WIDTH:
293 return TU_DYNAMIC_LINE_WIDTH;
294 case VK_DYNAMIC_STATE_DEPTH_BIAS:
295 return TU_DYNAMIC_DEPTH_BIAS;
296 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
297 return TU_DYNAMIC_BLEND_CONSTANTS;
298 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
299 return TU_DYNAMIC_DEPTH_BOUNDS;
300 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
301 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
302 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
303 return TU_DYNAMIC_STENCIL_WRITE_MASK;
304 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
305 return TU_DYNAMIC_STENCIL_REFERENCE;
306 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
307 return TU_DYNAMIC_SAMPLE_LOCATIONS;
308 default:
309 unreachable("invalid dynamic state");
310 return 0;
311 }
312 }
313
314 static bool
315 tu_logic_op_reads_dst(VkLogicOp op)
316 {
317 switch (op) {
318 case VK_LOGIC_OP_CLEAR:
319 case VK_LOGIC_OP_COPY:
320 case VK_LOGIC_OP_COPY_INVERTED:
321 case VK_LOGIC_OP_SET:
322 return false;
323 default:
324 return true;
325 }
326 }
327
328 static VkBlendFactor
329 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
330 {
331 /* treat dst alpha as 1.0 and avoid reading it */
332 switch (factor) {
333 case VK_BLEND_FACTOR_DST_ALPHA:
334 return VK_BLEND_FACTOR_ONE;
335 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
336 return VK_BLEND_FACTOR_ZERO;
337 default:
338 return factor;
339 }
340 }
341
342 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
343 {
344 switch (factor) {
345 case VK_BLEND_FACTOR_SRC1_COLOR:
346 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
347 case VK_BLEND_FACTOR_SRC1_ALPHA:
348 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
349 return true;
350 default:
351 return false;
352 }
353 }
354
355 static bool
356 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
357 {
358 if (!info)
359 return false;
360
361 for (unsigned i = 0; i < info->attachmentCount; i++) {
362 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
363 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
364 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
365 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
366 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
367 return true;
368 }
369
370 return false;
371 }
372
373 static enum pc_di_primtype
374 tu6_primtype(VkPrimitiveTopology topology)
375 {
376 switch (topology) {
377 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
378 return DI_PT_POINTLIST;
379 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
380 return DI_PT_LINELIST;
381 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
382 return DI_PT_LINESTRIP;
383 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
384 return DI_PT_TRILIST;
385 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
386 return DI_PT_TRISTRIP;
387 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
388 return DI_PT_TRIFAN;
389 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
390 return DI_PT_LINE_ADJ;
391 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
392 return DI_PT_LINESTRIP_ADJ;
393 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
394 return DI_PT_TRI_ADJ;
395 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
396 return DI_PT_TRISTRIP_ADJ;
397 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
398 default:
399 unreachable("invalid primitive topology");
400 return DI_PT_NONE;
401 }
402 }
403
404 static enum adreno_compare_func
405 tu6_compare_func(VkCompareOp op)
406 {
407 switch (op) {
408 case VK_COMPARE_OP_NEVER:
409 return FUNC_NEVER;
410 case VK_COMPARE_OP_LESS:
411 return FUNC_LESS;
412 case VK_COMPARE_OP_EQUAL:
413 return FUNC_EQUAL;
414 case VK_COMPARE_OP_LESS_OR_EQUAL:
415 return FUNC_LEQUAL;
416 case VK_COMPARE_OP_GREATER:
417 return FUNC_GREATER;
418 case VK_COMPARE_OP_NOT_EQUAL:
419 return FUNC_NOTEQUAL;
420 case VK_COMPARE_OP_GREATER_OR_EQUAL:
421 return FUNC_GEQUAL;
422 case VK_COMPARE_OP_ALWAYS:
423 return FUNC_ALWAYS;
424 default:
425 unreachable("invalid VkCompareOp");
426 return FUNC_NEVER;
427 }
428 }
429
430 static enum adreno_stencil_op
431 tu6_stencil_op(VkStencilOp op)
432 {
433 switch (op) {
434 case VK_STENCIL_OP_KEEP:
435 return STENCIL_KEEP;
436 case VK_STENCIL_OP_ZERO:
437 return STENCIL_ZERO;
438 case VK_STENCIL_OP_REPLACE:
439 return STENCIL_REPLACE;
440 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
441 return STENCIL_INCR_CLAMP;
442 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
443 return STENCIL_DECR_CLAMP;
444 case VK_STENCIL_OP_INVERT:
445 return STENCIL_INVERT;
446 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
447 return STENCIL_INCR_WRAP;
448 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
449 return STENCIL_DECR_WRAP;
450 default:
451 unreachable("invalid VkStencilOp");
452 return STENCIL_KEEP;
453 }
454 }
455
456 static enum a3xx_rop_code
457 tu6_rop(VkLogicOp op)
458 {
459 switch (op) {
460 case VK_LOGIC_OP_CLEAR:
461 return ROP_CLEAR;
462 case VK_LOGIC_OP_AND:
463 return ROP_AND;
464 case VK_LOGIC_OP_AND_REVERSE:
465 return ROP_AND_REVERSE;
466 case VK_LOGIC_OP_COPY:
467 return ROP_COPY;
468 case VK_LOGIC_OP_AND_INVERTED:
469 return ROP_AND_INVERTED;
470 case VK_LOGIC_OP_NO_OP:
471 return ROP_NOOP;
472 case VK_LOGIC_OP_XOR:
473 return ROP_XOR;
474 case VK_LOGIC_OP_OR:
475 return ROP_OR;
476 case VK_LOGIC_OP_NOR:
477 return ROP_NOR;
478 case VK_LOGIC_OP_EQUIVALENT:
479 return ROP_EQUIV;
480 case VK_LOGIC_OP_INVERT:
481 return ROP_INVERT;
482 case VK_LOGIC_OP_OR_REVERSE:
483 return ROP_OR_REVERSE;
484 case VK_LOGIC_OP_COPY_INVERTED:
485 return ROP_COPY_INVERTED;
486 case VK_LOGIC_OP_OR_INVERTED:
487 return ROP_OR_INVERTED;
488 case VK_LOGIC_OP_NAND:
489 return ROP_NAND;
490 case VK_LOGIC_OP_SET:
491 return ROP_SET;
492 default:
493 unreachable("invalid VkLogicOp");
494 return ROP_NOOP;
495 }
496 }
497
498 static enum adreno_rb_blend_factor
499 tu6_blend_factor(VkBlendFactor factor)
500 {
501 switch (factor) {
502 case VK_BLEND_FACTOR_ZERO:
503 return FACTOR_ZERO;
504 case VK_BLEND_FACTOR_ONE:
505 return FACTOR_ONE;
506 case VK_BLEND_FACTOR_SRC_COLOR:
507 return FACTOR_SRC_COLOR;
508 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
509 return FACTOR_ONE_MINUS_SRC_COLOR;
510 case VK_BLEND_FACTOR_DST_COLOR:
511 return FACTOR_DST_COLOR;
512 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
513 return FACTOR_ONE_MINUS_DST_COLOR;
514 case VK_BLEND_FACTOR_SRC_ALPHA:
515 return FACTOR_SRC_ALPHA;
516 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
517 return FACTOR_ONE_MINUS_SRC_ALPHA;
518 case VK_BLEND_FACTOR_DST_ALPHA:
519 return FACTOR_DST_ALPHA;
520 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
521 return FACTOR_ONE_MINUS_DST_ALPHA;
522 case VK_BLEND_FACTOR_CONSTANT_COLOR:
523 return FACTOR_CONSTANT_COLOR;
524 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
525 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
526 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
527 return FACTOR_CONSTANT_ALPHA;
528 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
529 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
530 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
531 return FACTOR_SRC_ALPHA_SATURATE;
532 case VK_BLEND_FACTOR_SRC1_COLOR:
533 return FACTOR_SRC1_COLOR;
534 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
535 return FACTOR_ONE_MINUS_SRC1_COLOR;
536 case VK_BLEND_FACTOR_SRC1_ALPHA:
537 return FACTOR_SRC1_ALPHA;
538 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
539 return FACTOR_ONE_MINUS_SRC1_ALPHA;
540 default:
541 unreachable("invalid VkBlendFactor");
542 return FACTOR_ZERO;
543 }
544 }
545
546 static enum a3xx_rb_blend_opcode
547 tu6_blend_op(VkBlendOp op)
548 {
549 switch (op) {
550 case VK_BLEND_OP_ADD:
551 return BLEND_DST_PLUS_SRC;
552 case VK_BLEND_OP_SUBTRACT:
553 return BLEND_SRC_MINUS_DST;
554 case VK_BLEND_OP_REVERSE_SUBTRACT:
555 return BLEND_DST_MINUS_SRC;
556 case VK_BLEND_OP_MIN:
557 return BLEND_MIN_DST_SRC;
558 case VK_BLEND_OP_MAX:
559 return BLEND_MAX_DST_SRC;
560 default:
561 unreachable("invalid VkBlendOp");
562 return BLEND_DST_PLUS_SRC;
563 }
564 }
565
566 void
567 tu6_emit_xs_config(struct tu_cs *cs,
568 gl_shader_stage stage, /* xs->type, but xs may be NULL */
569 const struct ir3_shader_variant *xs,
570 uint64_t binary_iova)
571 {
572 static const struct xs_config {
573 uint16_t reg_sp_xs_ctrl;
574 uint16_t reg_sp_xs_config;
575 uint16_t reg_hlsq_xs_ctrl;
576 uint16_t reg_sp_vs_obj_start;
577 } xs_config[] = {
578 [MESA_SHADER_VERTEX] = {
579 REG_A6XX_SP_VS_CTRL_REG0,
580 REG_A6XX_SP_VS_CONFIG,
581 REG_A6XX_HLSQ_VS_CNTL,
582 REG_A6XX_SP_VS_OBJ_START_LO,
583 },
584 [MESA_SHADER_TESS_CTRL] = {
585 REG_A6XX_SP_HS_CTRL_REG0,
586 REG_A6XX_SP_HS_CONFIG,
587 REG_A6XX_HLSQ_HS_CNTL,
588 REG_A6XX_SP_HS_OBJ_START_LO,
589 },
590 [MESA_SHADER_TESS_EVAL] = {
591 REG_A6XX_SP_DS_CTRL_REG0,
592 REG_A6XX_SP_DS_CONFIG,
593 REG_A6XX_HLSQ_DS_CNTL,
594 REG_A6XX_SP_DS_OBJ_START_LO,
595 },
596 [MESA_SHADER_GEOMETRY] = {
597 REG_A6XX_SP_GS_CTRL_REG0,
598 REG_A6XX_SP_GS_CONFIG,
599 REG_A6XX_HLSQ_GS_CNTL,
600 REG_A6XX_SP_GS_OBJ_START_LO,
601 },
602 [MESA_SHADER_FRAGMENT] = {
603 REG_A6XX_SP_FS_CTRL_REG0,
604 REG_A6XX_SP_FS_CONFIG,
605 REG_A6XX_HLSQ_FS_CNTL,
606 REG_A6XX_SP_FS_OBJ_START_LO,
607 },
608 [MESA_SHADER_COMPUTE] = {
609 REG_A6XX_SP_CS_CTRL_REG0,
610 REG_A6XX_SP_CS_CONFIG,
611 REG_A6XX_HLSQ_CS_CNTL,
612 REG_A6XX_SP_CS_OBJ_START_LO,
613 },
614 };
615 const struct xs_config *cfg = &xs_config[stage];
616
617 if (!xs) {
618 /* shader stage disabled */
619 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
620 tu_cs_emit(cs, 0);
621
622 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
623 tu_cs_emit(cs, 0);
624 return;
625 }
626
627 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
628 enum a3xx_threadsize threadsize = FOUR_QUADS;
629
630 /* TODO:
631 * the "threadsize" field may have nothing to do with threadsize,
632 * use a value that matches the blob until it is figured out
633 */
634 if (xs->type == MESA_SHADER_GEOMETRY)
635 threadsize = TWO_QUADS;
636
637 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
638 tu_cs_emit(cs,
639 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
640 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
641 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
642 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
643 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
644 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
645 /* only fragment shader sets VARYING bit */
646 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
647 /* unknown bit, seems unnecessary */
648 COND(is_fs, 0x1000000));
649
650 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
651 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
652 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
653 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
654 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
655 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
656 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
657 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
658 tu_cs_emit(cs, xs->instrlen);
659
660 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
661 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(xs->constlen, 4)) |
662 A6XX_HLSQ_VS_CNTL_ENABLED);
663
664 /* emit program binary
665 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
666 */
667
668 assert((binary_iova & 0x7f) == 0);
669
670 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
671 tu_cs_emit_qw(cs, binary_iova);
672
673 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
674 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
675 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
676 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
677 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
678 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
679 tu_cs_emit_qw(cs, binary_iova);
680
681 /* emit immediates */
682
683 const struct ir3_const_state *const_state = &xs->shader->const_state;
684 uint32_t base = const_state->offsets.immediate;
685 int size = const_state->immediates_count;
686
687 /* truncate size to avoid writing constants that shader
688 * does not use:
689 */
690 size = MIN2(size + base, xs->constlen) - base;
691
692 if (size <= 0)
693 return;
694
695 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + size * 4);
696 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
697 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
698 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
699 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
700 CP_LOAD_STATE6_0_NUM_UNIT(size));
701 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
702 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
703
704 for (unsigned i = 0; i < size; i++) {
705 tu_cs_emit(cs, const_state->immediates[i].val[0]);
706 tu_cs_emit(cs, const_state->immediates[i].val[1]);
707 tu_cs_emit(cs, const_state->immediates[i].val[2]);
708 tu_cs_emit(cs, const_state->immediates[i].val[3]);
709 }
710 }
711
712 static void
713 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
714 const struct ir3_shader_variant *v,
715 uint32_t binary_iova)
716 {
717 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
718 tu_cs_emit(cs, 0xff);
719
720 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
721
722 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
723 tu_cs_emit(cs, 0x41);
724
725 uint32_t local_invocation_id =
726 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
727 uint32_t work_group_id =
728 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
729
730 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
731 tu_cs_emit(cs,
732 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
733 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
734 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
735 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
736 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
737 }
738
739 static void
740 tu6_emit_vs_system_values(struct tu_cs *cs,
741 const struct ir3_shader_variant *vs,
742 const struct ir3_shader_variant *gs,
743 bool primid_passthru)
744 {
745 const uint32_t vertexid_regid =
746 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
747 const uint32_t instanceid_regid =
748 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
749 const uint32_t primitiveid_regid = gs ?
750 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
751 regid(63, 0);
752 const uint32_t gsheader_regid = gs ?
753 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
754 regid(63, 0);
755
756 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
757 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
758 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
759 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
760 0xfc000000);
761 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
762 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
763 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
764 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
765 0xfc00); /* VFD_CONTROL_5 */
766 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
767 }
768
769 /* Add any missing varyings needed for stream-out. Otherwise varyings not
770 * used by fragment shader will be stripped out.
771 */
772 static void
773 tu6_link_streamout(struct ir3_shader_linkage *l,
774 const struct ir3_shader_variant *v)
775 {
776 const struct ir3_stream_output_info *info = &v->shader->stream_output;
777
778 /*
779 * First, any stream-out varyings not already in linkage map (ie. also
780 * consumed by frag shader) need to be added:
781 */
782 for (unsigned i = 0; i < info->num_outputs; i++) {
783 const struct ir3_stream_output *out = &info->output[i];
784 unsigned compmask =
785 (1 << (out->num_components + out->start_component)) - 1;
786 unsigned k = out->register_index;
787 unsigned idx, nextloc = 0;
788
789 /* psize/pos need to be the last entries in linkage map, and will
790 * get added link_stream_out, so skip over them:
791 */
792 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
793 v->outputs[k].slot == VARYING_SLOT_POS)
794 continue;
795
796 for (idx = 0; idx < l->cnt; idx++) {
797 if (l->var[idx].regid == v->outputs[k].regid)
798 break;
799 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
800 }
801
802 /* add if not already in linkage map: */
803 if (idx == l->cnt)
804 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
805
806 /* expand component-mask if needed, ie streaming out all components
807 * but frag shader doesn't consume all components:
808 */
809 if (compmask & ~l->var[idx].compmask) {
810 l->var[idx].compmask |= compmask;
811 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
812 util_last_bit(l->var[idx].compmask));
813 }
814 }
815 }
816
817 static void
818 tu6_setup_streamout(const struct ir3_shader_variant *v,
819 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
820 {
821 const struct ir3_stream_output_info *info = &v->shader->stream_output;
822
823 memset(tf, 0, sizeof(*tf));
824
825 tf->prog_count = align(l->max_loc, 2) / 2;
826
827 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
828
829 /* set stride info to the streamout state */
830 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
831 tf->stride[i] = info->stride[i];
832
833 for (unsigned i = 0; i < info->num_outputs; i++) {
834 const struct ir3_stream_output *out = &info->output[i];
835 unsigned k = out->register_index;
836 unsigned idx;
837
838 /* Skip it, if there's an unused reg in the middle of outputs. */
839 if (v->outputs[k].regid == INVALID_REG)
840 continue;
841
842 tf->ncomp[out->output_buffer] += out->num_components;
843
844 /* linkage map sorted by order frag shader wants things, so
845 * a bit less ideal here..
846 */
847 for (idx = 0; idx < l->cnt; idx++)
848 if (l->var[idx].regid == v->outputs[k].regid)
849 break;
850
851 debug_assert(idx < l->cnt);
852
853 for (unsigned j = 0; j < out->num_components; j++) {
854 unsigned c = j + out->start_component;
855 unsigned loc = l->var[idx].loc + c;
856 unsigned off = j + out->dst_offset; /* in dwords */
857
858 if (loc & 1) {
859 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
860 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
861 A6XX_VPC_SO_PROG_B_OFF(off * 4);
862 } else {
863 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
864 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
865 A6XX_VPC_SO_PROG_A_OFF(off * 4);
866 }
867 }
868 }
869
870 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
871 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
872 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
873 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
874 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
875 }
876
877 static void
878 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
879 enum a6xx_state_block block, uint32_t offset,
880 uint32_t size, uint32_t *dwords) {
881 assert(size % 4 == 0);
882
883 tu_cs_emit_pkt7(cs, opcode, 3 + size);
884 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
885 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
886 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
887 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
888 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
889
890 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
891 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
892 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
893
894 tu_cs_emit_array(cs, dwords, size);
895 }
896
897 static void
898 tu6_emit_link_map(struct tu_cs *cs,
899 const struct ir3_shader_variant *producer,
900 const struct ir3_shader_variant *consumer) {
901 const struct ir3_const_state *const_state = &consumer->shader->const_state;
902 uint32_t base = const_state->offsets.primitive_map;
903 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
904 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
905 int size = DIV_ROUND_UP(num_loc, 4);
906
907 size = (MIN2(size + base, consumer->constlen) - base) * 4;
908 if (size <= 0)
909 return;
910
911 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
912 patch_locs);
913 }
914
915 static uint16_t
916 gl_primitive_to_tess(uint16_t primitive) {
917 switch (primitive) {
918 case GL_POINTS:
919 return TESS_POINTS;
920 case GL_LINE_STRIP:
921 return TESS_LINES;
922 case GL_TRIANGLE_STRIP:
923 return TESS_CW_TRIS;
924 default:
925 unreachable("");
926 }
927 }
928
929 void
930 tu6_emit_vpc(struct tu_cs *cs,
931 const struct ir3_shader_variant *vs,
932 const struct ir3_shader_variant *gs,
933 const struct ir3_shader_variant *fs,
934 struct tu_streamout_state *tf)
935 {
936 const struct ir3_shader_variant *last_shader = gs ?: vs;
937 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
938 if (fs)
939 ir3_link_shaders(&linkage, last_shader, fs, true);
940
941 if (last_shader->shader->stream_output.num_outputs)
942 tu6_link_streamout(&linkage, last_shader);
943
944 /* We do this after linking shaders in order to know whether PrimID
945 * passthrough needs to be enabled.
946 */
947 bool primid_passthru = linkage.primid_loc != 0xff;
948 tu6_emit_vs_system_values(cs, vs, gs, primid_passthru);
949
950 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
951 tu_cs_emit(cs, ~linkage.varmask[0]);
952 tu_cs_emit(cs, ~linkage.varmask[1]);
953 tu_cs_emit(cs, ~linkage.varmask[2]);
954 tu_cs_emit(cs, ~linkage.varmask[3]);
955
956 /* a6xx finds position/pointsize at the end */
957 const uint32_t position_regid =
958 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
959 const uint32_t pointsize_regid =
960 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
961 const uint32_t layer_regid = gs ?
962 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
963
964 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
965 if (layer_regid != regid(63, 0)) {
966 layer_loc = linkage.max_loc;
967 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
968 }
969 if (position_regid != regid(63, 0)) {
970 position_loc = linkage.max_loc;
971 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
972 }
973 if (pointsize_regid != regid(63, 0)) {
974 pointsize_loc = linkage.max_loc;
975 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
976 }
977
978 if (last_shader->shader->stream_output.num_outputs)
979 tu6_setup_streamout(last_shader, &linkage, tf);
980
981 /* map outputs of the last shader to VPC */
982 assert(linkage.cnt <= 32);
983 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
984 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
985 uint32_t sp_out[16];
986 uint32_t sp_vpc_dst[8];
987 for (uint32_t i = 0; i < linkage.cnt; i++) {
988 ((uint16_t *) sp_out)[i] =
989 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
990 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
991 ((uint8_t *) sp_vpc_dst)[i] =
992 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
993 }
994
995 if (gs)
996 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
997 else
998 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
999 tu_cs_emit_array(cs, sp_out, sp_out_count);
1000
1001 if (gs)
1002 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
1003 else
1004 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
1005 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
1006
1007 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
1008 tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
1009
1010 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
1011 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
1012 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
1013 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
1014 A6XX_VPC_CNTL_0_UNKLOC(0xff));
1015
1016 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
1017 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
1018 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
1019 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
1020
1021 if (gs) {
1022 uint32_t vertices_out, invocations, output, vec4_size;
1023 /* this detects the tu_clear_blit path, which doesn't set ->nir */
1024 if (gs->shader->nir) {
1025 tu6_emit_link_map(cs, vs, gs);
1026 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
1027 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
1028 invocations = gs->shader->nir->info.gs.invocations - 1;
1029 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1030 vec4_size = gs->shader->nir->info.gs.vertices_in *
1031 DIV_ROUND_UP(vs->shader->output_size, 4);
1032 } else {
1033 vertices_out = 3;
1034 output = TESS_CW_TRIS;
1035 invocations = 0;
1036 vec4_size = 0;
1037 }
1038
1039 uint32_t primitive_regid =
1040 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
1041 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
1042 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
1043 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
1044 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
1045
1046 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
1047 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
1048
1049 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
1050 tu_cs_emit(cs, CONDREG(layer_regid,
1051 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
1052
1053 uint32_t flags_regid = ir3_find_output_regid(gs,
1054 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
1055
1056 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
1057 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
1058 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
1059
1060 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
1061 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
1062 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
1063 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
1064 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
1065
1066 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1067 tu_cs_emit(cs,
1068 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1069 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1070 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1071
1072 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1073 tu_cs_emit(cs, 0);
1074
1075 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
1076 tu_cs_emit(cs, 0);
1077
1078 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1079 tu_cs_emit(cs, 0xff);
1080
1081 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
1082 tu_cs_emit(cs, 0xffff00);
1083
1084 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1085 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1086
1087 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
1088 tu_cs_emit(cs, 0);
1089
1090 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1091 tu_cs_emit(cs, vs->shader->output_size);
1092 }
1093
1094 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
1095 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
1096
1097 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
1098 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
1099 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
1100 }
1101
1102 static int
1103 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1104 uint32_t index,
1105 uint8_t *interp_mode,
1106 uint8_t *ps_repl_mode)
1107 {
1108 enum
1109 {
1110 INTERP_SMOOTH = 0,
1111 INTERP_FLAT = 1,
1112 INTERP_ZERO = 2,
1113 INTERP_ONE = 3,
1114 };
1115 enum
1116 {
1117 PS_REPL_NONE = 0,
1118 PS_REPL_S = 1,
1119 PS_REPL_T = 2,
1120 PS_REPL_ONE_MINUS_T = 3,
1121 };
1122
1123 const uint32_t compmask = fs->inputs[index].compmask;
1124
1125 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1126 * fourth component occupy three consecutive varying slots
1127 */
1128 int shift = 0;
1129 *interp_mode = 0;
1130 *ps_repl_mode = 0;
1131 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1132 if (compmask & 0x1) {
1133 *ps_repl_mode |= PS_REPL_S << shift;
1134 shift += 2;
1135 }
1136 if (compmask & 0x2) {
1137 *ps_repl_mode |= PS_REPL_T << shift;
1138 shift += 2;
1139 }
1140 if (compmask & 0x4) {
1141 *interp_mode |= INTERP_ZERO << shift;
1142 shift += 2;
1143 }
1144 if (compmask & 0x8) {
1145 *interp_mode |= INTERP_ONE << 6;
1146 shift += 2;
1147 }
1148 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1149 fs->inputs[index].rasterflat) {
1150 for (int i = 0; i < 4; i++) {
1151 if (compmask & (1 << i)) {
1152 *interp_mode |= INTERP_FLAT << shift;
1153 shift += 2;
1154 }
1155 }
1156 }
1157
1158 return shift;
1159 }
1160
1161 static void
1162 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1163 const struct ir3_shader_variant *fs)
1164 {
1165 uint32_t interp_modes[8] = { 0 };
1166 uint32_t ps_repl_modes[8] = { 0 };
1167
1168 if (fs) {
1169 for (int i = -1;
1170 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1171
1172 /* get the mode for input i */
1173 uint8_t interp_mode;
1174 uint8_t ps_repl_mode;
1175 const int bits =
1176 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1177
1178 /* OR the mode into the array */
1179 const uint32_t inloc = fs->inputs[i].inloc * 2;
1180 uint32_t n = inloc / 32;
1181 uint32_t shift = inloc % 32;
1182 interp_modes[n] |= interp_mode << shift;
1183 ps_repl_modes[n] |= ps_repl_mode << shift;
1184 if (shift + bits > 32) {
1185 n++;
1186 shift = 32 - shift;
1187
1188 interp_modes[n] |= interp_mode >> shift;
1189 ps_repl_modes[n] |= ps_repl_mode >> shift;
1190 }
1191 }
1192 }
1193
1194 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1195 tu_cs_emit_array(cs, interp_modes, 8);
1196
1197 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1198 tu_cs_emit_array(cs, ps_repl_modes, 8);
1199 }
1200
1201 void
1202 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1203 {
1204 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1205 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
1206 uint32_t smask_in_regid;
1207
1208 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
1209 bool enable_varyings = fs->total_in > 0;
1210
1211 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1212 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1213 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1214 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1215 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1216 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1217 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1218 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1219 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1220
1221 if (fs->num_sampler_prefetch > 0) {
1222 assert(VALIDREG(ij_pix_regid));
1223 /* also, it seems like ij_pix is *required* to be r0.x */
1224 assert(ij_pix_regid == regid(0, 0));
1225 }
1226
1227 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1228 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1229 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1230 0x7000); // XXX);
1231 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1232 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1233 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1234 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1235 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1236 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1237 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1238 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1239 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1240 }
1241
1242 if (fs->num_sampler_prefetch > 0) {
1243 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1244 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1245 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1246 tu_cs_emit(cs,
1247 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1248 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1249 }
1250 }
1251
1252 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1253 tu_cs_emit(cs, 0x7);
1254 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1255 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1256 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1257 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1258 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1259 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1260 0xfc00fc00);
1261 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1262 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1263 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1264 0x0000fc00);
1265 tu_cs_emit(cs, 0xfc);
1266
1267 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1268 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1269
1270 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1271 tu_cs_emit(cs,
1272 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1273 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1274 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1275 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1276 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1277 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
1278 A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
1279 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1280
1281 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1282 tu_cs_emit(cs,
1283 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1284 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1285 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1286 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1287 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1288 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1289 COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
1290 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
1291 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1292 tu_cs_emit(cs,
1293 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1294 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1295 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1296 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1297
1298 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1299 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1300
1301 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1302 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1303
1304 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1305 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1306 }
1307
1308 static void
1309 tu6_emit_fs_outputs(struct tu_cs *cs,
1310 const struct ir3_shader_variant *fs,
1311 uint32_t mrt_count, bool dual_src_blend,
1312 uint32_t render_components)
1313 {
1314 uint32_t smask_regid, posz_regid;
1315
1316 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1317 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1318
1319 uint32_t fragdata_regid[8];
1320 if (fs->color0_mrt) {
1321 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1322 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1323 fragdata_regid[i] = fragdata_regid[0];
1324 } else {
1325 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1326 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1327 }
1328
1329 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1330 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1331 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1332 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
1333 0xfc000000);
1334 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1335
1336 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1337 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1338 // TODO we could have a mix of half and full precision outputs,
1339 // we really need to figure out half-precision from IR3_REG_HALF
1340 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1341 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1342 }
1343
1344 tu_cs_emit_regs(cs,
1345 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1346
1347 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1348 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1349 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1350 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1351 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1352
1353 tu_cs_emit_regs(cs,
1354 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1355
1356 enum a6xx_ztest_mode zmode;
1357
1358 if (fs->no_earlyz || fs->has_kill || fs->writes_pos) {
1359 zmode = A6XX_LATE_Z;
1360 } else {
1361 zmode = A6XX_EARLY_Z;
1362 }
1363
1364 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1365 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1366
1367 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1368 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1369 }
1370
1371 static void
1372 tu6_emit_geometry_consts(struct tu_cs *cs,
1373 const struct ir3_shader_variant *vs,
1374 const struct ir3_shader_variant *gs) {
1375 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1376
1377 uint32_t params[4] = {
1378 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1379 vs->shader->output_size * 4, /* vertex stride */
1380 0,
1381 0,
1382 };
1383 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1384 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1385 ARRAY_SIZE(params), params);
1386
1387 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1388 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1389 ARRAY_SIZE(params), params);
1390 }
1391
1392 static void
1393 tu6_emit_program(struct tu_cs *cs,
1394 struct tu_pipeline_builder *builder,
1395 const struct tu_bo *binary_bo,
1396 bool binning_pass,
1397 struct tu_streamout_state *tf)
1398 {
1399 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
1400 const struct ir3_shader_variant *bs = builder->binning_variant;
1401 const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
1402 const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
1403 gl_shader_stage stage = MESA_SHADER_VERTEX;
1404
1405 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1406
1407 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1408 tu_cs_emit(cs, 0xff); /* XXX */
1409
1410 /* Don't use the binning pass variant when GS is present because we don't
1411 * support compiling correct binning pass variants with GS.
1412 */
1413 if (binning_pass && !gs) {
1414 vs = bs;
1415 tu6_emit_xs_config(cs, stage, bs,
1416 binary_bo->iova + builder->binning_vs_offset);
1417 stage++;
1418 }
1419
1420 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1421 const struct ir3_shader_variant *xs = builder->variants[stage];
1422
1423 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1424 fs = xs = NULL;
1425
1426 tu6_emit_xs_config(cs, stage, xs,
1427 binary_bo->iova + builder->shader_offsets[stage]);
1428 }
1429
1430 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1431 tu_cs_emit(cs, 0);
1432
1433 tu6_emit_vpc(cs, vs, gs, fs, tf);
1434 tu6_emit_vpc_varying_modes(cs, fs);
1435
1436 if (fs) {
1437 tu6_emit_fs_inputs(cs, fs);
1438 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1439 builder->use_dual_src_blend,
1440 builder->render_components);
1441 } else {
1442 /* TODO: check if these can be skipped if fs is disabled */
1443 struct ir3_shader_variant dummy_variant = {};
1444 tu6_emit_fs_inputs(cs, &dummy_variant);
1445 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1446 builder->use_dual_src_blend,
1447 builder->render_components);
1448 }
1449
1450 if (gs)
1451 tu6_emit_geometry_consts(cs, vs, gs);
1452 }
1453
1454 static void
1455 tu6_emit_vertex_input(struct tu_cs *cs,
1456 const struct ir3_shader_variant *vs,
1457 const VkPipelineVertexInputStateCreateInfo *info,
1458 uint32_t *bindings_used)
1459 {
1460 uint32_t vfd_decode_idx = 0;
1461 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1462
1463 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1464 const VkVertexInputBindingDescription *binding =
1465 &info->pVertexBindingDescriptions[i];
1466
1467 tu_cs_emit_regs(cs,
1468 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1469
1470 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1471 binding_instanced |= 1 << binding->binding;
1472
1473 *bindings_used |= 1 << binding->binding;
1474 }
1475
1476 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1477
1478 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1479 const VkVertexInputAttributeDescription *attr =
1480 &info->pVertexAttributeDescriptions[i];
1481 uint32_t input_idx;
1482
1483 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1484 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1485 break;
1486 }
1487
1488 /* attribute not used, skip it */
1489 if (input_idx == vs->inputs_count)
1490 continue;
1491
1492 const struct tu_native_format format = tu6_format_vtx(attr->format);
1493 tu_cs_emit_regs(cs,
1494 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1495 .idx = attr->binding,
1496 .offset = attr->offset,
1497 .instanced = binding_instanced & (1 << attr->binding),
1498 .format = format.fmt,
1499 .swap = format.swap,
1500 .unk30 = 1,
1501 ._float = !vk_format_is_int(attr->format)),
1502 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1503
1504 tu_cs_emit_regs(cs,
1505 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1506 .writemask = vs->inputs[input_idx].compmask,
1507 .regid = vs->inputs[input_idx].regid));
1508
1509 vfd_decode_idx++;
1510 }
1511
1512 tu_cs_emit_regs(cs,
1513 A6XX_VFD_CONTROL_0(
1514 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1515 .decode_cnt = vfd_decode_idx));
1516 }
1517
1518 static uint32_t
1519 tu6_guardband_adj(uint32_t v)
1520 {
1521 if (v > 256)
1522 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1523 else
1524 return 511;
1525 }
1526
1527 void
1528 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1529 {
1530 float offsets[3];
1531 float scales[3];
1532 scales[0] = viewport->width / 2.0f;
1533 scales[1] = viewport->height / 2.0f;
1534 scales[2] = viewport->maxDepth - viewport->minDepth;
1535 offsets[0] = viewport->x + scales[0];
1536 offsets[1] = viewport->y + scales[1];
1537 offsets[2] = viewport->minDepth;
1538
1539 VkOffset2D min;
1540 VkOffset2D max;
1541 min.x = (int32_t) viewport->x;
1542 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1543 if (viewport->height >= 0.0f) {
1544 min.y = (int32_t) viewport->y;
1545 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1546 } else {
1547 min.y = (int32_t)(viewport->y + viewport->height);
1548 max.y = (int32_t) ceilf(viewport->y);
1549 }
1550 /* the spec allows viewport->height to be 0.0f */
1551 if (min.y == max.y)
1552 max.y++;
1553 assert(min.x >= 0 && min.x < max.x);
1554 assert(min.y >= 0 && min.y < max.y);
1555
1556 VkExtent2D guardband_adj;
1557 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1558 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1559
1560 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1561 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1562 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1563 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1564 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1565 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1566 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1567
1568 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1569 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1570 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1571 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1572 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1573
1574 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1575 tu_cs_emit(cs,
1576 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1577 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1578
1579 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1580 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1581
1582 tu_cs_emit_regs(cs,
1583 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1584 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1585
1586 tu_cs_emit_regs(cs,
1587 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1588 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1589 }
1590
1591 void
1592 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1593 {
1594 const VkOffset2D min = scissor->offset;
1595 const VkOffset2D max = {
1596 scissor->offset.x + scissor->extent.width,
1597 scissor->offset.y + scissor->extent.height,
1598 };
1599
1600 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1601 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1602 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1603 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1604 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1605 }
1606
1607 void
1608 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1609 {
1610 if (!samp_loc) {
1611 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1612 tu_cs_emit(cs, 0);
1613
1614 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1615 tu_cs_emit(cs, 0);
1616
1617 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1618 tu_cs_emit(cs, 0);
1619 return;
1620 }
1621
1622 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1623 assert(samp_loc->sampleLocationGridSize.width == 1);
1624 assert(samp_loc->sampleLocationGridSize.height == 1);
1625
1626 uint32_t sample_config =
1627 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1628 uint32_t sample_locations = 0;
1629 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1630 sample_locations |=
1631 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1632 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1633 }
1634
1635 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1636 tu_cs_emit(cs, sample_config);
1637 tu_cs_emit(cs, sample_locations);
1638
1639 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1640 tu_cs_emit(cs, sample_config);
1641 tu_cs_emit(cs, sample_locations);
1642
1643 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1644 tu_cs_emit(cs, sample_config);
1645 tu_cs_emit(cs, sample_locations);
1646 }
1647
1648 static void
1649 tu6_emit_gras_unknowns(struct tu_cs *cs)
1650 {
1651 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1652 tu_cs_emit(cs, 0x0);
1653 }
1654
1655 static void
1656 tu6_emit_point_size(struct tu_cs *cs)
1657 {
1658 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1659 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1660 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1661 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1662 }
1663
1664 static uint32_t
1665 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1666 VkSampleCountFlagBits samples)
1667 {
1668 uint32_t gras_su_cntl = 0;
1669
1670 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1671 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1672 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1673 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1674
1675 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1676 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1677
1678 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1679
1680 if (rast_info->depthBiasEnable)
1681 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1682
1683 if (samples > VK_SAMPLE_COUNT_1_BIT)
1684 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1685
1686 return gras_su_cntl;
1687 }
1688
1689 void
1690 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1691 uint32_t gras_su_cntl,
1692 float line_width)
1693 {
1694 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1695 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1696
1697 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1698 tu_cs_emit(cs, gras_su_cntl);
1699 }
1700
1701 void
1702 tu6_emit_depth_bias(struct tu_cs *cs,
1703 float constant_factor,
1704 float clamp,
1705 float slope_factor)
1706 {
1707 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1708 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1709 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1710 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1711 }
1712
1713 static void
1714 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1715 {
1716 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1717 tu_cs_emit(cs, 0);
1718 }
1719
1720 static void
1721 tu6_emit_depth_control(struct tu_cs *cs,
1722 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1723 const VkPipelineRasterizationStateCreateInfo *rast_info)
1724 {
1725 assert(!ds_info->depthBoundsTestEnable);
1726
1727 uint32_t rb_depth_cntl = 0;
1728 if (ds_info->depthTestEnable) {
1729 rb_depth_cntl |=
1730 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1731 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1732 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1733
1734 if (rast_info->depthClampEnable)
1735 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1736
1737 if (ds_info->depthWriteEnable)
1738 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1739 }
1740
1741 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1742 tu_cs_emit(cs, rb_depth_cntl);
1743 }
1744
1745 static void
1746 tu6_emit_stencil_control(struct tu_cs *cs,
1747 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1748 {
1749 uint32_t rb_stencil_control = 0;
1750 if (ds_info->stencilTestEnable) {
1751 const VkStencilOpState *front = &ds_info->front;
1752 const VkStencilOpState *back = &ds_info->back;
1753 rb_stencil_control |=
1754 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1755 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1756 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1757 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1758 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1759 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1760 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1761 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1762 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1763 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1764 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1765 }
1766
1767 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1768 tu_cs_emit(cs, rb_stencil_control);
1769 }
1770
1771 void
1772 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1773 {
1774 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1775 tu_cs_emit(
1776 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1777 }
1778
1779 void
1780 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1781 {
1782 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1783 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1784 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1785 }
1786
1787 void
1788 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1789 {
1790 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1791 tu_cs_emit(cs,
1792 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1793 }
1794
1795 static uint32_t
1796 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1797 bool has_alpha)
1798 {
1799 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1800 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1801 has_alpha ? att->srcColorBlendFactor
1802 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1803 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1804 has_alpha ? att->dstColorBlendFactor
1805 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1806 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1807 const enum adreno_rb_blend_factor src_alpha_factor =
1808 tu6_blend_factor(att->srcAlphaBlendFactor);
1809 const enum adreno_rb_blend_factor dst_alpha_factor =
1810 tu6_blend_factor(att->dstAlphaBlendFactor);
1811
1812 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1813 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1814 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1815 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1816 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1817 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1818 }
1819
1820 static uint32_t
1821 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1822 uint32_t rb_mrt_control_rop,
1823 bool is_int,
1824 bool has_alpha)
1825 {
1826 uint32_t rb_mrt_control =
1827 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1828
1829 /* ignore blending and logic op for integer attachments */
1830 if (is_int) {
1831 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1832 return rb_mrt_control;
1833 }
1834
1835 rb_mrt_control |= rb_mrt_control_rop;
1836
1837 if (att->blendEnable) {
1838 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1839
1840 if (has_alpha)
1841 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1842 }
1843
1844 return rb_mrt_control;
1845 }
1846
1847 static void
1848 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1849 const VkPipelineColorBlendStateCreateInfo *blend_info,
1850 const VkFormat attachment_formats[MAX_RTS],
1851 uint32_t *blend_enable_mask)
1852 {
1853 *blend_enable_mask = 0;
1854
1855 bool rop_reads_dst = false;
1856 uint32_t rb_mrt_control_rop = 0;
1857 if (blend_info->logicOpEnable) {
1858 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1859 rb_mrt_control_rop =
1860 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1861 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1862 }
1863
1864 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1865 const VkPipelineColorBlendAttachmentState *att =
1866 &blend_info->pAttachments[i];
1867 const VkFormat format = attachment_formats[i];
1868
1869 uint32_t rb_mrt_control = 0;
1870 uint32_t rb_mrt_blend_control = 0;
1871 if (format != VK_FORMAT_UNDEFINED) {
1872 const bool is_int = vk_format_is_int(format);
1873 const bool has_alpha = vk_format_has_alpha(format);
1874
1875 rb_mrt_control =
1876 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1877 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1878
1879 if (att->blendEnable || rop_reads_dst)
1880 *blend_enable_mask |= 1 << i;
1881 }
1882
1883 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1884 tu_cs_emit(cs, rb_mrt_control);
1885 tu_cs_emit(cs, rb_mrt_blend_control);
1886 }
1887 }
1888
1889 static void
1890 tu6_emit_blend_control(struct tu_cs *cs,
1891 uint32_t blend_enable_mask,
1892 bool dual_src_blend,
1893 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1894 {
1895 const uint32_t sample_mask =
1896 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1897 : ((1 << msaa_info->rasterizationSamples) - 1);
1898
1899 tu_cs_emit_regs(cs,
1900 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1901 .dual_color_in_enable = dual_src_blend,
1902 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1903 .unk8 = true));
1904
1905 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1906 tu_cs_emit_regs(cs,
1907 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1908 .independent_blend = true,
1909 .sample_mask = sample_mask,
1910 .dual_color_in_enable = dual_src_blend,
1911 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1912 .alpha_to_one = msaa_info->alphaToOneEnable));
1913 }
1914
1915 void
1916 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1917 {
1918 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1919 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1920 }
1921
1922 static VkResult
1923 tu_pipeline_create(struct tu_device *dev,
1924 struct tu_pipeline_layout *layout,
1925 bool compute,
1926 const VkAllocationCallbacks *pAllocator,
1927 struct tu_pipeline **out_pipeline)
1928 {
1929 struct tu_pipeline *pipeline =
1930 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
1931 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1932 if (!pipeline)
1933 return VK_ERROR_OUT_OF_HOST_MEMORY;
1934
1935 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
1936
1937 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1938 * that LOAD_STATE can potentially take up a large amount of space so we
1939 * calculate its size explicitly.
1940 */
1941 unsigned load_state_size = tu6_load_state_size(layout, compute);
1942 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size);
1943 if (result != VK_SUCCESS) {
1944 vk_free2(&dev->alloc, pAllocator, pipeline);
1945 return result;
1946 }
1947
1948 *out_pipeline = pipeline;
1949
1950 return VK_SUCCESS;
1951 }
1952
1953 static void
1954 tu_pipeline_shader_key_init(struct ir3_shader_key *key,
1955 const VkGraphicsPipelineCreateInfo *pipeline_info)
1956 {
1957 bool has_gs = false;
1958 bool msaa = false;
1959 if (pipeline_info) {
1960 for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
1961 if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
1962 has_gs = true;
1963 break;
1964 }
1965 }
1966
1967 const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
1968 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
1969 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1970 if (!pipeline_info->pRasterizationState->rasterizerDiscardEnable &&
1971 (msaa_info->rasterizationSamples > 1 ||
1972 /* also set msaa key when sample location is not the default
1973 * since this affects varying interpolation */
1974 (sample_locations && sample_locations->sampleLocationsEnable))) {
1975 msaa = true;
1976 }
1977 }
1978
1979 /* TODO: Populate the remaining fields of ir3_shader_key. */
1980 *key = (struct ir3_shader_key) {
1981 .has_gs = has_gs,
1982 .msaa = msaa,
1983 };
1984 }
1985
1986 static VkResult
1987 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1988 {
1989 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1990 NULL
1991 };
1992 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1993 gl_shader_stage stage =
1994 vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage);
1995 stage_infos[stage] = &builder->create_info->pStages[i];
1996 }
1997
1998 struct ir3_shader_key key;
1999 tu_pipeline_shader_key_init(&key, builder->create_info);
2000
2001 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2002 stage < MESA_SHADER_STAGES; stage++) {
2003 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
2004 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
2005 continue;
2006
2007 struct tu_shader *shader =
2008 tu_shader_create(builder->device, stage, stage_info, builder->layout,
2009 builder->alloc);
2010 if (!shader)
2011 return VK_ERROR_OUT_OF_HOST_MEMORY;
2012
2013 builder->shaders[stage] = shader;
2014 }
2015
2016 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
2017 stage > MESA_SHADER_NONE; stage--) {
2018 if (!builder->shaders[stage])
2019 continue;
2020
2021 bool created;
2022 builder->variants[stage] =
2023 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2024 &key, false, &created);
2025 if (!builder->variants[stage])
2026 return VK_ERROR_OUT_OF_HOST_MEMORY;
2027
2028 builder->shader_offsets[stage] = builder->shader_total_size;
2029 builder->shader_total_size +=
2030 sizeof(uint32_t) * builder->variants[stage]->info.sizedwords;
2031 }
2032
2033 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2034 struct ir3_shader_variant *variant;
2035
2036 if (vs->ir3_shader->stream_output.num_outputs) {
2037 variant = builder->variants[MESA_SHADER_VERTEX];
2038 } else {
2039 bool created;
2040 variant = ir3_shader_get_variant(vs->ir3_shader, &key,
2041 true, &created);
2042 if (!variant)
2043 return VK_ERROR_OUT_OF_HOST_MEMORY;
2044 }
2045
2046 builder->binning_vs_offset = builder->shader_total_size;
2047 builder->shader_total_size +=
2048 sizeof(uint32_t) * variant->info.sizedwords;
2049 builder->binning_variant = variant;
2050
2051 return VK_SUCCESS;
2052 }
2053
2054 static VkResult
2055 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
2056 struct tu_pipeline *pipeline)
2057 {
2058 struct tu_bo *bo = &pipeline->program.binary_bo;
2059
2060 VkResult result =
2061 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
2062 if (result != VK_SUCCESS)
2063 return result;
2064
2065 result = tu_bo_map(builder->device, bo);
2066 if (result != VK_SUCCESS)
2067 return result;
2068
2069 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2070 const struct ir3_shader_variant *variant = builder->variants[i];
2071 if (!variant)
2072 continue;
2073
2074 memcpy(bo->map + builder->shader_offsets[i], variant->bin,
2075 sizeof(uint32_t) * variant->info.sizedwords);
2076 }
2077
2078 if (builder->binning_variant) {
2079 const struct ir3_shader_variant *variant = builder->binning_variant;
2080 memcpy(bo->map + builder->binning_vs_offset, variant->bin,
2081 sizeof(uint32_t) * variant->info.sizedwords);
2082 }
2083
2084 return VK_SUCCESS;
2085 }
2086
2087 static void
2088 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2089 struct tu_pipeline *pipeline)
2090 {
2091 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2092 builder->create_info->pDynamicState;
2093
2094 if (!dynamic_info)
2095 return;
2096
2097 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2098 pipeline->dynamic_state.mask |=
2099 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
2100 }
2101 }
2102
2103 static void
2104 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2105 struct tu_shader *shader,
2106 struct ir3_shader_variant *v)
2107 {
2108 link->ubo_state = v->shader->ubo_state;
2109 link->const_state = v->shader->const_state;
2110 link->constlen = v->constlen;
2111 link->push_consts = shader->push_consts;
2112 }
2113
2114 static void
2115 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2116 struct tu_pipeline *pipeline)
2117 {
2118 struct tu_cs prog_cs;
2119 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2120 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
2121 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2122
2123 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2124 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
2125 pipeline->program.binning_state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2126
2127 VkShaderStageFlags stages = 0;
2128 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2129 stages |= builder->create_info->pStages[i].stage;
2130 }
2131 pipeline->active_stages = stages;
2132
2133 uint32_t desc_sets = 0;
2134 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2135 if (!builder->shaders[i])
2136 continue;
2137
2138 tu_pipeline_set_linkage(&pipeline->program.link[i],
2139 builder->shaders[i],
2140 builder->variants[i]);
2141 desc_sets |= builder->shaders[i]->active_desc_sets;
2142 }
2143 pipeline->active_desc_sets = desc_sets;
2144
2145 if (builder->shaders[MESA_SHADER_FRAGMENT]) {
2146 memcpy(pipeline->program.input_attachment_idx,
2147 builder->shaders[MESA_SHADER_FRAGMENT]->attachment_idx,
2148 sizeof(pipeline->program.input_attachment_idx));
2149 }
2150 }
2151
2152 static void
2153 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2154 struct tu_pipeline *pipeline)
2155 {
2156 const VkPipelineVertexInputStateCreateInfo *vi_info =
2157 builder->create_info->pVertexInputState;
2158 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
2159 const struct ir3_shader_variant *bs = builder->binning_variant;
2160
2161 struct tu_cs vi_cs;
2162 tu_cs_begin_sub_stream(&pipeline->cs,
2163 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2164 tu6_emit_vertex_input(&vi_cs, vs, vi_info,
2165 &pipeline->vi.bindings_used);
2166 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2167
2168 if (bs) {
2169 tu_cs_begin_sub_stream(&pipeline->cs,
2170 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2171 tu6_emit_vertex_input(
2172 &vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
2173 pipeline->vi.binning_state_ib =
2174 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2175 }
2176 }
2177
2178 static void
2179 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2180 struct tu_pipeline *pipeline)
2181 {
2182 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2183 builder->create_info->pInputAssemblyState;
2184
2185 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2186 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2187 }
2188
2189 static void
2190 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2191 struct tu_pipeline *pipeline)
2192 {
2193 /* The spec says:
2194 *
2195 * pViewportState is a pointer to an instance of the
2196 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2197 * pipeline has rasterization disabled."
2198 *
2199 * We leave the relevant registers stale in that case.
2200 */
2201 if (builder->rasterizer_discard)
2202 return;
2203
2204 const VkPipelineViewportStateCreateInfo *vp_info =
2205 builder->create_info->pViewportState;
2206
2207 struct tu_cs vp_cs;
2208 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
2209
2210 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2211 assert(vp_info->viewportCount == 1);
2212 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
2213 }
2214
2215 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2216 assert(vp_info->scissorCount == 1);
2217 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
2218 }
2219
2220 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
2221 }
2222
2223 static void
2224 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2225 struct tu_pipeline *pipeline)
2226 {
2227 const VkPipelineRasterizationStateCreateInfo *rast_info =
2228 builder->create_info->pRasterizationState;
2229
2230 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2231
2232 struct tu_cs rast_cs;
2233 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
2234
2235
2236 tu_cs_emit_regs(&rast_cs,
2237 A6XX_GRAS_CL_CNTL(
2238 .znear_clip_disable = rast_info->depthClampEnable,
2239 .zfar_clip_disable = rast_info->depthClampEnable,
2240 .unk5 = rast_info->depthClampEnable,
2241 .zero_gb_scale_z = 1,
2242 .vp_clip_code_ignore = 1));
2243 /* move to hw ctx init? */
2244 tu6_emit_gras_unknowns(&rast_cs);
2245 tu6_emit_point_size(&rast_cs);
2246
2247 const uint32_t gras_su_cntl =
2248 tu6_gras_su_cntl(rast_info, builder->samples);
2249
2250 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
2251 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
2252
2253 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
2254 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
2255 rast_info->depthBiasClamp,
2256 rast_info->depthBiasSlopeFactor);
2257 }
2258
2259 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
2260
2261 pipeline->rast.gras_su_cntl = gras_su_cntl;
2262 }
2263
2264 static void
2265 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2266 struct tu_pipeline *pipeline)
2267 {
2268 /* The spec says:
2269 *
2270 * pDepthStencilState is a pointer to an instance of the
2271 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2272 * the pipeline has rasterization disabled or if the subpass of the
2273 * render pass the pipeline is created against does not use a
2274 * depth/stencil attachment.
2275 *
2276 * Disable both depth and stencil tests if there is no ds attachment,
2277 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2278 * only the separate stencil attachment
2279 */
2280 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2281 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2282 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2283 ? builder->create_info->pDepthStencilState
2284 : &dummy_ds_info;
2285 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2286 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2287 ? ds_info : &dummy_ds_info;
2288
2289 struct tu_cs ds_cs;
2290 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2291
2292 /* move to hw ctx init? */
2293 tu6_emit_alpha_control_disable(&ds_cs);
2294
2295 tu6_emit_depth_control(&ds_cs, ds_info_depth,
2296 builder->create_info->pRasterizationState);
2297 tu6_emit_stencil_control(&ds_cs, ds_info);
2298
2299 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2300 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2301 ds_info->back.compareMask);
2302 }
2303 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2304 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2305 ds_info->back.writeMask);
2306 }
2307 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2308 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2309 ds_info->back.reference);
2310 }
2311
2312 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2313 }
2314
2315 static void
2316 tu_pipeline_builder_parse_multisample_and_color_blend(
2317 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2318 {
2319 /* The spec says:
2320 *
2321 * pMultisampleState is a pointer to an instance of the
2322 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2323 * has rasterization disabled.
2324 *
2325 * Also,
2326 *
2327 * pColorBlendState is a pointer to an instance of the
2328 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2329 * pipeline has rasterization disabled or if the subpass of the render
2330 * pass the pipeline is created against does not use any color
2331 * attachments.
2332 *
2333 * We leave the relevant registers stale when rasterization is disabled.
2334 */
2335 if (builder->rasterizer_discard)
2336 return;
2337
2338 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2339 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2340 builder->create_info->pMultisampleState;
2341 const VkPipelineColorBlendStateCreateInfo *blend_info =
2342 builder->use_color_attachments ? builder->create_info->pColorBlendState
2343 : &dummy_blend_info;
2344
2345 struct tu_cs blend_cs;
2346 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 18, &blend_cs);
2347
2348 uint32_t blend_enable_mask;
2349 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2350 builder->color_attachment_formats,
2351 &blend_enable_mask);
2352
2353 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2354 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2355
2356 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SAMPLE_LOCATIONS)) {
2357 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2358 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2359 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2360
2361 if (sample_locations && sample_locations->sampleLocationsEnable)
2362 samp_loc = &sample_locations->sampleLocationsInfo;
2363
2364 tu6_emit_sample_locations(&blend_cs, samp_loc);
2365 }
2366
2367 tu6_emit_blend_control(&blend_cs, blend_enable_mask,
2368 builder->use_dual_src_blend, msaa_info);
2369
2370 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2371 }
2372
2373 static void
2374 tu_pipeline_finish(struct tu_pipeline *pipeline,
2375 struct tu_device *dev,
2376 const VkAllocationCallbacks *alloc)
2377 {
2378 tu_cs_finish(&pipeline->cs);
2379
2380 if (pipeline->program.binary_bo.gem_handle)
2381 tu_bo_finish(dev, &pipeline->program.binary_bo);
2382 }
2383
2384 static VkResult
2385 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2386 struct tu_pipeline **pipeline)
2387 {
2388 VkResult result = tu_pipeline_create(builder->device, builder->layout,
2389 false, builder->alloc, pipeline);
2390 if (result != VK_SUCCESS)
2391 return result;
2392
2393 (*pipeline)->layout = builder->layout;
2394
2395 /* compile and upload shaders */
2396 result = tu_pipeline_builder_compile_shaders(builder);
2397 if (result == VK_SUCCESS)
2398 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2399 if (result != VK_SUCCESS) {
2400 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2401 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2402 *pipeline = VK_NULL_HANDLE;
2403
2404 return result;
2405 }
2406
2407 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2408 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2409 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2410 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2411 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2412 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2413 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2414 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2415 tu6_emit_load_state(*pipeline, false);
2416
2417 /* we should have reserved enough space upfront such that the CS never
2418 * grows
2419 */
2420 assert((*pipeline)->cs.bo_count == 1);
2421
2422 return VK_SUCCESS;
2423 }
2424
2425 static void
2426 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2427 {
2428 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2429 if (!builder->shaders[i])
2430 continue;
2431 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2432 }
2433 }
2434
2435 static void
2436 tu_pipeline_builder_init_graphics(
2437 struct tu_pipeline_builder *builder,
2438 struct tu_device *dev,
2439 struct tu_pipeline_cache *cache,
2440 const VkGraphicsPipelineCreateInfo *create_info,
2441 const VkAllocationCallbacks *alloc)
2442 {
2443 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2444
2445 *builder = (struct tu_pipeline_builder) {
2446 .device = dev,
2447 .cache = cache,
2448 .create_info = create_info,
2449 .alloc = alloc,
2450 .layout = layout,
2451 };
2452
2453 builder->rasterizer_discard =
2454 create_info->pRasterizationState->rasterizerDiscardEnable;
2455
2456 if (builder->rasterizer_discard) {
2457 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2458 } else {
2459 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2460
2461 const struct tu_render_pass *pass =
2462 tu_render_pass_from_handle(create_info->renderPass);
2463 const struct tu_subpass *subpass =
2464 &pass->subpasses[create_info->subpass];
2465
2466 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2467 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2468 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2469
2470 assert(subpass->color_count == 0 ||
2471 !create_info->pColorBlendState ||
2472 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2473 builder->color_attachment_count = subpass->color_count;
2474 for (uint32_t i = 0; i < subpass->color_count; i++) {
2475 const uint32_t a = subpass->color_attachments[i].attachment;
2476 if (a == VK_ATTACHMENT_UNUSED)
2477 continue;
2478
2479 builder->color_attachment_formats[i] = pass->attachments[a].format;
2480 builder->use_color_attachments = true;
2481 builder->render_components |= 0xf << (i * 4);
2482 }
2483
2484 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2485 builder->color_attachment_count++;
2486 builder->use_dual_src_blend = true;
2487 /* dual source blending has an extra fs output in the 2nd slot */
2488 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2489 builder->render_components |= 0xf << 4;
2490 }
2491 }
2492 }
2493
2494 static VkResult
2495 tu_graphics_pipeline_create(VkDevice device,
2496 VkPipelineCache pipelineCache,
2497 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2498 const VkAllocationCallbacks *pAllocator,
2499 VkPipeline *pPipeline)
2500 {
2501 TU_FROM_HANDLE(tu_device, dev, device);
2502 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2503
2504 struct tu_pipeline_builder builder;
2505 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2506 pCreateInfo, pAllocator);
2507
2508 struct tu_pipeline *pipeline = NULL;
2509 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2510 tu_pipeline_builder_finish(&builder);
2511
2512 if (result == VK_SUCCESS)
2513 *pPipeline = tu_pipeline_to_handle(pipeline);
2514 else
2515 *pPipeline = VK_NULL_HANDLE;
2516
2517 return result;
2518 }
2519
2520 VkResult
2521 tu_CreateGraphicsPipelines(VkDevice device,
2522 VkPipelineCache pipelineCache,
2523 uint32_t count,
2524 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2525 const VkAllocationCallbacks *pAllocator,
2526 VkPipeline *pPipelines)
2527 {
2528 VkResult final_result = VK_SUCCESS;
2529
2530 for (uint32_t i = 0; i < count; i++) {
2531 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2532 &pCreateInfos[i], pAllocator,
2533 &pPipelines[i]);
2534
2535 if (result != VK_SUCCESS)
2536 final_result = result;
2537 }
2538
2539 return final_result;
2540 }
2541
2542 static VkResult
2543 tu_compute_upload_shader(VkDevice device,
2544 struct tu_pipeline *pipeline,
2545 struct ir3_shader_variant *v)
2546 {
2547 TU_FROM_HANDLE(tu_device, dev, device);
2548 struct tu_bo *bo = &pipeline->program.binary_bo;
2549
2550 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2551 VkResult result =
2552 tu_bo_init_new(dev, bo, shader_size);
2553 if (result != VK_SUCCESS)
2554 return result;
2555
2556 result = tu_bo_map(dev, bo);
2557 if (result != VK_SUCCESS)
2558 return result;
2559
2560 memcpy(bo->map, v->bin, shader_size);
2561
2562 return VK_SUCCESS;
2563 }
2564
2565
2566 static VkResult
2567 tu_compute_pipeline_create(VkDevice device,
2568 VkPipelineCache _cache,
2569 const VkComputePipelineCreateInfo *pCreateInfo,
2570 const VkAllocationCallbacks *pAllocator,
2571 VkPipeline *pPipeline)
2572 {
2573 TU_FROM_HANDLE(tu_device, dev, device);
2574 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2575 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2576 VkResult result;
2577
2578 struct tu_pipeline *pipeline;
2579
2580 *pPipeline = VK_NULL_HANDLE;
2581
2582 result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline);
2583 if (result != VK_SUCCESS)
2584 return result;
2585
2586 pipeline->layout = layout;
2587
2588 struct ir3_shader_key key;
2589 tu_pipeline_shader_key_init(&key, NULL);
2590
2591 struct tu_shader *shader =
2592 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2593 if (!shader) {
2594 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2595 goto fail;
2596 }
2597
2598 bool created;
2599 struct ir3_shader_variant *v =
2600 ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
2601 if (!v)
2602 goto fail;
2603
2604 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2605 shader, v);
2606
2607 result = tu_compute_upload_shader(device, pipeline, v);
2608 if (result != VK_SUCCESS)
2609 goto fail;
2610
2611 for (int i = 0; i < 3; i++)
2612 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2613
2614 struct tu_cs prog_cs;
2615 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2616 tu6_emit_cs_config(&prog_cs, shader, v, pipeline->program.binary_bo.iova);
2617 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2618
2619 tu6_emit_load_state(pipeline, true);
2620
2621 *pPipeline = tu_pipeline_to_handle(pipeline);
2622 return VK_SUCCESS;
2623
2624 fail:
2625 if (shader)
2626 tu_shader_destroy(dev, shader, pAllocator);
2627
2628 tu_pipeline_finish(pipeline, dev, pAllocator);
2629 vk_free2(&dev->alloc, pAllocator, pipeline);
2630
2631 return result;
2632 }
2633
2634 VkResult
2635 tu_CreateComputePipelines(VkDevice device,
2636 VkPipelineCache pipelineCache,
2637 uint32_t count,
2638 const VkComputePipelineCreateInfo *pCreateInfos,
2639 const VkAllocationCallbacks *pAllocator,
2640 VkPipeline *pPipelines)
2641 {
2642 VkResult final_result = VK_SUCCESS;
2643
2644 for (uint32_t i = 0; i < count; i++) {
2645 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2646 &pCreateInfos[i],
2647 pAllocator, &pPipelines[i]);
2648 if (result != VK_SUCCESS)
2649 final_result = result;
2650 }
2651
2652 return final_result;
2653 }
2654
2655 void
2656 tu_DestroyPipeline(VkDevice _device,
2657 VkPipeline _pipeline,
2658 const VkAllocationCallbacks *pAllocator)
2659 {
2660 TU_FROM_HANDLE(tu_device, dev, _device);
2661 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2662
2663 if (!_pipeline)
2664 return;
2665
2666 tu_pipeline_finish(pipeline, dev, pAllocator);
2667 vk_free2(&dev->alloc, pAllocator, pipeline);
2668 }