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turnip: clean up primitive output state
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static void
46 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
47 enum a6xx_state_block sb, unsigned base, unsigned offset,
48 unsigned count)
49 {
50 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
51 * clear if emitting more packets will even help anything. Presumably the
52 * descriptor cache is relatively small, and these packets stop doing
53 * anything when there are too many descriptors.
54 */
55 tu_cs_emit_pkt7(cs, opcode, 3);
56 tu_cs_emit(cs,
57 CP_LOAD_STATE6_0_STATE_TYPE(st) |
58 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
59 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
60 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
61 tu_cs_emit_qw(cs, offset | (base << 28));
62 }
63
64 static unsigned
65 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
66 {
67 const unsigned load_state_size = 4;
68 unsigned size = 0;
69 for (unsigned i = 0; i < layout->num_sets; i++) {
70 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
71 for (unsigned j = 0; j < set_layout->binding_count; j++) {
72 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
73 unsigned count = 0;
74 /* Note: some users, like amber for example, pass in
75 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
76 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
77 */
78 VkShaderStageFlags stages = compute ?
79 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
80 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
81 unsigned stage_count = util_bitcount(stages);
82 switch (binding->type) {
83 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
84 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
85 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
86 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
87 /* IBO-backed resources only need one packet for all graphics stages */
88 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
89 count += 1;
90 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
91 count += 1;
92 break;
93 case VK_DESCRIPTOR_TYPE_SAMPLER:
94 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
95 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
96 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
97 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
98 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
99 /* Textures and UBO's needs a packet for each stage */
100 count = stage_count;
101 break;
102 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
103 /* Because of how we pack combined images and samplers, we
104 * currently can't use one packet for the whole array.
105 */
106 count = stage_count * binding->array_size * 2;
107 break;
108 default:
109 unreachable("bad descriptor type");
110 }
111 size += count * load_state_size;
112 }
113 }
114 return size;
115 }
116
117 static void
118 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
119 {
120 unsigned size = tu6_load_state_size(pipeline->layout, compute);
121 if (size == 0)
122 return;
123
124 struct tu_cs cs;
125 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
126
127 struct tu_pipeline_layout *layout = pipeline->layout;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 /* From 13.2.7. Descriptor Set Binding:
130 *
131 * A compatible descriptor set must be bound for all set numbers that
132 * any shaders in a pipeline access, at the time that a draw or
133 * dispatch command is recorded to execute using that pipeline.
134 * However, if none of the shaders in a pipeline statically use any
135 * bindings with a particular set number, then no descriptor set need
136 * be bound for that set number, even if the pipeline layout includes
137 * a non-trivial descriptor set layout for that set number.
138 *
139 * This means that descriptor sets unused by the pipeline may have a
140 * garbage or 0 BINDLESS_BASE register, which will cause context faults
141 * when prefetching descriptors from these sets. Skip prefetching for
142 * descriptors from them to avoid this. This is also an optimization,
143 * since these prefetches would be useless.
144 */
145 if (!(pipeline->active_desc_sets & (1u << i)))
146 continue;
147
148 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
149 for (unsigned j = 0; j < set_layout->binding_count; j++) {
150 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
151 unsigned base = i;
152 unsigned offset = binding->offset / 4;
153 /* Note: some users, like amber for example, pass in
154 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
155 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
156 */
157 VkShaderStageFlags stages = compute ?
158 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
159 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
160 unsigned count = binding->array_size;
161 if (count == 0 || stages == 0)
162 continue;
163 switch (binding->type) {
164 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
165 base = MAX_SETS;
166 offset = (layout->set[i].dynamic_offset_start +
167 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
168 /* fallthrough */
169 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
170 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
171 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
172 /* IBO-backed resources only need one packet for all graphics stages */
173 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
174 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
175 base, offset, count);
176 }
177 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
178 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
179 base, offset, count);
180 }
181 break;
182 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
183 /* nothing - input attachment doesn't use bindless */
184 break;
185 case VK_DESCRIPTOR_TYPE_SAMPLER:
186 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
187 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
188 tu_foreach_stage(stage, stages) {
189 emit_load_state(&cs, tu6_stage2opcode(stage),
190 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
191 ST6_SHADER : ST6_CONSTANTS,
192 tu6_stage2texsb(stage), base, offset, count);
193 }
194 break;
195 }
196 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
197 base = MAX_SETS;
198 offset = (layout->set[i].dynamic_offset_start +
199 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
200 /* fallthrough */
201 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
202 tu_foreach_stage(stage, stages) {
203 emit_load_state(&cs, tu6_stage2opcode(stage), ST6_UBO,
204 tu6_stage2shadersb(stage), base, offset, count);
205 }
206 break;
207 }
208 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
209 tu_foreach_stage(stage, stages) {
210 /* TODO: We could emit less CP_LOAD_STATE6 if we used
211 * struct-of-arrays instead of array-of-structs.
212 */
213 for (unsigned i = 0; i < count; i++) {
214 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
215 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
216 emit_load_state(&cs, tu6_stage2opcode(stage),
217 ST6_CONSTANTS, tu6_stage2texsb(stage),
218 base, tex_offset, 1);
219 emit_load_state(&cs, tu6_stage2opcode(stage),
220 ST6_SHADER, tu6_stage2texsb(stage),
221 base, sam_offset, 1);
222 }
223 }
224 break;
225 }
226 default:
227 unreachable("bad descriptor type");
228 }
229 }
230 }
231
232 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
233 }
234
235 struct tu_pipeline_builder
236 {
237 struct tu_device *device;
238 struct tu_pipeline_cache *cache;
239 struct tu_pipeline_layout *layout;
240 const VkAllocationCallbacks *alloc;
241 const VkGraphicsPipelineCreateInfo *create_info;
242
243 struct tu_shader *shaders[MESA_SHADER_STAGES];
244 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
245 struct ir3_shader_variant *binning_variant;
246 uint64_t shader_iova[MESA_SHADER_STAGES];
247 uint64_t binning_vs_iova;
248
249 bool rasterizer_discard;
250 /* these states are affectd by rasterizer_discard */
251 VkSampleCountFlagBits samples;
252 bool use_color_attachments;
253 bool use_dual_src_blend;
254 uint32_t color_attachment_count;
255 VkFormat color_attachment_formats[MAX_RTS];
256 VkFormat depth_attachment_format;
257 uint32_t render_components;
258 };
259
260 static bool
261 tu_logic_op_reads_dst(VkLogicOp op)
262 {
263 switch (op) {
264 case VK_LOGIC_OP_CLEAR:
265 case VK_LOGIC_OP_COPY:
266 case VK_LOGIC_OP_COPY_INVERTED:
267 case VK_LOGIC_OP_SET:
268 return false;
269 default:
270 return true;
271 }
272 }
273
274 static VkBlendFactor
275 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
276 {
277 /* treat dst alpha as 1.0 and avoid reading it */
278 switch (factor) {
279 case VK_BLEND_FACTOR_DST_ALPHA:
280 return VK_BLEND_FACTOR_ONE;
281 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
282 return VK_BLEND_FACTOR_ZERO;
283 default:
284 return factor;
285 }
286 }
287
288 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
289 {
290 switch (factor) {
291 case VK_BLEND_FACTOR_SRC1_COLOR:
292 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
293 case VK_BLEND_FACTOR_SRC1_ALPHA:
294 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
295 return true;
296 default:
297 return false;
298 }
299 }
300
301 static bool
302 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
303 {
304 if (!info)
305 return false;
306
307 for (unsigned i = 0; i < info->attachmentCount; i++) {
308 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
309 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
310 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
311 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
312 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
313 return true;
314 }
315
316 return false;
317 }
318
319 void
320 tu6_emit_xs_config(struct tu_cs *cs,
321 gl_shader_stage stage, /* xs->type, but xs may be NULL */
322 const struct ir3_shader_variant *xs,
323 uint64_t binary_iova)
324 {
325 static const struct xs_config {
326 uint16_t reg_sp_xs_ctrl;
327 uint16_t reg_sp_xs_config;
328 uint16_t reg_hlsq_xs_ctrl;
329 uint16_t reg_sp_vs_obj_start;
330 } xs_config[] = {
331 [MESA_SHADER_VERTEX] = {
332 REG_A6XX_SP_VS_CTRL_REG0,
333 REG_A6XX_SP_VS_CONFIG,
334 REG_A6XX_HLSQ_VS_CNTL,
335 REG_A6XX_SP_VS_OBJ_START_LO,
336 },
337 [MESA_SHADER_TESS_CTRL] = {
338 REG_A6XX_SP_HS_CTRL_REG0,
339 REG_A6XX_SP_HS_CONFIG,
340 REG_A6XX_HLSQ_HS_CNTL,
341 REG_A6XX_SP_HS_OBJ_START_LO,
342 },
343 [MESA_SHADER_TESS_EVAL] = {
344 REG_A6XX_SP_DS_CTRL_REG0,
345 REG_A6XX_SP_DS_CONFIG,
346 REG_A6XX_HLSQ_DS_CNTL,
347 REG_A6XX_SP_DS_OBJ_START_LO,
348 },
349 [MESA_SHADER_GEOMETRY] = {
350 REG_A6XX_SP_GS_CTRL_REG0,
351 REG_A6XX_SP_GS_CONFIG,
352 REG_A6XX_HLSQ_GS_CNTL,
353 REG_A6XX_SP_GS_OBJ_START_LO,
354 },
355 [MESA_SHADER_FRAGMENT] = {
356 REG_A6XX_SP_FS_CTRL_REG0,
357 REG_A6XX_SP_FS_CONFIG,
358 REG_A6XX_HLSQ_FS_CNTL,
359 REG_A6XX_SP_FS_OBJ_START_LO,
360 },
361 [MESA_SHADER_COMPUTE] = {
362 REG_A6XX_SP_CS_CTRL_REG0,
363 REG_A6XX_SP_CS_CONFIG,
364 REG_A6XX_HLSQ_CS_CNTL,
365 REG_A6XX_SP_CS_OBJ_START_LO,
366 },
367 };
368 const struct xs_config *cfg = &xs_config[stage];
369
370 if (!xs) {
371 /* shader stage disabled */
372 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
373 tu_cs_emit(cs, 0);
374
375 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
376 tu_cs_emit(cs, 0);
377 return;
378 }
379
380 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
381 enum a3xx_threadsize threadsize = FOUR_QUADS;
382
383 /* TODO:
384 * the "threadsize" field may have nothing to do with threadsize,
385 * use a value that matches the blob until it is figured out
386 */
387 if (xs->type == MESA_SHADER_GEOMETRY)
388 threadsize = TWO_QUADS;
389
390 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
391 tu_cs_emit(cs,
392 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
393 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
394 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs->info.max_half_reg + 1) |
395 COND(xs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
396 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
397 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
398 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
399 /* only fragment shader sets VARYING bit */
400 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
401 /* unknown bit, seems unnecessary */
402 COND(is_fs, 0x1000000));
403
404 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
405 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
406 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
407 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
408 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
409 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
410 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
411 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
412 tu_cs_emit(cs, xs->instrlen);
413
414 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
415 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) |
416 A6XX_HLSQ_VS_CNTL_ENABLED);
417
418 /* emit program binary
419 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
420 */
421
422 assert((binary_iova & 0x7f) == 0);
423
424 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
425 tu_cs_emit_qw(cs, binary_iova);
426
427 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
428 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
429 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
430 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
431 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
432 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
433 tu_cs_emit_qw(cs, binary_iova);
434
435 /* emit immediates */
436
437 const struct ir3_const_state *const_state = ir3_const_state(xs);
438 uint32_t base = const_state->offsets.immediate;
439 int size = const_state->immediates_count;
440
441 /* truncate size to avoid writing constants that shader
442 * does not use:
443 */
444 size = MIN2(size + base, xs->constlen) - base;
445
446 if (size <= 0)
447 return;
448
449 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + size * 4);
450 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
451 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
452 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
453 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
454 CP_LOAD_STATE6_0_NUM_UNIT(size));
455 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
456 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
457
458 for (unsigned i = 0; i < size; i++) {
459 tu_cs_emit(cs, const_state->immediates[i].val[0]);
460 tu_cs_emit(cs, const_state->immediates[i].val[1]);
461 tu_cs_emit(cs, const_state->immediates[i].val[2]);
462 tu_cs_emit(cs, const_state->immediates[i].val[3]);
463 }
464 }
465
466 static void
467 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
468 const struct ir3_shader_variant *v,
469 uint32_t binary_iova)
470 {
471 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
472 tu_cs_emit(cs, 0xff);
473
474 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
475
476 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
477 tu_cs_emit(cs, 0x41);
478
479 uint32_t local_invocation_id =
480 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
481 uint32_t work_group_id =
482 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
483
484 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
485 tu_cs_emit(cs,
486 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
487 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
488 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
489 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
490 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
491 }
492
493 static void
494 tu6_emit_vs_system_values(struct tu_cs *cs,
495 const struct ir3_shader_variant *vs,
496 const struct ir3_shader_variant *hs,
497 const struct ir3_shader_variant *ds,
498 const struct ir3_shader_variant *gs,
499 bool primid_passthru)
500 {
501 const uint32_t vertexid_regid =
502 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
503 const uint32_t instanceid_regid =
504 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
505 const uint32_t tess_coord_x_regid = hs ?
506 ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD) :
507 regid(63, 0);
508 const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ?
509 tess_coord_x_regid + 1 :
510 regid(63, 0);
511 const uint32_t hs_patch_regid = hs ?
512 ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
513 regid(63, 0);
514 const uint32_t ds_patch_regid = hs ?
515 ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
516 regid(63, 0);
517 const uint32_t hs_invocation_regid = hs ?
518 ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) :
519 regid(63, 0);
520 const uint32_t primitiveid_regid = gs ?
521 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
522 regid(63, 0);
523 const uint32_t gsheader_regid = gs ?
524 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
525 regid(63, 0);
526
527 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
528 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
529 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
530 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
531 0xfc000000);
532 tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
533 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
534 tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
535 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
536 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
537 0xfc);
538 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
539 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
540 0xfc00); /* VFD_CONTROL_5 */
541 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
542 }
543
544 /* Add any missing varyings needed for stream-out. Otherwise varyings not
545 * used by fragment shader will be stripped out.
546 */
547 static void
548 tu6_link_streamout(struct ir3_shader_linkage *l,
549 const struct ir3_shader_variant *v)
550 {
551 const struct ir3_stream_output_info *info = &v->shader->stream_output;
552
553 /*
554 * First, any stream-out varyings not already in linkage map (ie. also
555 * consumed by frag shader) need to be added:
556 */
557 for (unsigned i = 0; i < info->num_outputs; i++) {
558 const struct ir3_stream_output *out = &info->output[i];
559 unsigned compmask =
560 (1 << (out->num_components + out->start_component)) - 1;
561 unsigned k = out->register_index;
562 unsigned idx, nextloc = 0;
563
564 /* psize/pos need to be the last entries in linkage map, and will
565 * get added link_stream_out, so skip over them:
566 */
567 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
568 v->outputs[k].slot == VARYING_SLOT_POS)
569 continue;
570
571 for (idx = 0; idx < l->cnt; idx++) {
572 if (l->var[idx].regid == v->outputs[k].regid)
573 break;
574 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
575 }
576
577 /* add if not already in linkage map: */
578 if (idx == l->cnt)
579 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
580
581 /* expand component-mask if needed, ie streaming out all components
582 * but frag shader doesn't consume all components:
583 */
584 if (compmask & ~l->var[idx].compmask) {
585 l->var[idx].compmask |= compmask;
586 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
587 util_last_bit(l->var[idx].compmask));
588 }
589 }
590 }
591
592 static void
593 tu6_setup_streamout(struct tu_cs *cs,
594 const struct ir3_shader_variant *v,
595 struct ir3_shader_linkage *l)
596 {
597 const struct ir3_stream_output_info *info = &v->shader->stream_output;
598 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2] = {};
599 uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {};
600 uint32_t prog_count = align(l->max_loc, 2) / 2;
601
602 /* TODO: streamout state should be in a non-GMEM draw state */
603
604 /* no streamout: */
605 if (info->num_outputs == 0) {
606 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
607 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
608 tu_cs_emit(cs, 0);
609 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
610 tu_cs_emit(cs, 0);
611 return;
612 }
613
614 /* is there something to do with info->stride[i]? */
615
616 for (unsigned i = 0; i < info->num_outputs; i++) {
617 const struct ir3_stream_output *out = &info->output[i];
618 unsigned k = out->register_index;
619 unsigned idx;
620
621 /* Skip it, if there's an unused reg in the middle of outputs. */
622 if (v->outputs[k].regid == INVALID_REG)
623 continue;
624
625 ncomp[out->output_buffer] += out->num_components;
626
627 /* linkage map sorted by order frag shader wants things, so
628 * a bit less ideal here..
629 */
630 for (idx = 0; idx < l->cnt; idx++)
631 if (l->var[idx].regid == v->outputs[k].regid)
632 break;
633
634 debug_assert(idx < l->cnt);
635
636 for (unsigned j = 0; j < out->num_components; j++) {
637 unsigned c = j + out->start_component;
638 unsigned loc = l->var[idx].loc + c;
639 unsigned off = j + out->dst_offset; /* in dwords */
640
641 if (loc & 1) {
642 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
643 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
644 A6XX_VPC_SO_PROG_B_OFF(off * 4);
645 } else {
646 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
647 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
648 A6XX_VPC_SO_PROG_A_OFF(off * 4);
649 }
650 }
651 }
652
653 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count);
654 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
655 tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE |
656 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
657 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
658 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
659 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
660 for (uint32_t i = 0; i < 4; i++) {
661 tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
662 tu_cs_emit(cs, ncomp[i]);
663 }
664 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
665 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
666 tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
667 for (uint32_t i = 0; i < prog_count; i++) {
668 tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
669 tu_cs_emit(cs, prog[i]);
670 }
671 }
672
673 static void
674 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
675 enum a6xx_state_block block, uint32_t offset,
676 uint32_t size, uint32_t *dwords) {
677 assert(size % 4 == 0);
678
679 tu_cs_emit_pkt7(cs, opcode, 3 + size);
680 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
681 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
682 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
683 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
684 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
685
686 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
687 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
688 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
689
690 tu_cs_emit_array(cs, dwords, size);
691 }
692
693 static void
694 tu6_emit_link_map(struct tu_cs *cs,
695 const struct ir3_shader_variant *producer,
696 const struct ir3_shader_variant *consumer,
697 enum a6xx_state_block sb)
698 {
699 const struct ir3_const_state *const_state = ir3_const_state(consumer);
700 uint32_t base = const_state->offsets.primitive_map;
701 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
702 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
703 int size = DIV_ROUND_UP(num_loc, 4);
704
705 size = (MIN2(size + base, consumer->constlen) - base) * 4;
706 if (size <= 0)
707 return;
708
709 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, sb, 0, size,
710 patch_locs);
711 }
712
713 static uint16_t
714 gl_primitive_to_tess(uint16_t primitive) {
715 switch (primitive) {
716 case GL_POINTS:
717 return TESS_POINTS;
718 case GL_LINE_STRIP:
719 return TESS_LINES;
720 case GL_TRIANGLE_STRIP:
721 return TESS_CW_TRIS;
722 default:
723 unreachable("");
724 }
725 }
726
727 void
728 tu6_emit_vpc(struct tu_cs *cs,
729 const struct ir3_shader_variant *vs,
730 const struct ir3_shader_variant *hs,
731 const struct ir3_shader_variant *ds,
732 const struct ir3_shader_variant *gs,
733 const struct ir3_shader_variant *fs)
734 {
735 /* note: doesn't compile as static because of the array regs.. */
736 const struct reg_config {
737 uint16_t reg_sp_xs_out_reg;
738 uint16_t reg_sp_xs_vpc_dst_reg;
739 uint16_t reg_vpc_xs_pack;
740 uint16_t reg_vpc_xs_clip_cntl;
741 uint16_t reg_gras_xs_cl_cntl;
742 uint16_t reg_pc_xs_out_cntl;
743 uint16_t reg_sp_xs_primitive_cntl;
744 uint16_t reg_vpc_xs_layer_cntl;
745 uint16_t reg_gras_xs_layer_cntl;
746 } reg_config[] = {
747 [MESA_SHADER_VERTEX] = {
748 REG_A6XX_SP_VS_OUT_REG(0),
749 REG_A6XX_SP_VS_VPC_DST_REG(0),
750 REG_A6XX_VPC_VS_PACK,
751 REG_A6XX_VPC_VS_CLIP_CNTL,
752 REG_A6XX_GRAS_VS_CL_CNTL,
753 REG_A6XX_PC_VS_OUT_CNTL,
754 REG_A6XX_SP_VS_PRIMITIVE_CNTL,
755 REG_A6XX_VPC_VS_LAYER_CNTL,
756 REG_A6XX_GRAS_VS_LAYER_CNTL
757 },
758 [MESA_SHADER_TESS_EVAL] = {
759 REG_A6XX_SP_DS_OUT_REG(0),
760 REG_A6XX_SP_DS_VPC_DST_REG(0),
761 REG_A6XX_VPC_DS_PACK,
762 REG_A6XX_VPC_DS_CLIP_CNTL,
763 REG_A6XX_GRAS_DS_CL_CNTL,
764 REG_A6XX_PC_DS_OUT_CNTL,
765 REG_A6XX_SP_DS_PRIMITIVE_CNTL,
766 REG_A6XX_VPC_DS_LAYER_CNTL,
767 REG_A6XX_GRAS_DS_LAYER_CNTL
768 },
769 [MESA_SHADER_GEOMETRY] = {
770 REG_A6XX_SP_GS_OUT_REG(0),
771 REG_A6XX_SP_GS_VPC_DST_REG(0),
772 REG_A6XX_VPC_GS_PACK,
773 REG_A6XX_VPC_GS_CLIP_CNTL,
774 REG_A6XX_GRAS_GS_CL_CNTL,
775 REG_A6XX_PC_GS_OUT_CNTL,
776 REG_A6XX_SP_GS_PRIMITIVE_CNTL,
777 REG_A6XX_VPC_GS_LAYER_CNTL,
778 REG_A6XX_GRAS_GS_LAYER_CNTL
779 },
780 };
781
782 const struct ir3_shader_variant *last_shader;
783 if (gs) {
784 last_shader = gs;
785 } else if (hs) {
786 last_shader = ds;
787 } else {
788 last_shader = vs;
789 }
790
791 const struct reg_config *cfg = &reg_config[last_shader->type];
792
793 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
794 if (fs)
795 ir3_link_shaders(&linkage, last_shader, fs, true);
796
797 if (last_shader->shader->stream_output.num_outputs)
798 tu6_link_streamout(&linkage, last_shader);
799
800 /* We do this after linking shaders in order to know whether PrimID
801 * passthrough needs to be enabled.
802 */
803 bool primid_passthru = linkage.primid_loc != 0xff;
804 tu6_emit_vs_system_values(cs, vs, hs, ds, gs, primid_passthru);
805
806 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
807 tu_cs_emit(cs, ~linkage.varmask[0]);
808 tu_cs_emit(cs, ~linkage.varmask[1]);
809 tu_cs_emit(cs, ~linkage.varmask[2]);
810 tu_cs_emit(cs, ~linkage.varmask[3]);
811
812 /* a6xx finds position/pointsize at the end */
813 const uint32_t position_regid =
814 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
815 const uint32_t pointsize_regid =
816 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
817 const uint32_t layer_regid = gs ?
818 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
819 uint32_t primitive_regid = gs ?
820 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) : regid(63, 0);
821 uint32_t flags_regid = gs ?
822 ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3) : 0;
823
824 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
825 if (layer_regid != regid(63, 0)) {
826 layer_loc = linkage.max_loc;
827 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
828 }
829 if (position_regid != regid(63, 0)) {
830 position_loc = linkage.max_loc;
831 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
832 }
833 if (pointsize_regid != regid(63, 0)) {
834 pointsize_loc = linkage.max_loc;
835 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
836 }
837
838 tu6_setup_streamout(cs, last_shader, &linkage);
839
840 /* map outputs of the last shader to VPC */
841 assert(linkage.cnt <= 32);
842 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
843 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
844 uint32_t sp_out[16];
845 uint32_t sp_vpc_dst[8];
846 for (uint32_t i = 0; i < linkage.cnt; i++) {
847 ((uint16_t *) sp_out)[i] =
848 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
849 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
850 ((uint8_t *) sp_vpc_dst)[i] =
851 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
852 }
853
854 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_out_reg, sp_out_count);
855 tu_cs_emit_array(cs, sp_out, sp_out_count);
856
857 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_vpc_dst_reg, sp_vpc_dst_count);
858 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
859
860 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_pack, 1);
861 tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
862 A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) |
863 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc));
864
865 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_clip_cntl, 1);
866 tu_cs_emit(cs, 0xffff00);
867
868 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_cl_cntl, 1);
869 tu_cs_emit(cs, 0);
870
871 tu_cs_emit_pkt4(cs, cfg->reg_pc_xs_out_cntl, 1);
872 tu_cs_emit(cs, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
873 CONDREG(pointsize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
874 CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
875 CONDREG(primitive_regid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID));
876
877 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_primitive_cntl, 1);
878 tu_cs_emit(cs, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt) |
879 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
880
881 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_layer_cntl, 1);
882 tu_cs_emit(cs, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
883
884 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_layer_cntl, 1);
885 tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
886
887 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
888 tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
889
890 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
891 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
892 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
893 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
894 A6XX_VPC_CNTL_0_UNKLOC(0xff));
895
896 if (hs) {
897 shader_info *hs_info = &hs->shader->nir->info;
898 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
899 tu_cs_emit(cs, hs_info->tess.tcs_vertices_out);
900
901 /* Total attribute slots in HS incoming patch. */
902 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9801, 1);
903 tu_cs_emit(cs,
904 hs_info->tess.tcs_vertices_out * vs->output_size / 4);
905
906 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
907 tu_cs_emit(cs, vs->output_size);
908 /* In SPIR-V generated from GLSL, the tessellation primitive params are
909 * are specified in the tess eval shader, but in SPIR-V generated from
910 * HLSL, they are specified in the tess control shader. */
911 shader_info *tess_info =
912 ds->shader->nir->info.tess.spacing == TESS_SPACING_UNSPECIFIED ?
913 &hs->shader->nir->info : &ds->shader->nir->info;
914 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_CNTL, 1);
915 uint32_t output;
916 if (tess_info->tess.point_mode)
917 output = TESS_POINTS;
918 else if (tess_info->tess.primitive_mode == GL_ISOLINES)
919 output = TESS_LINES;
920 else if (tess_info->tess.ccw)
921 output = TESS_CCW_TRIS;
922 else
923 output = TESS_CW_TRIS;
924
925 enum a6xx_tess_spacing spacing;
926 switch (tess_info->tess.spacing) {
927 case TESS_SPACING_EQUAL:
928 spacing = TESS_EQUAL;
929 break;
930 case TESS_SPACING_FRACTIONAL_ODD:
931 spacing = TESS_FRACTIONAL_ODD;
932 break;
933 case TESS_SPACING_FRACTIONAL_EVEN:
934 spacing = TESS_FRACTIONAL_EVEN;
935 break;
936 case TESS_SPACING_UNSPECIFIED:
937 default:
938 unreachable("invalid tess spacing");
939 }
940 tu_cs_emit(cs, A6XX_PC_TESS_CNTL_SPACING(spacing) |
941 A6XX_PC_TESS_CNTL_OUTPUT(output));
942
943 tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
944 tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER);
945 }
946
947
948 if (gs) {
949 uint32_t vertices_out, invocations, output, vec4_size;
950 /* this detects the tu_clear_blit path, which doesn't set ->nir */
951 if (gs->shader->nir) {
952 if (hs) {
953 tu6_emit_link_map(cs, ds, gs, SB6_GS_SHADER);
954 } else {
955 tu6_emit_link_map(cs, vs, gs, SB6_GS_SHADER);
956 }
957 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
958 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
959 invocations = gs->shader->nir->info.gs.invocations - 1;
960 /* Size of per-primitive alloction in ldlw memory in vec4s. */
961 vec4_size = gs->shader->nir->info.gs.vertices_in *
962 DIV_ROUND_UP(vs->output_size, 4);
963 } else {
964 vertices_out = 3;
965 output = TESS_CW_TRIS;
966 invocations = 0;
967 vec4_size = 0;
968 }
969
970 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
971 tu_cs_emit(cs,
972 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
973 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
974 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
975
976 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
977 tu_cs_emit(cs, 0);
978
979 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
980 tu_cs_emit(cs, 0xff);
981
982 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
983 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
984
985 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
986 tu_cs_emit(cs, 0);
987
988 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
989 tu_cs_emit(cs, vs->output_size);
990 }
991 }
992
993 static int
994 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
995 uint32_t index,
996 uint8_t *interp_mode,
997 uint8_t *ps_repl_mode)
998 {
999 enum
1000 {
1001 INTERP_SMOOTH = 0,
1002 INTERP_FLAT = 1,
1003 INTERP_ZERO = 2,
1004 INTERP_ONE = 3,
1005 };
1006 enum
1007 {
1008 PS_REPL_NONE = 0,
1009 PS_REPL_S = 1,
1010 PS_REPL_T = 2,
1011 PS_REPL_ONE_MINUS_T = 3,
1012 };
1013
1014 const uint32_t compmask = fs->inputs[index].compmask;
1015
1016 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1017 * fourth component occupy three consecutive varying slots
1018 */
1019 int shift = 0;
1020 *interp_mode = 0;
1021 *ps_repl_mode = 0;
1022 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1023 if (compmask & 0x1) {
1024 *ps_repl_mode |= PS_REPL_S << shift;
1025 shift += 2;
1026 }
1027 if (compmask & 0x2) {
1028 *ps_repl_mode |= PS_REPL_T << shift;
1029 shift += 2;
1030 }
1031 if (compmask & 0x4) {
1032 *interp_mode |= INTERP_ZERO << shift;
1033 shift += 2;
1034 }
1035 if (compmask & 0x8) {
1036 *interp_mode |= INTERP_ONE << 6;
1037 shift += 2;
1038 }
1039 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1040 fs->inputs[index].rasterflat) {
1041 for (int i = 0; i < 4; i++) {
1042 if (compmask & (1 << i)) {
1043 *interp_mode |= INTERP_FLAT << shift;
1044 shift += 2;
1045 }
1046 }
1047 }
1048
1049 return shift;
1050 }
1051
1052 static void
1053 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1054 const struct ir3_shader_variant *fs)
1055 {
1056 uint32_t interp_modes[8] = { 0 };
1057 uint32_t ps_repl_modes[8] = { 0 };
1058
1059 if (fs) {
1060 for (int i = -1;
1061 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1062
1063 /* get the mode for input i */
1064 uint8_t interp_mode;
1065 uint8_t ps_repl_mode;
1066 const int bits =
1067 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1068
1069 /* OR the mode into the array */
1070 const uint32_t inloc = fs->inputs[i].inloc * 2;
1071 uint32_t n = inloc / 32;
1072 uint32_t shift = inloc % 32;
1073 interp_modes[n] |= interp_mode << shift;
1074 ps_repl_modes[n] |= ps_repl_mode << shift;
1075 if (shift + bits > 32) {
1076 n++;
1077 shift = 32 - shift;
1078
1079 interp_modes[n] |= interp_mode >> shift;
1080 ps_repl_modes[n] |= ps_repl_mode >> shift;
1081 }
1082 }
1083 }
1084
1085 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1086 tu_cs_emit_array(cs, interp_modes, 8);
1087
1088 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1089 tu_cs_emit_array(cs, ps_repl_modes, 8);
1090 }
1091
1092 void
1093 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1094 {
1095 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1096 uint32_t ij_regid[IJ_COUNT];
1097 uint32_t smask_in_regid;
1098
1099 bool sample_shading = fs->per_samp | fs->key.sample_shading;
1100 bool enable_varyings = fs->total_in > 0;
1101
1102 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1103 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1104 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1105 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1106 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1107 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
1108 ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
1109
1110 if (VALIDREG(ij_regid[IJ_LINEAR_SAMPLE]))
1111 tu_finishme("linear sample varying");
1112
1113 if (VALIDREG(ij_regid[IJ_LINEAR_CENTROID]))
1114 tu_finishme("linear centroid varying");
1115
1116 if (fs->num_sampler_prefetch > 0) {
1117 assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
1118 /* also, it seems like ij_pix is *required* to be r0.x */
1119 assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
1120 }
1121
1122 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1123 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1124 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1125 0x7000); // XXX);
1126 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1127 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1128 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1129 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1130 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1131 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1132 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1133 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1134 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1135 }
1136
1137 if (fs->num_sampler_prefetch > 0) {
1138 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1139 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1140 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1141 tu_cs_emit(cs,
1142 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1143 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1144 }
1145 }
1146
1147 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1148 tu_cs_emit(cs, 0x7);
1149 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1150 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1151 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1152 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
1153 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
1154 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
1155 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
1156 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
1157 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1158 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1159 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
1160 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
1161 tu_cs_emit(cs, 0xfc);
1162
1163 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1164 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1165
1166 bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
1167 bool need_size_persamp = false;
1168 if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
1169 if (sample_shading)
1170 need_size_persamp = true;
1171 else
1172 need_size = true;
1173 }
1174 if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
1175 need_size = true;
1176
1177 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1178 tu_cs_emit(cs,
1179 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
1180 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
1181 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
1182 COND(need_size, A6XX_GRAS_CNTL_SIZE) |
1183 COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1184 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
1185
1186 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1187 tu_cs_emit(cs,
1188 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
1189 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
1190 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
1191 COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
1192 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1193 COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1194 COND(fs->fragcoord_compmask != 0,
1195 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
1196 tu_cs_emit(cs,
1197 /* these two bits (UNK4/UNK5) relate to fragcoord
1198 * without them, fragcoord is the same for all samples
1199 */
1200 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) |
1201 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) |
1202 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1203 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1204 CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
1205 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1206
1207 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1208 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1209
1210 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1211 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1212
1213 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1214 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1215 }
1216
1217 static void
1218 tu6_emit_fs_outputs(struct tu_cs *cs,
1219 const struct ir3_shader_variant *fs,
1220 uint32_t mrt_count, bool dual_src_blend,
1221 uint32_t render_components,
1222 bool is_s8_uint)
1223 {
1224 uint32_t smask_regid, posz_regid;
1225
1226 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1227 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1228
1229 uint32_t fragdata_regid[8];
1230 if (fs->color0_mrt) {
1231 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1232 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1233 fragdata_regid[i] = fragdata_regid[0];
1234 } else {
1235 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1236 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1237 }
1238
1239 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1240 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1241 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1242 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
1243 0xfc000000);
1244 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1245
1246 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1247 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1248 // TODO we could have a mix of half and full precision outputs,
1249 // we really need to figure out half-precision from IR3_REG_HALF
1250 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1251 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1252 }
1253
1254 tu_cs_emit_regs(cs,
1255 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1256
1257 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1258 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1259 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1260 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1261 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1262
1263 tu_cs_emit_regs(cs,
1264 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1265
1266 enum a6xx_ztest_mode zmode;
1267
1268 if (fs->no_earlyz || fs->has_kill || fs->writes_pos || is_s8_uint) {
1269 zmode = A6XX_LATE_Z;
1270 } else {
1271 zmode = A6XX_EARLY_Z;
1272 }
1273
1274 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1275 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1276
1277 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1278 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1279 }
1280
1281 static void
1282 tu6_emit_geom_tess_consts(struct tu_cs *cs,
1283 const struct ir3_shader_variant *vs,
1284 const struct ir3_shader_variant *hs,
1285 const struct ir3_shader_variant *ds,
1286 const struct ir3_shader_variant *gs,
1287 uint32_t cps_per_patch)
1288 {
1289 uint32_t num_vertices =
1290 hs ? cps_per_patch : gs->shader->nir->info.gs.vertices_in;
1291
1292 uint32_t vs_params[4] = {
1293 vs->output_size * num_vertices * 4, /* vs primitive stride */
1294 vs->output_size * 4, /* vs vertex stride */
1295 0,
1296 0,
1297 };
1298 uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param;
1299 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1300 ARRAY_SIZE(vs_params), vs_params);
1301
1302 if (hs) {
1303 assert(ds->type != MESA_SHADER_NONE);
1304 uint32_t hs_params[4] = {
1305 vs->output_size * num_vertices * 4, /* hs primitive stride */
1306 vs->output_size * 4, /* hs vertex stride */
1307 hs->output_size,
1308 cps_per_patch,
1309 };
1310
1311 uint32_t hs_base = hs->const_state->offsets.primitive_param;
1312 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, hs_base, SB6_HS_SHADER, 0,
1313 ARRAY_SIZE(hs_params), hs_params);
1314 if (gs)
1315 num_vertices = gs->shader->nir->info.gs.vertices_in;
1316
1317 uint32_t ds_params[4] = {
1318 ds->output_size * num_vertices * 4, /* ds primitive stride */
1319 ds->output_size * 4, /* ds vertex stride */
1320 hs->output_size, /* hs vertex stride (dwords) */
1321 hs->shader->nir->info.tess.tcs_vertices_out
1322 };
1323
1324 uint32_t ds_base = ds->const_state->offsets.primitive_param;
1325 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, ds_base, SB6_DS_SHADER, 0,
1326 ARRAY_SIZE(ds_params), ds_params);
1327 }
1328
1329 if (gs) {
1330 const struct ir3_shader_variant *prev = ds ? ds : vs;
1331 uint32_t gs_params[4] = {
1332 prev->output_size * num_vertices * 4, /* gs primitive stride */
1333 prev->output_size * 4, /* gs vertex stride */
1334 0,
1335 0,
1336 };
1337 uint32_t gs_base = gs->const_state->offsets.primitive_param;
1338 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1339 ARRAY_SIZE(gs_params), gs_params);
1340 }
1341 }
1342
1343 static void
1344 tu6_emit_program(struct tu_cs *cs,
1345 struct tu_pipeline_builder *builder,
1346 bool binning_pass)
1347 {
1348 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
1349 const struct ir3_shader_variant *bs = builder->binning_variant;
1350 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
1351 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
1352 const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
1353 const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
1354 gl_shader_stage stage = MESA_SHADER_VERTEX;
1355
1356 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1357
1358 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1359 tu_cs_emit(cs, 0xff); /* XXX */
1360
1361 /* Don't use the binning pass variant when GS is present because we don't
1362 * support compiling correct binning pass variants with GS.
1363 */
1364 if (binning_pass && !gs) {
1365 vs = bs;
1366 tu6_emit_xs_config(cs, stage, bs, builder->binning_vs_iova);
1367 stage++;
1368 }
1369
1370 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1371 const struct ir3_shader_variant *xs = builder->variants[stage];
1372
1373 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1374 fs = xs = NULL;
1375
1376 tu6_emit_xs_config(cs, stage, xs, builder->shader_iova[stage]);
1377 }
1378
1379 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1380 tu_cs_emit(cs, 0);
1381
1382 tu6_emit_vpc(cs, vs, hs, ds, gs, fs);
1383 tu6_emit_vpc_varying_modes(cs, fs);
1384
1385 if (fs) {
1386 tu6_emit_fs_inputs(cs, fs);
1387 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1388 builder->use_dual_src_blend,
1389 builder->render_components,
1390 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1391 } else {
1392 /* TODO: check if these can be skipped if fs is disabled */
1393 struct ir3_shader_variant dummy_variant = {};
1394 tu6_emit_fs_inputs(cs, &dummy_variant);
1395 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1396 builder->use_dual_src_blend,
1397 builder->render_components,
1398 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1399 }
1400
1401 if (gs || hs) {
1402 uint32_t cps_per_patch = builder->create_info->pTessellationState ?
1403 builder->create_info->pTessellationState->patchControlPoints : 0;
1404 tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch);
1405 }
1406 }
1407
1408 static void
1409 tu6_emit_vertex_input(struct tu_cs *cs,
1410 const struct ir3_shader_variant *vs,
1411 const VkPipelineVertexInputStateCreateInfo *info,
1412 uint32_t *bindings_used)
1413 {
1414 uint32_t vfd_decode_idx = 0;
1415 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1416 uint32_t step_rate[MAX_VBS];
1417
1418 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1419 const VkVertexInputBindingDescription *binding =
1420 &info->pVertexBindingDescriptions[i];
1421
1422 tu_cs_emit_regs(cs,
1423 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1424
1425 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1426 binding_instanced |= 1 << binding->binding;
1427
1428 *bindings_used |= 1 << binding->binding;
1429 step_rate[binding->binding] = 1;
1430 }
1431
1432 const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_state =
1433 vk_find_struct_const(info->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1434 if (div_state) {
1435 for (uint32_t i = 0; i < div_state->vertexBindingDivisorCount; i++) {
1436 const VkVertexInputBindingDivisorDescriptionEXT *desc =
1437 &div_state->pVertexBindingDivisors[i];
1438 step_rate[desc->binding] = desc->divisor;
1439 }
1440 }
1441
1442 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1443
1444 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1445 const VkVertexInputAttributeDescription *attr =
1446 &info->pVertexAttributeDescriptions[i];
1447 uint32_t input_idx;
1448
1449 assert(*bindings_used & BIT(attr->binding));
1450
1451 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1452 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1453 break;
1454 }
1455
1456 /* attribute not used, skip it */
1457 if (input_idx == vs->inputs_count)
1458 continue;
1459
1460 const struct tu_native_format format = tu6_format_vtx(attr->format);
1461 tu_cs_emit_regs(cs,
1462 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1463 .idx = attr->binding,
1464 .offset = attr->offset,
1465 .instanced = binding_instanced & (1 << attr->binding),
1466 .format = format.fmt,
1467 .swap = format.swap,
1468 .unk30 = 1,
1469 ._float = !vk_format_is_int(attr->format)),
1470 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, step_rate[attr->binding]));
1471
1472 tu_cs_emit_regs(cs,
1473 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1474 .writemask = vs->inputs[input_idx].compmask,
1475 .regid = vs->inputs[input_idx].regid));
1476
1477 vfd_decode_idx++;
1478 }
1479
1480 tu_cs_emit_regs(cs,
1481 A6XX_VFD_CONTROL_0(
1482 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1483 .decode_cnt = vfd_decode_idx));
1484 }
1485
1486 static uint32_t
1487 tu6_guardband_adj(uint32_t v)
1488 {
1489 if (v > 256)
1490 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1491 else
1492 return 511;
1493 }
1494
1495 void
1496 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1497 {
1498 float offsets[3];
1499 float scales[3];
1500 scales[0] = viewport->width / 2.0f;
1501 scales[1] = viewport->height / 2.0f;
1502 scales[2] = viewport->maxDepth - viewport->minDepth;
1503 offsets[0] = viewport->x + scales[0];
1504 offsets[1] = viewport->y + scales[1];
1505 offsets[2] = viewport->minDepth;
1506
1507 VkOffset2D min;
1508 VkOffset2D max;
1509 min.x = (int32_t) viewport->x;
1510 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1511 if (viewport->height >= 0.0f) {
1512 min.y = (int32_t) viewport->y;
1513 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1514 } else {
1515 min.y = (int32_t)(viewport->y + viewport->height);
1516 max.y = (int32_t) ceilf(viewport->y);
1517 }
1518 /* the spec allows viewport->height to be 0.0f */
1519 if (min.y == max.y)
1520 max.y++;
1521 assert(min.x >= 0 && min.x < max.x);
1522 assert(min.y >= 0 && min.y < max.y);
1523
1524 VkExtent2D guardband_adj;
1525 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1526 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1527
1528 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1529 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1530 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1531 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1532 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1533 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1534 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1535
1536 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1537 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1538 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1539 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1540 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1541
1542 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1543 tu_cs_emit(cs,
1544 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1545 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1546
1547 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1548 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1549
1550 tu_cs_emit_regs(cs,
1551 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1552 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1553
1554 tu_cs_emit_regs(cs,
1555 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1556 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1557 }
1558
1559 void
1560 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1561 {
1562 VkOffset2D min = scissor->offset;
1563 VkOffset2D max = {
1564 scissor->offset.x + scissor->extent.width,
1565 scissor->offset.y + scissor->extent.height,
1566 };
1567
1568 /* special case for empty scissor with max == 0 to avoid overflow */
1569 if (max.x == 0)
1570 min.x = max.x = 1;
1571 if (max.y == 0)
1572 min.y = max.y = 1;
1573
1574 /* avoid overflow with large scissor
1575 * note the max will be limited to min - 1, so that empty scissor works
1576 */
1577 uint32_t scissor_max = BITFIELD_MASK(15);
1578 min.x = MIN2(scissor_max, min.x);
1579 min.y = MIN2(scissor_max, min.y);
1580 max.x = MIN2(scissor_max, max.x);
1581 max.y = MIN2(scissor_max, max.y);
1582
1583 tu_cs_emit_regs(cs,
1584 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0(.x = min.x, .y = min.y),
1585 A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0(.x = max.x - 1, .y = max.y - 1));
1586 }
1587
1588 void
1589 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1590 {
1591 if (!samp_loc) {
1592 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1593 tu_cs_emit(cs, 0);
1594
1595 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1596 tu_cs_emit(cs, 0);
1597
1598 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1599 tu_cs_emit(cs, 0);
1600 return;
1601 }
1602
1603 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1604 assert(samp_loc->sampleLocationGridSize.width == 1);
1605 assert(samp_loc->sampleLocationGridSize.height == 1);
1606
1607 uint32_t sample_config =
1608 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1609 uint32_t sample_locations = 0;
1610 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1611 sample_locations |=
1612 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1613 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1614 }
1615
1616 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1617 tu_cs_emit(cs, sample_config);
1618 tu_cs_emit(cs, sample_locations);
1619
1620 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1621 tu_cs_emit(cs, sample_config);
1622 tu_cs_emit(cs, sample_locations);
1623
1624 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1625 tu_cs_emit(cs, sample_config);
1626 tu_cs_emit(cs, sample_locations);
1627 }
1628
1629 static uint32_t
1630 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1631 VkSampleCountFlagBits samples)
1632 {
1633 uint32_t gras_su_cntl = 0;
1634
1635 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1636 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1637 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1638 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1639
1640 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1641 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1642
1643 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1644
1645 if (rast_info->depthBiasEnable)
1646 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1647
1648 if (samples > VK_SAMPLE_COUNT_1_BIT)
1649 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1650
1651 return gras_su_cntl;
1652 }
1653
1654 void
1655 tu6_emit_depth_bias(struct tu_cs *cs,
1656 float constant_factor,
1657 float clamp,
1658 float slope_factor)
1659 {
1660 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1661 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1662 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1663 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1664 }
1665
1666 static void
1667 tu6_emit_depth_control(struct tu_cs *cs,
1668 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1669 const VkPipelineRasterizationStateCreateInfo *rast_info)
1670 {
1671 uint32_t rb_depth_cntl = 0;
1672 if (ds_info->depthTestEnable) {
1673 rb_depth_cntl |=
1674 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1675 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1676 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
1677
1678 if (rast_info->depthClampEnable)
1679 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1680
1681 if (ds_info->depthWriteEnable)
1682 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1683 }
1684
1685 if (ds_info->depthBoundsTestEnable)
1686 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1687
1688 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1689 tu_cs_emit(cs, rb_depth_cntl);
1690 }
1691
1692 static void
1693 tu6_emit_stencil_control(struct tu_cs *cs,
1694 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1695 {
1696 uint32_t rb_stencil_control = 0;
1697 if (ds_info->stencilTestEnable) {
1698 const VkStencilOpState *front = &ds_info->front;
1699 const VkStencilOpState *back = &ds_info->back;
1700 rb_stencil_control |=
1701 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1702 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1703 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1704 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1705 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1706 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1707 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1708 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1709 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1710 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1711 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1712 }
1713
1714 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1715 tu_cs_emit(cs, rb_stencil_control);
1716 }
1717
1718 static uint32_t
1719 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1720 bool has_alpha)
1721 {
1722 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1723 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1724 has_alpha ? att->srcColorBlendFactor
1725 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1726 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1727 has_alpha ? att->dstColorBlendFactor
1728 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1729 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1730 const enum adreno_rb_blend_factor src_alpha_factor =
1731 tu6_blend_factor(att->srcAlphaBlendFactor);
1732 const enum adreno_rb_blend_factor dst_alpha_factor =
1733 tu6_blend_factor(att->dstAlphaBlendFactor);
1734
1735 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1736 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1737 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1738 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1739 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1740 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1741 }
1742
1743 static uint32_t
1744 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1745 uint32_t rb_mrt_control_rop,
1746 bool is_int,
1747 bool has_alpha)
1748 {
1749 uint32_t rb_mrt_control =
1750 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1751
1752 /* ignore blending and logic op for integer attachments */
1753 if (is_int) {
1754 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1755 return rb_mrt_control;
1756 }
1757
1758 rb_mrt_control |= rb_mrt_control_rop;
1759
1760 if (att->blendEnable) {
1761 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1762
1763 if (has_alpha)
1764 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1765 }
1766
1767 return rb_mrt_control;
1768 }
1769
1770 static void
1771 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1772 const VkPipelineColorBlendStateCreateInfo *blend_info,
1773 const VkFormat attachment_formats[MAX_RTS],
1774 uint32_t *blend_enable_mask)
1775 {
1776 *blend_enable_mask = 0;
1777
1778 bool rop_reads_dst = false;
1779 uint32_t rb_mrt_control_rop = 0;
1780 if (blend_info->logicOpEnable) {
1781 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1782 rb_mrt_control_rop =
1783 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1784 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1785 }
1786
1787 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1788 const VkPipelineColorBlendAttachmentState *att =
1789 &blend_info->pAttachments[i];
1790 const VkFormat format = attachment_formats[i];
1791
1792 uint32_t rb_mrt_control = 0;
1793 uint32_t rb_mrt_blend_control = 0;
1794 if (format != VK_FORMAT_UNDEFINED) {
1795 const bool is_int = vk_format_is_int(format);
1796 const bool has_alpha = vk_format_has_alpha(format);
1797
1798 rb_mrt_control =
1799 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1800 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1801
1802 if (att->blendEnable || rop_reads_dst)
1803 *blend_enable_mask |= 1 << i;
1804 }
1805
1806 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1807 tu_cs_emit(cs, rb_mrt_control);
1808 tu_cs_emit(cs, rb_mrt_blend_control);
1809 }
1810 }
1811
1812 static void
1813 tu6_emit_blend_control(struct tu_cs *cs,
1814 uint32_t blend_enable_mask,
1815 bool dual_src_blend,
1816 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1817 {
1818 const uint32_t sample_mask =
1819 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1820 : ((1 << msaa_info->rasterizationSamples) - 1);
1821
1822 tu_cs_emit_regs(cs,
1823 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1824 .dual_color_in_enable = dual_src_blend,
1825 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1826 .unk8 = true));
1827
1828 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1829 tu_cs_emit_regs(cs,
1830 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1831 .independent_blend = true,
1832 .sample_mask = sample_mask,
1833 .dual_color_in_enable = dual_src_blend,
1834 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1835 .alpha_to_one = msaa_info->alphaToOneEnable));
1836 }
1837
1838 static VkResult
1839 tu_pipeline_allocate_cs(struct tu_device *dev,
1840 struct tu_pipeline *pipeline,
1841 struct tu_pipeline_builder *builder,
1842 struct ir3_shader_variant *compute)
1843 {
1844 uint32_t size = 2048 + tu6_load_state_size(pipeline->layout, compute);
1845
1846 /* graphics case: */
1847 if (builder) {
1848 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1849 if (builder->variants[i])
1850 size += builder->variants[i]->info.sizedwords;
1851 }
1852
1853 size += builder->binning_variant->info.sizedwords;
1854 } else {
1855 size += compute->info.sizedwords;
1856 }
1857
1858 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, size);
1859
1860 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1861 * that LOAD_STATE can potentially take up a large amount of space so we
1862 * calculate its size explicitly.
1863 */
1864 return tu_cs_reserve_space(&pipeline->cs, size);
1865 }
1866
1867 static void
1868 tu_pipeline_shader_key_init(struct ir3_shader_key *key,
1869 const VkGraphicsPipelineCreateInfo *pipeline_info)
1870 {
1871 for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
1872 if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
1873 key->has_gs = true;
1874 break;
1875 }
1876 }
1877
1878 if (pipeline_info->pRasterizationState->rasterizerDiscardEnable)
1879 return;
1880
1881 const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
1882 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
1883 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1884 if (msaa_info->rasterizationSamples > 1 ||
1885 /* also set msaa key when sample location is not the default
1886 * since this affects varying interpolation */
1887 (sample_locations && sample_locations->sampleLocationsEnable)) {
1888 key->msaa = true;
1889 }
1890
1891 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1892 if (msaa_info->sampleShadingEnable)
1893 key->sample_shading = true;
1894
1895 /* We set this after we compile to NIR because we need the prim mode */
1896 key->tessellation = IR3_TESS_NONE;
1897 }
1898
1899 static uint32_t
1900 tu6_get_tessmode(struct tu_shader* shader)
1901 {
1902 uint32_t primitive_mode = shader->ir3_shader->nir->info.tess.primitive_mode;
1903 switch (primitive_mode) {
1904 case GL_ISOLINES:
1905 return IR3_TESS_ISOLINES;
1906 case GL_TRIANGLES:
1907 return IR3_TESS_TRIANGLES;
1908 case GL_QUADS:
1909 return IR3_TESS_QUADS;
1910 case GL_NONE:
1911 return IR3_TESS_NONE;
1912 default:
1913 unreachable("bad tessmode");
1914 }
1915 }
1916
1917 static uint64_t
1918 tu_upload_variant(struct tu_pipeline *pipeline,
1919 const struct ir3_shader_variant *variant)
1920 {
1921 struct tu_cs_memory memory;
1922
1923 if (!variant)
1924 return 0;
1925
1926 /* this expects to get enough alignment because shaders are allocated first
1927 * and sizedwords is always aligned correctly
1928 * note: an assert in tu6_emit_xs_config validates the alignment
1929 */
1930 tu_cs_alloc(&pipeline->cs, variant->info.sizedwords, 1, &memory);
1931
1932 memcpy(memory.map, variant->bin, sizeof(uint32_t) * variant->info.sizedwords);
1933 return memory.iova;
1934 }
1935
1936 static VkResult
1937 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
1938 struct tu_pipeline *pipeline)
1939 {
1940 const struct ir3_compiler *compiler = builder->device->compiler;
1941 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1942 NULL
1943 };
1944 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1945 gl_shader_stage stage =
1946 vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage);
1947 stage_infos[stage] = &builder->create_info->pStages[i];
1948 }
1949
1950 struct ir3_shader_key key = {};
1951 tu_pipeline_shader_key_init(&key, builder->create_info);
1952
1953 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1954 stage < MESA_SHADER_STAGES; stage++) {
1955 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1956 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
1957 continue;
1958
1959 struct tu_shader *shader =
1960 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1961 builder->alloc);
1962 if (!shader)
1963 return VK_ERROR_OUT_OF_HOST_MEMORY;
1964
1965 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
1966 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
1967 * the mode is specified in the tessellation control shader. */
1968 if ((stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_TESS_CTRL) &&
1969 key.tessellation == IR3_TESS_NONE) {
1970 key.tessellation = tu6_get_tessmode(shader);
1971 }
1972
1973 builder->shaders[stage] = shader;
1974 }
1975
1976 struct tu_shader *gs = builder->shaders[MESA_SHADER_GEOMETRY];
1977 key.layer_zero =
1978 !gs || !(gs->ir3_shader->nir->info.outputs_written & VARYING_SLOT_LAYER);
1979
1980 pipeline->tess.patch_type = key.tessellation;
1981
1982 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1983 stage < MESA_SHADER_STAGES; stage++) {
1984 if (!builder->shaders[stage])
1985 continue;
1986
1987 bool created;
1988 builder->variants[stage] =
1989 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
1990 &key, false, &created);
1991 if (!builder->variants[stage])
1992 return VK_ERROR_OUT_OF_HOST_MEMORY;
1993 }
1994
1995 uint32_t safe_constlens = ir3_trim_constlen(builder->variants, compiler);
1996
1997 key.safe_constlen = true;
1998
1999 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2000 stage < MESA_SHADER_STAGES; stage++) {
2001 if (!builder->shaders[stage])
2002 continue;
2003
2004 if (safe_constlens & (1 << stage)) {
2005 bool created;
2006 builder->variants[stage] =
2007 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2008 &key, false, &created);
2009 if (!builder->variants[stage])
2010 return VK_ERROR_OUT_OF_HOST_MEMORY;
2011 }
2012 }
2013
2014 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2015 struct ir3_shader_variant *variant;
2016
2017 if (vs->ir3_shader->stream_output.num_outputs ||
2018 !ir3_has_binning_vs(&key)) {
2019 variant = builder->variants[MESA_SHADER_VERTEX];
2020 } else {
2021 bool created;
2022 key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX));
2023 variant = ir3_shader_get_variant(vs->ir3_shader, &key,
2024 true, &created);
2025 if (!variant)
2026 return VK_ERROR_OUT_OF_HOST_MEMORY;
2027 }
2028
2029 builder->binning_variant = variant;
2030
2031 return VK_SUCCESS;
2032 }
2033
2034 static void
2035 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2036 struct tu_pipeline *pipeline)
2037 {
2038 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2039 builder->create_info->pDynamicState;
2040
2041 if (!dynamic_info)
2042 return;
2043
2044 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2045 VkDynamicState state = dynamic_info->pDynamicStates[i];
2046 switch (state) {
2047 case VK_DYNAMIC_STATE_VIEWPORT ... VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2048 pipeline->dynamic_state_mask |= BIT(state);
2049 break;
2050 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
2051 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS);
2052 break;
2053 default:
2054 assert(!"unsupported dynamic state");
2055 break;
2056 }
2057 }
2058 }
2059
2060 static void
2061 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2062 struct tu_shader *shader,
2063 struct ir3_shader_variant *v)
2064 {
2065 link->const_state = *ir3_const_state(v);
2066 link->constlen = v->constlen;
2067 link->push_consts = shader->push_consts;
2068 }
2069
2070 static void
2071 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2072 struct tu_pipeline *pipeline)
2073 {
2074 struct tu_cs prog_cs;
2075 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2076 tu6_emit_program(&prog_cs, builder, false);
2077 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2078
2079 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2080 tu6_emit_program(&prog_cs, builder, true);
2081 pipeline->program.binning_state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2082
2083 VkShaderStageFlags stages = 0;
2084 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2085 stages |= builder->create_info->pStages[i].stage;
2086 }
2087 pipeline->active_stages = stages;
2088
2089 uint32_t desc_sets = 0;
2090 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2091 if (!builder->shaders[i])
2092 continue;
2093
2094 tu_pipeline_set_linkage(&pipeline->program.link[i],
2095 builder->shaders[i],
2096 builder->variants[i]);
2097 desc_sets |= builder->shaders[i]->active_desc_sets;
2098 }
2099 pipeline->active_desc_sets = desc_sets;
2100 }
2101
2102 static void
2103 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2104 struct tu_pipeline *pipeline)
2105 {
2106 const VkPipelineVertexInputStateCreateInfo *vi_info =
2107 builder->create_info->pVertexInputState;
2108 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
2109 const struct ir3_shader_variant *bs = builder->binning_variant;
2110
2111 struct tu_cs vi_cs;
2112 tu_cs_begin_sub_stream(&pipeline->cs,
2113 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2114 tu6_emit_vertex_input(&vi_cs, vs, vi_info,
2115 &pipeline->vi.bindings_used);
2116 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2117
2118 if (bs) {
2119 tu_cs_begin_sub_stream(&pipeline->cs,
2120 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2121 tu6_emit_vertex_input(
2122 &vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
2123 pipeline->vi.binning_state_ib =
2124 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2125 }
2126 }
2127
2128 static void
2129 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2130 struct tu_pipeline *pipeline)
2131 {
2132 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2133 builder->create_info->pInputAssemblyState;
2134
2135 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2136 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2137 }
2138
2139 static bool
2140 tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs,
2141 uint32_t id, uint32_t size)
2142 {
2143 struct tu_cs_memory memory;
2144
2145 if (pipeline->dynamic_state_mask & BIT(id))
2146 return false;
2147
2148 /* TODO: share this logc with tu_cmd_dynamic_state */
2149 tu_cs_alloc(&pipeline->cs, size, 1, &memory);
2150 tu_cs_init_external(cs, memory.map, memory.map + size);
2151 tu_cs_begin(cs);
2152 tu_cs_reserve_space(cs, size);
2153
2154 assert(id < ARRAY_SIZE(pipeline->dynamic_state));
2155 pipeline->dynamic_state[id].iova = memory.iova;
2156 pipeline->dynamic_state[id].size = size;
2157 return true;
2158 }
2159
2160 static void
2161 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder,
2162 struct tu_pipeline *pipeline)
2163 {
2164 const VkPipelineTessellationStateCreateInfo *tess_info =
2165 builder->create_info->pTessellationState;
2166
2167 if (!tess_info)
2168 return;
2169
2170 assert(pipeline->ia.primtype == DI_PT_PATCHES0);
2171 assert(tess_info->patchControlPoints <= 32);
2172 pipeline->ia.primtype += tess_info->patchControlPoints;
2173 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info =
2174 vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2175 pipeline->tess.upper_left_domain_origin = !domain_info ||
2176 domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
2177 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
2178 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
2179 pipeline->tess.param_stride = hs->output_size * 4;
2180 pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1;
2181 pipeline->tess.ds_bo_regid = ds->const_state->offsets.primitive_param + 1;
2182 }
2183
2184 static void
2185 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2186 struct tu_pipeline *pipeline)
2187 {
2188 /* The spec says:
2189 *
2190 * pViewportState is a pointer to an instance of the
2191 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2192 * pipeline has rasterization disabled."
2193 *
2194 * We leave the relevant registers stale in that case.
2195 */
2196 if (builder->rasterizer_discard)
2197 return;
2198
2199 const VkPipelineViewportStateCreateInfo *vp_info =
2200 builder->create_info->pViewportState;
2201
2202 struct tu_cs cs;
2203
2204 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_VIEWPORT, 18))
2205 tu6_emit_viewport(&cs, vp_info->pViewports);
2206
2207 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_SCISSOR, 3))
2208 tu6_emit_scissor(&cs, vp_info->pScissors);
2209 }
2210
2211 static void
2212 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2213 struct tu_pipeline *pipeline)
2214 {
2215 const VkPipelineRasterizationStateCreateInfo *rast_info =
2216 builder->create_info->pRasterizationState;
2217
2218 enum a6xx_polygon_mode mode = tu6_polygon_mode(rast_info->polygonMode);
2219
2220 struct tu_cs cs;
2221 tu_cs_begin_sub_stream(&pipeline->cs, 9, &cs);
2222
2223 tu_cs_emit_regs(&cs,
2224 A6XX_GRAS_CL_CNTL(
2225 .znear_clip_disable = rast_info->depthClampEnable,
2226 .zfar_clip_disable = rast_info->depthClampEnable,
2227 .unk5 = rast_info->depthClampEnable,
2228 .zero_gb_scale_z = 1,
2229 .vp_clip_code_ignore = 1));
2230
2231 tu_cs_emit_regs(&cs,
2232 A6XX_VPC_POLYGON_MODE(.mode = mode));
2233
2234 tu_cs_emit_regs(&cs,
2235 A6XX_PC_POLYGON_MODE(.mode = mode));
2236
2237 /* move to hw ctx init? */
2238 tu_cs_emit_regs(&cs,
2239 A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
2240 A6XX_GRAS_SU_POINT_SIZE(1.0f));
2241
2242 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2243
2244 pipeline->gras_su_cntl =
2245 tu6_gras_su_cntl(rast_info, builder->samples);
2246
2247 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_LINE_WIDTH, 2)) {
2248 pipeline->gras_su_cntl |=
2249 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info->lineWidth / 2.0f);
2250 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = pipeline->gras_su_cntl));
2251 }
2252
2253 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BIAS, 4)) {
2254 tu6_emit_depth_bias(&cs, rast_info->depthBiasConstantFactor,
2255 rast_info->depthBiasClamp,
2256 rast_info->depthBiasSlopeFactor);
2257 }
2258
2259 }
2260
2261 static void
2262 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2263 struct tu_pipeline *pipeline)
2264 {
2265 /* The spec says:
2266 *
2267 * pDepthStencilState is a pointer to an instance of the
2268 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2269 * the pipeline has rasterization disabled or if the subpass of the
2270 * render pass the pipeline is created against does not use a
2271 * depth/stencil attachment.
2272 *
2273 * Disable both depth and stencil tests if there is no ds attachment,
2274 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2275 * only the separate stencil attachment
2276 */
2277 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2278 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2279 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2280 ? builder->create_info->pDepthStencilState
2281 : &dummy_ds_info;
2282 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2283 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2284 ? ds_info : &dummy_ds_info;
2285
2286 struct tu_cs cs;
2287 tu_cs_begin_sub_stream(&pipeline->cs, 6, &cs);
2288
2289 /* move to hw ctx init? */
2290 tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
2291 tu6_emit_depth_control(&cs, ds_info_depth,
2292 builder->create_info->pRasterizationState);
2293 tu6_emit_stencil_control(&cs, ds_info);
2294
2295 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2296
2297 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
2298 tu_cs_emit_regs(&cs,
2299 A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
2300 A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
2301 }
2302
2303 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
2304 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
2305 .bfmask = ds_info->back.compareMask & 0xff));
2306 }
2307
2308 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2)) {
2309 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.wrmask = ds_info->front.writeMask & 0xff,
2310 .bfwrmask = ds_info->back.writeMask & 0xff));
2311 }
2312
2313 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2)) {
2314 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.ref = ds_info->front.reference & 0xff,
2315 .bfref = ds_info->back.reference & 0xff));
2316 }
2317 }
2318
2319 static void
2320 tu_pipeline_builder_parse_multisample_and_color_blend(
2321 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2322 {
2323 /* The spec says:
2324 *
2325 * pMultisampleState is a pointer to an instance of the
2326 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2327 * has rasterization disabled.
2328 *
2329 * Also,
2330 *
2331 * pColorBlendState is a pointer to an instance of the
2332 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2333 * pipeline has rasterization disabled or if the subpass of the render
2334 * pass the pipeline is created against does not use any color
2335 * attachments.
2336 *
2337 * We leave the relevant registers stale when rasterization is disabled.
2338 */
2339 if (builder->rasterizer_discard)
2340 return;
2341
2342 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2343 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2344 builder->create_info->pMultisampleState;
2345 const VkPipelineColorBlendStateCreateInfo *blend_info =
2346 builder->use_color_attachments ? builder->create_info->pColorBlendState
2347 : &dummy_blend_info;
2348
2349 struct tu_cs cs;
2350 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 4, &cs);
2351
2352 uint32_t blend_enable_mask;
2353 tu6_emit_rb_mrt_controls(&cs, blend_info,
2354 builder->color_attachment_formats,
2355 &blend_enable_mask);
2356
2357 tu6_emit_blend_control(&cs, blend_enable_mask,
2358 builder->use_dual_src_blend, msaa_info);
2359
2360 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2361
2362 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5)) {
2363 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2364 tu_cs_emit_array(&cs, (const uint32_t *) blend_info->blendConstants, 4);
2365 }
2366
2367 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2368 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2369 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2370
2371 if (sample_locations && sample_locations->sampleLocationsEnable)
2372 samp_loc = &sample_locations->sampleLocationsInfo;
2373
2374 if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
2375 samp_loc ? 9 : 6)) {
2376 tu6_emit_sample_locations(&cs, samp_loc);
2377 }
2378 }
2379
2380 static void
2381 tu_pipeline_finish(struct tu_pipeline *pipeline,
2382 struct tu_device *dev,
2383 const VkAllocationCallbacks *alloc)
2384 {
2385 tu_cs_finish(&pipeline->cs);
2386 }
2387
2388 static VkResult
2389 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2390 struct tu_pipeline **pipeline)
2391 {
2392 VkResult result;
2393
2394 *pipeline = vk_object_zalloc(&builder->device->vk, builder->alloc,
2395 sizeof(**pipeline), VK_OBJECT_TYPE_PIPELINE);
2396 if (!*pipeline)
2397 return VK_ERROR_OUT_OF_HOST_MEMORY;
2398
2399 (*pipeline)->layout = builder->layout;
2400
2401 /* compile and upload shaders */
2402 result = tu_pipeline_builder_compile_shaders(builder, *pipeline);
2403 if (result != VK_SUCCESS) {
2404 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2405 return result;
2406 }
2407
2408 result = tu_pipeline_allocate_cs(builder->device, *pipeline, builder, NULL);
2409 if (result != VK_SUCCESS) {
2410 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2411 return result;
2412 }
2413
2414 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2415 builder->shader_iova[i] = tu_upload_variant(*pipeline, builder->variants[i]);
2416
2417 builder->binning_vs_iova =
2418 tu_upload_variant(*pipeline, builder->binning_variant);
2419
2420 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2421 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2422 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2423 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2424 tu_pipeline_builder_parse_tessellation(builder, *pipeline);
2425 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2426 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2427 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2428 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2429 tu6_emit_load_state(*pipeline, false);
2430
2431 /* we should have reserved enough space upfront such that the CS never
2432 * grows
2433 */
2434 assert((*pipeline)->cs.bo_count == 1);
2435
2436 return VK_SUCCESS;
2437 }
2438
2439 static void
2440 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2441 {
2442 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2443 if (!builder->shaders[i])
2444 continue;
2445 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2446 }
2447 }
2448
2449 static void
2450 tu_pipeline_builder_init_graphics(
2451 struct tu_pipeline_builder *builder,
2452 struct tu_device *dev,
2453 struct tu_pipeline_cache *cache,
2454 const VkGraphicsPipelineCreateInfo *create_info,
2455 const VkAllocationCallbacks *alloc)
2456 {
2457 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2458
2459 *builder = (struct tu_pipeline_builder) {
2460 .device = dev,
2461 .cache = cache,
2462 .create_info = create_info,
2463 .alloc = alloc,
2464 .layout = layout,
2465 };
2466
2467 builder->rasterizer_discard =
2468 create_info->pRasterizationState->rasterizerDiscardEnable;
2469
2470 if (builder->rasterizer_discard) {
2471 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2472 } else {
2473 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2474
2475 const struct tu_render_pass *pass =
2476 tu_render_pass_from_handle(create_info->renderPass);
2477 const struct tu_subpass *subpass =
2478 &pass->subpasses[create_info->subpass];
2479
2480 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2481 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2482 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2483
2484 assert(subpass->color_count == 0 ||
2485 !create_info->pColorBlendState ||
2486 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2487 builder->color_attachment_count = subpass->color_count;
2488 for (uint32_t i = 0; i < subpass->color_count; i++) {
2489 const uint32_t a = subpass->color_attachments[i].attachment;
2490 if (a == VK_ATTACHMENT_UNUSED)
2491 continue;
2492
2493 builder->color_attachment_formats[i] = pass->attachments[a].format;
2494 builder->use_color_attachments = true;
2495 builder->render_components |= 0xf << (i * 4);
2496 }
2497
2498 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2499 builder->color_attachment_count++;
2500 builder->use_dual_src_blend = true;
2501 /* dual source blending has an extra fs output in the 2nd slot */
2502 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2503 builder->render_components |= 0xf << 4;
2504 }
2505 }
2506 }
2507
2508 static VkResult
2509 tu_graphics_pipeline_create(VkDevice device,
2510 VkPipelineCache pipelineCache,
2511 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2512 const VkAllocationCallbacks *pAllocator,
2513 VkPipeline *pPipeline)
2514 {
2515 TU_FROM_HANDLE(tu_device, dev, device);
2516 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2517
2518 struct tu_pipeline_builder builder;
2519 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2520 pCreateInfo, pAllocator);
2521
2522 struct tu_pipeline *pipeline = NULL;
2523 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2524 tu_pipeline_builder_finish(&builder);
2525
2526 if (result == VK_SUCCESS)
2527 *pPipeline = tu_pipeline_to_handle(pipeline);
2528 else
2529 *pPipeline = VK_NULL_HANDLE;
2530
2531 return result;
2532 }
2533
2534 VkResult
2535 tu_CreateGraphicsPipelines(VkDevice device,
2536 VkPipelineCache pipelineCache,
2537 uint32_t count,
2538 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2539 const VkAllocationCallbacks *pAllocator,
2540 VkPipeline *pPipelines)
2541 {
2542 VkResult final_result = VK_SUCCESS;
2543
2544 for (uint32_t i = 0; i < count; i++) {
2545 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2546 &pCreateInfos[i], pAllocator,
2547 &pPipelines[i]);
2548
2549 if (result != VK_SUCCESS)
2550 final_result = result;
2551 }
2552
2553 return final_result;
2554 }
2555
2556 static VkResult
2557 tu_compute_pipeline_create(VkDevice device,
2558 VkPipelineCache _cache,
2559 const VkComputePipelineCreateInfo *pCreateInfo,
2560 const VkAllocationCallbacks *pAllocator,
2561 VkPipeline *pPipeline)
2562 {
2563 TU_FROM_HANDLE(tu_device, dev, device);
2564 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2565 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2566 VkResult result;
2567
2568 struct tu_pipeline *pipeline;
2569
2570 *pPipeline = VK_NULL_HANDLE;
2571
2572 pipeline = vk_object_zalloc(&dev->vk, pAllocator, sizeof(*pipeline),
2573 VK_OBJECT_TYPE_PIPELINE);
2574 if (!pipeline)
2575 return VK_ERROR_OUT_OF_HOST_MEMORY;
2576
2577 pipeline->layout = layout;
2578
2579 struct ir3_shader_key key = {};
2580
2581 struct tu_shader *shader =
2582 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2583 if (!shader) {
2584 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2585 goto fail;
2586 }
2587
2588 pipeline->active_desc_sets = shader->active_desc_sets;
2589
2590 bool created;
2591 struct ir3_shader_variant *v =
2592 ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
2593 if (!v) {
2594 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2595 goto fail;
2596 }
2597
2598 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2599 shader, v);
2600
2601 result = tu_pipeline_allocate_cs(dev, pipeline, NULL, v);
2602 if (result != VK_SUCCESS)
2603 goto fail;
2604
2605 uint64_t shader_iova = tu_upload_variant(pipeline, v);
2606
2607 for (int i = 0; i < 3; i++)
2608 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2609
2610 struct tu_cs prog_cs;
2611 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2612 tu6_emit_cs_config(&prog_cs, shader, v, shader_iova);
2613 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2614
2615 tu6_emit_load_state(pipeline, true);
2616
2617 *pPipeline = tu_pipeline_to_handle(pipeline);
2618 return VK_SUCCESS;
2619
2620 fail:
2621 if (shader)
2622 tu_shader_destroy(dev, shader, pAllocator);
2623
2624 vk_object_free(&dev->vk, pAllocator, pipeline);
2625
2626 return result;
2627 }
2628
2629 VkResult
2630 tu_CreateComputePipelines(VkDevice device,
2631 VkPipelineCache pipelineCache,
2632 uint32_t count,
2633 const VkComputePipelineCreateInfo *pCreateInfos,
2634 const VkAllocationCallbacks *pAllocator,
2635 VkPipeline *pPipelines)
2636 {
2637 VkResult final_result = VK_SUCCESS;
2638
2639 for (uint32_t i = 0; i < count; i++) {
2640 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2641 &pCreateInfos[i],
2642 pAllocator, &pPipelines[i]);
2643 if (result != VK_SUCCESS)
2644 final_result = result;
2645 }
2646
2647 return final_result;
2648 }
2649
2650 void
2651 tu_DestroyPipeline(VkDevice _device,
2652 VkPipeline _pipeline,
2653 const VkAllocationCallbacks *pAllocator)
2654 {
2655 TU_FROM_HANDLE(tu_device, dev, _device);
2656 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2657
2658 if (!_pipeline)
2659 return;
2660
2661 tu_pipeline_finish(pipeline, dev, pAllocator);
2662 vk_object_free(&dev->vk, pAllocator, pipeline);
2663 }