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tu: Implement dual-src blending
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static inline uint32_t
46 tu6_vkstage2opcode(VkShaderStageFlags stage)
47 {
48 switch (stage) {
49 case VK_SHADER_STAGE_VERTEX_BIT:
50 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
51 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
52 case VK_SHADER_STAGE_GEOMETRY_BIT:
53 return CP_LOAD_STATE6_GEOM;
54 case VK_SHADER_STAGE_FRAGMENT_BIT:
55 case VK_SHADER_STAGE_COMPUTE_BIT:
56 return CP_LOAD_STATE6_FRAG;
57 default:
58 unreachable("bad shader type");
59 }
60 }
61
62 static enum a6xx_state_block
63 tu6_tex_stage2sb(VkShaderStageFlags stage)
64 {
65 switch (stage) {
66 case VK_SHADER_STAGE_VERTEX_BIT:
67 return SB6_VS_TEX;
68 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
69 return SB6_HS_TEX;
70 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
71 return SB6_DS_TEX;
72 case VK_SHADER_STAGE_GEOMETRY_BIT:
73 return SB6_GS_TEX;
74 case VK_SHADER_STAGE_FRAGMENT_BIT:
75 return SB6_FS_TEX;
76 case VK_SHADER_STAGE_COMPUTE_BIT:
77 return SB6_CS_TEX;
78 default:
79 unreachable("bad shader stage");
80 }
81 }
82
83 static enum a6xx_state_block
84 tu6_ubo_stage2sb(VkShaderStageFlags stage)
85 {
86 switch (stage) {
87 case VK_SHADER_STAGE_VERTEX_BIT:
88 return SB6_VS_SHADER;
89 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
90 return SB6_HS_SHADER;
91 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
92 return SB6_DS_SHADER;
93 case VK_SHADER_STAGE_GEOMETRY_BIT:
94 return SB6_GS_SHADER;
95 case VK_SHADER_STAGE_FRAGMENT_BIT:
96 return SB6_FS_SHADER;
97 case VK_SHADER_STAGE_COMPUTE_BIT:
98 return SB6_CS_SHADER;
99 default:
100 unreachable("bad shader stage");
101 }
102 }
103
104 static void
105 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
106 enum a6xx_state_block sb, unsigned base, unsigned offset,
107 unsigned count)
108 {
109 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
110 * clear if emitting more packets will even help anything. Presumably the
111 * descriptor cache is relatively small, and these packets stop doing
112 * anything when there are too many descriptors.
113 */
114 tu_cs_emit_pkt7(cs, opcode, 3);
115 tu_cs_emit(cs,
116 CP_LOAD_STATE6_0_STATE_TYPE(st) |
117 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
118 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
119 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
120 tu_cs_emit_qw(cs, offset | (base << 28));
121 }
122
123 static unsigned
124 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
125 {
126 const unsigned load_state_size = 4;
127 unsigned size = 0;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
130 for (unsigned j = 0; j < set_layout->binding_count; j++) {
131 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
132 unsigned count = 0;
133 /* Note: some users, like amber for example, pass in
134 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
135 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
136 */
137 VkShaderStageFlags stages = compute ?
138 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
139 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
140 unsigned stage_count = util_bitcount(stages);
141 switch (binding->type) {
142 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
143 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
144 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
145 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
146 /* IBO-backed resources only need one packet for all graphics stages */
147 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
148 count += 1;
149 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
150 count += 1;
151 break;
152 case VK_DESCRIPTOR_TYPE_SAMPLER:
153 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
154 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
155 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
156 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
157 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
158 /* Textures and UBO's needs a packet for each stage */
159 count = stage_count;
160 break;
161 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
162 /* Because of how we pack combined images and samplers, we
163 * currently can't use one packet for the whole array.
164 */
165 count = stage_count * binding->array_size * 2;
166 break;
167 default:
168 unreachable("bad descriptor type");
169 }
170 size += count * load_state_size;
171 }
172 }
173 return size;
174 }
175
176 static void
177 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
178 {
179 unsigned size = tu6_load_state_size(pipeline->layout, compute);
180 if (size == 0)
181 return;
182
183 struct tu_cs cs;
184 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
185
186 struct tu_pipeline_layout *layout = pipeline->layout;
187 for (unsigned i = 0; i < layout->num_sets; i++) {
188 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
189 for (unsigned j = 0; j < set_layout->binding_count; j++) {
190 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
191 unsigned base = i;
192 unsigned offset = binding->offset / 4;
193 /* Note: some users, like amber for example, pass in
194 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
195 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
196 */
197 VkShaderStageFlags stages = compute ?
198 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
199 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
200 unsigned count = binding->array_size;
201 if (count == 0 || stages == 0)
202 continue;
203 switch (binding->type) {
204 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
205 base = MAX_SETS;
206 offset = (layout->input_attachment_count +
207 layout->set[i].dynamic_offset_start +
208 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
209 /* fallthrough */
210 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
211 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
212 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
213 /* IBO-backed resources only need one packet for all graphics stages */
214 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
215 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
216 base, offset, count);
217 }
218 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
219 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
220 base, offset, count);
221 }
222 break;
223 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
224 base = MAX_SETS;
225 offset = (layout->set[i].input_attachment_start +
226 binding->input_attachment_offset) * A6XX_TEX_CONST_DWORDS;
227 case VK_DESCRIPTOR_TYPE_SAMPLER:
228 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
229 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
230 unsigned stage_log2;
231 for_each_bit(stage_log2, stages) {
232 VkShaderStageFlags stage = 1 << stage_log2;
233 emit_load_state(&cs, tu6_vkstage2opcode(stage),
234 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
235 ST6_SHADER : ST6_CONSTANTS,
236 tu6_tex_stage2sb(stage), base, offset, count);
237 }
238 break;
239 }
240 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
241 base = MAX_SETS;
242 offset = (layout->input_attachment_count +
243 layout->set[i].dynamic_offset_start +
244 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
245 /* fallthrough */
246 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
247 unsigned stage_log2;
248 for_each_bit(stage_log2, stages) {
249 VkShaderStageFlags stage = 1 << stage_log2;
250 emit_load_state(&cs, tu6_vkstage2opcode(stage), ST6_UBO,
251 tu6_ubo_stage2sb(stage), base, offset, count);
252 }
253 break;
254 }
255 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
256 unsigned stage_log2;
257 for_each_bit(stage_log2, stages) {
258 VkShaderStageFlags stage = 1 << stage_log2;
259 /* TODO: We could emit less CP_LOAD_STATE6 if we used
260 * struct-of-arrays instead of array-of-structs.
261 */
262 for (unsigned i = 0; i < count; i++) {
263 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
264 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
265 emit_load_state(&cs, tu6_vkstage2opcode(stage),
266 ST6_CONSTANTS, tu6_tex_stage2sb(stage),
267 base, tex_offset, 1);
268 emit_load_state(&cs, tu6_vkstage2opcode(stage),
269 ST6_SHADER, tu6_tex_stage2sb(stage),
270 base, sam_offset, 1);
271 }
272 }
273 break;
274 }
275 default:
276 unreachable("bad descriptor type");
277 }
278 }
279 }
280
281 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
282 }
283
284 struct tu_pipeline_builder
285 {
286 struct tu_device *device;
287 struct tu_pipeline_cache *cache;
288 struct tu_pipeline_layout *layout;
289 const VkAllocationCallbacks *alloc;
290 const VkGraphicsPipelineCreateInfo *create_info;
291
292 struct tu_shader *shaders[MESA_SHADER_STAGES];
293 uint32_t shader_offsets[MESA_SHADER_STAGES];
294 uint32_t binning_vs_offset;
295 uint32_t shader_total_size;
296
297 bool rasterizer_discard;
298 /* these states are affectd by rasterizer_discard */
299 VkSampleCountFlagBits samples;
300 bool use_color_attachments;
301 bool use_dual_src_blend;
302 uint32_t color_attachment_count;
303 VkFormat color_attachment_formats[MAX_RTS];
304 VkFormat depth_attachment_format;
305 };
306
307 static enum tu_dynamic_state_bits
308 tu_dynamic_state_bit(VkDynamicState state)
309 {
310 switch (state) {
311 case VK_DYNAMIC_STATE_VIEWPORT:
312 return TU_DYNAMIC_VIEWPORT;
313 case VK_DYNAMIC_STATE_SCISSOR:
314 return TU_DYNAMIC_SCISSOR;
315 case VK_DYNAMIC_STATE_LINE_WIDTH:
316 return TU_DYNAMIC_LINE_WIDTH;
317 case VK_DYNAMIC_STATE_DEPTH_BIAS:
318 return TU_DYNAMIC_DEPTH_BIAS;
319 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
320 return TU_DYNAMIC_BLEND_CONSTANTS;
321 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
322 return TU_DYNAMIC_DEPTH_BOUNDS;
323 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
324 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
325 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
326 return TU_DYNAMIC_STENCIL_WRITE_MASK;
327 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
328 return TU_DYNAMIC_STENCIL_REFERENCE;
329 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
330 return TU_DYNAMIC_SAMPLE_LOCATIONS;
331 default:
332 unreachable("invalid dynamic state");
333 return 0;
334 }
335 }
336
337 static gl_shader_stage
338 tu_shader_stage(VkShaderStageFlagBits stage)
339 {
340 switch (stage) {
341 case VK_SHADER_STAGE_VERTEX_BIT:
342 return MESA_SHADER_VERTEX;
343 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
344 return MESA_SHADER_TESS_CTRL;
345 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
346 return MESA_SHADER_TESS_EVAL;
347 case VK_SHADER_STAGE_GEOMETRY_BIT:
348 return MESA_SHADER_GEOMETRY;
349 case VK_SHADER_STAGE_FRAGMENT_BIT:
350 return MESA_SHADER_FRAGMENT;
351 case VK_SHADER_STAGE_COMPUTE_BIT:
352 return MESA_SHADER_COMPUTE;
353 default:
354 unreachable("invalid VkShaderStageFlagBits");
355 return MESA_SHADER_NONE;
356 }
357 }
358
359 static bool
360 tu_logic_op_reads_dst(VkLogicOp op)
361 {
362 switch (op) {
363 case VK_LOGIC_OP_CLEAR:
364 case VK_LOGIC_OP_COPY:
365 case VK_LOGIC_OP_COPY_INVERTED:
366 case VK_LOGIC_OP_SET:
367 return false;
368 default:
369 return true;
370 }
371 }
372
373 static VkBlendFactor
374 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
375 {
376 /* treat dst alpha as 1.0 and avoid reading it */
377 switch (factor) {
378 case VK_BLEND_FACTOR_DST_ALPHA:
379 return VK_BLEND_FACTOR_ONE;
380 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
381 return VK_BLEND_FACTOR_ZERO;
382 default:
383 return factor;
384 }
385 }
386
387 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
388 {
389 switch (factor) {
390 case VK_BLEND_FACTOR_SRC1_COLOR:
391 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
392 case VK_BLEND_FACTOR_SRC1_ALPHA:
393 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
394 return true;
395 default:
396 return false;
397 }
398 }
399
400 static bool
401 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
402 {
403 if (!info)
404 return false;
405
406 for (unsigned i = 0; i < info->attachmentCount; i++) {
407 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
408 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
409 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
410 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
411 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
412 return true;
413 }
414
415 return false;
416 }
417
418 static enum pc_di_primtype
419 tu6_primtype(VkPrimitiveTopology topology)
420 {
421 switch (topology) {
422 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
423 return DI_PT_POINTLIST;
424 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
425 return DI_PT_LINELIST;
426 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
427 return DI_PT_LINESTRIP;
428 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
429 return DI_PT_TRILIST;
430 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
431 return DI_PT_TRISTRIP;
432 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
433 return DI_PT_TRIFAN;
434 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
435 return DI_PT_LINE_ADJ;
436 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
437 return DI_PT_LINESTRIP_ADJ;
438 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
439 return DI_PT_TRI_ADJ;
440 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
441 return DI_PT_TRISTRIP_ADJ;
442 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
443 default:
444 unreachable("invalid primitive topology");
445 return DI_PT_NONE;
446 }
447 }
448
449 static enum adreno_compare_func
450 tu6_compare_func(VkCompareOp op)
451 {
452 switch (op) {
453 case VK_COMPARE_OP_NEVER:
454 return FUNC_NEVER;
455 case VK_COMPARE_OP_LESS:
456 return FUNC_LESS;
457 case VK_COMPARE_OP_EQUAL:
458 return FUNC_EQUAL;
459 case VK_COMPARE_OP_LESS_OR_EQUAL:
460 return FUNC_LEQUAL;
461 case VK_COMPARE_OP_GREATER:
462 return FUNC_GREATER;
463 case VK_COMPARE_OP_NOT_EQUAL:
464 return FUNC_NOTEQUAL;
465 case VK_COMPARE_OP_GREATER_OR_EQUAL:
466 return FUNC_GEQUAL;
467 case VK_COMPARE_OP_ALWAYS:
468 return FUNC_ALWAYS;
469 default:
470 unreachable("invalid VkCompareOp");
471 return FUNC_NEVER;
472 }
473 }
474
475 static enum adreno_stencil_op
476 tu6_stencil_op(VkStencilOp op)
477 {
478 switch (op) {
479 case VK_STENCIL_OP_KEEP:
480 return STENCIL_KEEP;
481 case VK_STENCIL_OP_ZERO:
482 return STENCIL_ZERO;
483 case VK_STENCIL_OP_REPLACE:
484 return STENCIL_REPLACE;
485 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
486 return STENCIL_INCR_CLAMP;
487 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
488 return STENCIL_DECR_CLAMP;
489 case VK_STENCIL_OP_INVERT:
490 return STENCIL_INVERT;
491 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
492 return STENCIL_INCR_WRAP;
493 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
494 return STENCIL_DECR_WRAP;
495 default:
496 unreachable("invalid VkStencilOp");
497 return STENCIL_KEEP;
498 }
499 }
500
501 static enum a3xx_rop_code
502 tu6_rop(VkLogicOp op)
503 {
504 switch (op) {
505 case VK_LOGIC_OP_CLEAR:
506 return ROP_CLEAR;
507 case VK_LOGIC_OP_AND:
508 return ROP_AND;
509 case VK_LOGIC_OP_AND_REVERSE:
510 return ROP_AND_REVERSE;
511 case VK_LOGIC_OP_COPY:
512 return ROP_COPY;
513 case VK_LOGIC_OP_AND_INVERTED:
514 return ROP_AND_INVERTED;
515 case VK_LOGIC_OP_NO_OP:
516 return ROP_NOOP;
517 case VK_LOGIC_OP_XOR:
518 return ROP_XOR;
519 case VK_LOGIC_OP_OR:
520 return ROP_OR;
521 case VK_LOGIC_OP_NOR:
522 return ROP_NOR;
523 case VK_LOGIC_OP_EQUIVALENT:
524 return ROP_EQUIV;
525 case VK_LOGIC_OP_INVERT:
526 return ROP_INVERT;
527 case VK_LOGIC_OP_OR_REVERSE:
528 return ROP_OR_REVERSE;
529 case VK_LOGIC_OP_COPY_INVERTED:
530 return ROP_COPY_INVERTED;
531 case VK_LOGIC_OP_OR_INVERTED:
532 return ROP_OR_INVERTED;
533 case VK_LOGIC_OP_NAND:
534 return ROP_NAND;
535 case VK_LOGIC_OP_SET:
536 return ROP_SET;
537 default:
538 unreachable("invalid VkLogicOp");
539 return ROP_NOOP;
540 }
541 }
542
543 static enum adreno_rb_blend_factor
544 tu6_blend_factor(VkBlendFactor factor)
545 {
546 switch (factor) {
547 case VK_BLEND_FACTOR_ZERO:
548 return FACTOR_ZERO;
549 case VK_BLEND_FACTOR_ONE:
550 return FACTOR_ONE;
551 case VK_BLEND_FACTOR_SRC_COLOR:
552 return FACTOR_SRC_COLOR;
553 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
554 return FACTOR_ONE_MINUS_SRC_COLOR;
555 case VK_BLEND_FACTOR_DST_COLOR:
556 return FACTOR_DST_COLOR;
557 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
558 return FACTOR_ONE_MINUS_DST_COLOR;
559 case VK_BLEND_FACTOR_SRC_ALPHA:
560 return FACTOR_SRC_ALPHA;
561 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
562 return FACTOR_ONE_MINUS_SRC_ALPHA;
563 case VK_BLEND_FACTOR_DST_ALPHA:
564 return FACTOR_DST_ALPHA;
565 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
566 return FACTOR_ONE_MINUS_DST_ALPHA;
567 case VK_BLEND_FACTOR_CONSTANT_COLOR:
568 return FACTOR_CONSTANT_COLOR;
569 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
570 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
571 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
572 return FACTOR_CONSTANT_ALPHA;
573 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
574 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
575 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
576 return FACTOR_SRC_ALPHA_SATURATE;
577 case VK_BLEND_FACTOR_SRC1_COLOR:
578 return FACTOR_SRC1_COLOR;
579 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
580 return FACTOR_ONE_MINUS_SRC1_COLOR;
581 case VK_BLEND_FACTOR_SRC1_ALPHA:
582 return FACTOR_SRC1_ALPHA;
583 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
584 return FACTOR_ONE_MINUS_SRC1_ALPHA;
585 default:
586 unreachable("invalid VkBlendFactor");
587 return FACTOR_ZERO;
588 }
589 }
590
591 static enum a3xx_rb_blend_opcode
592 tu6_blend_op(VkBlendOp op)
593 {
594 switch (op) {
595 case VK_BLEND_OP_ADD:
596 return BLEND_DST_PLUS_SRC;
597 case VK_BLEND_OP_SUBTRACT:
598 return BLEND_SRC_MINUS_DST;
599 case VK_BLEND_OP_REVERSE_SUBTRACT:
600 return BLEND_DST_MINUS_SRC;
601 case VK_BLEND_OP_MIN:
602 return BLEND_MIN_DST_SRC;
603 case VK_BLEND_OP_MAX:
604 return BLEND_MAX_DST_SRC;
605 default:
606 unreachable("invalid VkBlendOp");
607 return BLEND_DST_PLUS_SRC;
608 }
609 }
610
611 static uint32_t
612 emit_xs_config(const struct ir3_shader_variant *sh)
613 {
614 if (sh->instrlen) {
615 return A6XX_SP_VS_CONFIG_ENABLED |
616 COND(sh->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
617 COND(sh->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
618 COND(sh->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
619 COND(sh->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO);
620 } else {
621 return 0;
622 }
623 }
624
625 static void
626 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
627 const struct ir3_shader_variant *vs)
628 {
629 uint32_t sp_vs_ctrl =
630 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
631 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
632 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
633 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
634 if (vs->need_pixlod)
635 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
636 if (vs->need_fine_derivatives)
637 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_DIFF_FINE;
638
639 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
640 tu_cs_emit(cs, sp_vs_ctrl);
641
642 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
643 tu_cs_emit(cs, emit_xs_config(vs));
644 tu_cs_emit(cs, vs->instrlen);
645
646 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
647 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
648 A6XX_HLSQ_VS_CNTL_ENABLED);
649 }
650
651 static void
652 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
653 const struct ir3_shader_variant *hs)
654 {
655 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
656 tu_cs_emit(cs, 0);
657
658 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
659 tu_cs_emit(cs, emit_xs_config(hs));
660 tu_cs_emit(cs, hs->instrlen);
661
662 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
663 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
664 }
665
666 static void
667 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
668 const struct ir3_shader_variant *ds)
669 {
670 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
671 tu_cs_emit(cs, emit_xs_config(ds));
672 tu_cs_emit(cs, ds->instrlen);
673
674 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
675 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
676 }
677
678 static void
679 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
680 const struct ir3_shader_variant *gs)
681 {
682 bool has_gs = gs->type != MESA_SHADER_NONE;
683 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
684 tu_cs_emit(cs, 0);
685
686 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
687 tu_cs_emit(cs, emit_xs_config(gs));
688 tu_cs_emit(cs, gs->instrlen);
689
690 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
691 tu_cs_emit(cs, COND(has_gs, A6XX_HLSQ_GS_CNTL_ENABLED) |
692 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
693 }
694
695 static void
696 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
697 const struct ir3_shader_variant *fs)
698 {
699 uint32_t sp_fs_ctrl =
700 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
701 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
702 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
703 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
704 if (fs->total_in > 0)
705 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
706 if (fs->need_pixlod)
707 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
708 if (fs->need_fine_derivatives)
709 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_DIFF_FINE;
710
711 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
712 tu_cs_emit(cs, sp_fs_ctrl);
713
714 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
715 tu_cs_emit(cs, emit_xs_config(fs));
716 tu_cs_emit(cs, fs->instrlen);
717
718 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
719 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
720 A6XX_HLSQ_FS_CNTL_ENABLED);
721 }
722
723 static void
724 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
725 const struct ir3_shader_variant *v)
726 {
727 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
728 tu_cs_emit(cs, 0xff);
729
730 unsigned constlen = align(v->constlen, 4);
731 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
732 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
733 A6XX_HLSQ_CS_CNTL_ENABLED);
734
735 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
736 tu_cs_emit(cs, emit_xs_config(v));
737 tu_cs_emit(cs, v->instrlen);
738
739 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
740 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
741 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
742 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
743 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
744 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE) |
745 COND(v->need_fine_derivatives, A6XX_SP_CS_CTRL_REG0_DIFF_FINE));
746
747 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
748 tu_cs_emit(cs, 0x41);
749
750 uint32_t local_invocation_id =
751 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
752 uint32_t work_group_id =
753 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
754
755 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
756 tu_cs_emit(cs,
757 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
758 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
759 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
760 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
761 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
762 }
763
764 static void
765 tu6_emit_vs_system_values(struct tu_cs *cs,
766 const struct ir3_shader_variant *vs,
767 const struct ir3_shader_variant *gs,
768 bool primid_passthru)
769 {
770 const uint32_t vertexid_regid =
771 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
772 const uint32_t instanceid_regid =
773 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
774 const uint32_t primitiveid_regid = gs->type != MESA_SHADER_NONE ?
775 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
776 regid(63, 0);
777 const uint32_t gsheader_regid = gs->type != MESA_SHADER_NONE ?
778 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
779 regid(63, 0);
780
781 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
782 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
783 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
784 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
785 0xfc000000);
786 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
787 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
788 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
789 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
790 0xfc00); /* VFD_CONTROL_5 */
791 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
792 }
793
794 /* Add any missing varyings needed for stream-out. Otherwise varyings not
795 * used by fragment shader will be stripped out.
796 */
797 static void
798 tu6_link_streamout(struct ir3_shader_linkage *l,
799 const struct ir3_shader_variant *v)
800 {
801 const struct ir3_stream_output_info *info = &v->shader->stream_output;
802
803 /*
804 * First, any stream-out varyings not already in linkage map (ie. also
805 * consumed by frag shader) need to be added:
806 */
807 for (unsigned i = 0; i < info->num_outputs; i++) {
808 const struct ir3_stream_output *out = &info->output[i];
809 unsigned compmask =
810 (1 << (out->num_components + out->start_component)) - 1;
811 unsigned k = out->register_index;
812 unsigned idx, nextloc = 0;
813
814 /* psize/pos need to be the last entries in linkage map, and will
815 * get added link_stream_out, so skip over them:
816 */
817 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
818 v->outputs[k].slot == VARYING_SLOT_POS)
819 continue;
820
821 for (idx = 0; idx < l->cnt; idx++) {
822 if (l->var[idx].regid == v->outputs[k].regid)
823 break;
824 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
825 }
826
827 /* add if not already in linkage map: */
828 if (idx == l->cnt)
829 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
830
831 /* expand component-mask if needed, ie streaming out all components
832 * but frag shader doesn't consume all components:
833 */
834 if (compmask & ~l->var[idx].compmask) {
835 l->var[idx].compmask |= compmask;
836 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
837 util_last_bit(l->var[idx].compmask));
838 }
839 }
840 }
841
842 static void
843 tu6_setup_streamout(const struct ir3_shader_variant *v,
844 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
845 {
846 const struct ir3_stream_output_info *info = &v->shader->stream_output;
847
848 memset(tf, 0, sizeof(*tf));
849
850 tf->prog_count = align(l->max_loc, 2) / 2;
851
852 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
853
854 /* set stride info to the streamout state */
855 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
856 tf->stride[i] = info->stride[i];
857
858 for (unsigned i = 0; i < info->num_outputs; i++) {
859 const struct ir3_stream_output *out = &info->output[i];
860 unsigned k = out->register_index;
861 unsigned idx;
862
863 /* Skip it, if there's an unused reg in the middle of outputs. */
864 if (v->outputs[k].regid == INVALID_REG)
865 continue;
866
867 tf->ncomp[out->output_buffer] += out->num_components;
868
869 /* linkage map sorted by order frag shader wants things, so
870 * a bit less ideal here..
871 */
872 for (idx = 0; idx < l->cnt; idx++)
873 if (l->var[idx].regid == v->outputs[k].regid)
874 break;
875
876 debug_assert(idx < l->cnt);
877
878 for (unsigned j = 0; j < out->num_components; j++) {
879 unsigned c = j + out->start_component;
880 unsigned loc = l->var[idx].loc + c;
881 unsigned off = j + out->dst_offset; /* in dwords */
882
883 if (loc & 1) {
884 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
885 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
886 A6XX_VPC_SO_PROG_B_OFF(off * 4);
887 } else {
888 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
889 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
890 A6XX_VPC_SO_PROG_A_OFF(off * 4);
891 }
892 }
893 }
894
895 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
896 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
897 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
898 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
899 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
900 }
901
902 static void
903 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
904 enum a6xx_state_block block, uint32_t offset,
905 uint32_t size, uint32_t *dwords) {
906 assert(size % 4 == 0);
907
908 tu_cs_emit_pkt7(cs, opcode, 3 + size);
909 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
910 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
911 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
912 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
913 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
914
915 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
916 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
917 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
918
919 tu_cs_emit_array(cs, dwords, size);
920 }
921
922 static void
923 tu6_emit_link_map(struct tu_cs *cs,
924 const struct ir3_shader_variant *producer,
925 const struct ir3_shader_variant *consumer) {
926 const struct ir3_const_state *const_state = &consumer->shader->const_state;
927 uint32_t base = const_state->offsets.primitive_map;
928 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
929 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
930 int size = DIV_ROUND_UP(num_loc, 4);
931
932 size = (MIN2(size + base, consumer->constlen) - base) * 4;
933 if (size <= 0)
934 return;
935
936 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
937 patch_locs);
938 }
939
940 static uint16_t
941 gl_primitive_to_tess(uint16_t primitive) {
942 switch (primitive) {
943 case GL_POINTS:
944 return TESS_POINTS;
945 case GL_LINE_STRIP:
946 return TESS_LINES;
947 case GL_TRIANGLE_STRIP:
948 return TESS_CW_TRIS;
949 default:
950 unreachable("");
951 }
952 }
953
954 static void
955 tu6_emit_vpc(struct tu_cs *cs,
956 const struct ir3_shader_variant *vs,
957 const struct ir3_shader_variant *gs,
958 const struct ir3_shader_variant *fs,
959 bool binning_pass,
960 struct tu_streamout_state *tf)
961 {
962 bool has_gs = gs->type != MESA_SHADER_NONE;
963 const struct ir3_shader_variant *last_shader = has_gs ? gs : vs;
964 struct ir3_shader_linkage linkage = { 0 };
965 ir3_link_shaders(&linkage, last_shader, fs, true);
966
967 if (last_shader->shader->stream_output.num_outputs)
968 tu6_link_streamout(&linkage, last_shader);
969
970 /* We do this after linking shaders in order to know whether PrimID
971 * passthrough needs to be enabled.
972 */
973 bool primid_passthru = linkage.primid_loc != 0xff;
974 tu6_emit_vs_system_values(cs, vs, gs, primid_passthru);
975
976 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
977 tu_cs_emit(cs, ~linkage.varmask[0]);
978 tu_cs_emit(cs, ~linkage.varmask[1]);
979 tu_cs_emit(cs, ~linkage.varmask[2]);
980 tu_cs_emit(cs, ~linkage.varmask[3]);
981
982 /* a6xx finds position/pointsize at the end */
983 const uint32_t position_regid =
984 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
985 const uint32_t pointsize_regid =
986 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
987 const uint32_t layer_regid = has_gs ?
988 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
989
990 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
991 if (layer_regid != regid(63, 0)) {
992 layer_loc = linkage.max_loc;
993 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
994 }
995 if (position_regid != regid(63, 0)) {
996 position_loc = linkage.max_loc;
997 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
998 }
999 if (pointsize_regid != regid(63, 0)) {
1000 pointsize_loc = linkage.max_loc;
1001 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
1002 }
1003
1004 if (last_shader->shader->stream_output.num_outputs)
1005 tu6_setup_streamout(last_shader, &linkage, tf);
1006
1007 /* map outputs of the last shader to VPC */
1008 assert(linkage.cnt <= 32);
1009 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
1010 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
1011 uint32_t sp_out[16];
1012 uint32_t sp_vpc_dst[8];
1013 for (uint32_t i = 0; i < linkage.cnt; i++) {
1014 ((uint16_t *) sp_out)[i] =
1015 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
1016 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
1017 ((uint8_t *) sp_vpc_dst)[i] =
1018 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
1019 }
1020
1021 if (has_gs)
1022 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
1023 else
1024 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
1025 tu_cs_emit_array(cs, sp_out, sp_out_count);
1026
1027 if (has_gs)
1028 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
1029 else
1030 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
1031 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
1032
1033 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
1034 tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
1035
1036 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
1037 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
1038 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
1039 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
1040 A6XX_VPC_CNTL_0_UNKLOC(0xff));
1041
1042 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
1043 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
1044 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
1045 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
1046
1047 if (has_gs) {
1048 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1049 tu_cs_emit(cs, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
1050 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
1051 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
1052 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
1053
1054 tu6_emit_link_map(cs, vs, gs);
1055
1056 uint32_t primitive_regid =
1057 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
1058 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
1059 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
1060 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
1061 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
1062
1063 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
1064 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
1065
1066 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
1067 tu_cs_emit(cs, CONDREG(layer_regid,
1068 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
1069
1070 uint32_t flags_regid = ir3_find_output_regid(gs,
1071 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
1072
1073 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
1074 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
1075 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
1076
1077 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
1078 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
1079 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
1080 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
1081 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
1082
1083 uint32_t vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
1084 uint16_t output =
1085 gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
1086 uint32_t invocations = gs->shader->nir->info.gs.invocations - 1;
1087 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1088 tu_cs_emit(cs,
1089 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1090 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1091 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1092
1093 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1094 tu_cs_emit(cs, 0);
1095
1096 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
1097 tu_cs_emit(cs, 0);
1098
1099 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1100 tu_cs_emit(cs, 0xff);
1101
1102 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
1103 tu_cs_emit(cs, 0xffff00);
1104
1105 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1106 uint32_t vec4_size =
1107 gs->shader->nir->info.gs.vertices_in *
1108 DIV_ROUND_UP(vs->shader->output_size, 4);
1109 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1110 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1111
1112 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
1113 tu_cs_emit(cs, 0);
1114
1115 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
1116 tu_cs_emit(cs, vs->shader->output_size);
1117 }
1118
1119 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
1120 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
1121
1122 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
1123 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
1124 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
1125 }
1126
1127 static int
1128 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1129 uint32_t index,
1130 uint8_t *interp_mode,
1131 uint8_t *ps_repl_mode)
1132 {
1133 enum
1134 {
1135 INTERP_SMOOTH = 0,
1136 INTERP_FLAT = 1,
1137 INTERP_ZERO = 2,
1138 INTERP_ONE = 3,
1139 };
1140 enum
1141 {
1142 PS_REPL_NONE = 0,
1143 PS_REPL_S = 1,
1144 PS_REPL_T = 2,
1145 PS_REPL_ONE_MINUS_T = 3,
1146 };
1147
1148 const uint32_t compmask = fs->inputs[index].compmask;
1149
1150 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1151 * fourth component occupy three consecutive varying slots
1152 */
1153 int shift = 0;
1154 *interp_mode = 0;
1155 *ps_repl_mode = 0;
1156 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1157 if (compmask & 0x1) {
1158 *ps_repl_mode |= PS_REPL_S << shift;
1159 shift += 2;
1160 }
1161 if (compmask & 0x2) {
1162 *ps_repl_mode |= PS_REPL_T << shift;
1163 shift += 2;
1164 }
1165 if (compmask & 0x4) {
1166 *interp_mode |= INTERP_ZERO << shift;
1167 shift += 2;
1168 }
1169 if (compmask & 0x8) {
1170 *interp_mode |= INTERP_ONE << 6;
1171 shift += 2;
1172 }
1173 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1174 fs->inputs[index].rasterflat) {
1175 for (int i = 0; i < 4; i++) {
1176 if (compmask & (1 << i)) {
1177 *interp_mode |= INTERP_FLAT << shift;
1178 shift += 2;
1179 }
1180 }
1181 }
1182
1183 return shift;
1184 }
1185
1186 static void
1187 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1188 const struct ir3_shader_variant *fs,
1189 bool binning_pass)
1190 {
1191 uint32_t interp_modes[8] = { 0 };
1192 uint32_t ps_repl_modes[8] = { 0 };
1193
1194 if (!binning_pass) {
1195 for (int i = -1;
1196 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1197
1198 /* get the mode for input i */
1199 uint8_t interp_mode;
1200 uint8_t ps_repl_mode;
1201 const int bits =
1202 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1203
1204 /* OR the mode into the array */
1205 const uint32_t inloc = fs->inputs[i].inloc * 2;
1206 uint32_t n = inloc / 32;
1207 uint32_t shift = inloc % 32;
1208 interp_modes[n] |= interp_mode << shift;
1209 ps_repl_modes[n] |= ps_repl_mode << shift;
1210 if (shift + bits > 32) {
1211 n++;
1212 shift = 32 - shift;
1213
1214 interp_modes[n] |= interp_mode >> shift;
1215 ps_repl_modes[n] |= ps_repl_mode >> shift;
1216 }
1217 }
1218 }
1219
1220 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1221 tu_cs_emit_array(cs, interp_modes, 8);
1222
1223 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1224 tu_cs_emit_array(cs, ps_repl_modes, 8);
1225 }
1226
1227 static void
1228 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1229 {
1230 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1231 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
1232 uint32_t smask_in_regid;
1233
1234 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
1235 bool enable_varyings = fs->total_in > 0;
1236
1237 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1238 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1239 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1240 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1241 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1242 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1243 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1244 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1245 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1246
1247 if (fs->num_sampler_prefetch > 0) {
1248 assert(VALIDREG(ij_pix_regid));
1249 /* also, it seems like ij_pix is *required* to be r0.x */
1250 assert(ij_pix_regid == regid(0, 0));
1251 }
1252
1253 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1254 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1255 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1256 0x7000); // XXX);
1257 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1258 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1259 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1260 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1261 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1262 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1263 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1264 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1265 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1266 }
1267
1268 if (fs->num_sampler_prefetch > 0) {
1269 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1270 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1271 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1272 tu_cs_emit(cs,
1273 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1274 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1275 }
1276 }
1277
1278 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1279 tu_cs_emit(cs, 0x7);
1280 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1281 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1282 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1283 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1284 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1285 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1286 0xfc00fc00);
1287 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1288 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1289 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1290 0x0000fc00);
1291 tu_cs_emit(cs, 0xfc);
1292
1293 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1294 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1295
1296 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1297 tu_cs_emit(cs, 0xff); /* XXX */
1298
1299 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1300 tu_cs_emit(cs,
1301 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1302 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1303 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1304 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1305 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1306 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
1307 A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
1308 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1309
1310 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1311 tu_cs_emit(cs,
1312 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1313 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1314 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1315 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1316 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1317 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1318 COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
1319 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
1320 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1321 tu_cs_emit(cs,
1322 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1323 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1324 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1325 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1326
1327 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1328 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1329
1330 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1331 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1332
1333 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1334 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1335 }
1336
1337 static void
1338 tu6_emit_fs_outputs(struct tu_cs *cs,
1339 const struct ir3_shader_variant *fs,
1340 uint32_t mrt_count, bool dual_src_blend)
1341 {
1342 uint32_t smask_regid, posz_regid;
1343
1344 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1345 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1346
1347 uint32_t fragdata_regid[8];
1348 if (fs->color0_mrt) {
1349 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1350 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1351 fragdata_regid[i] = fragdata_regid[0];
1352 } else {
1353 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1354 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1355 }
1356
1357 uint32_t render_components = (1 << (4 * mrt_count)) - 1;
1358
1359 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1360 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1361 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1362 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
1363 0xfc000000);
1364 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1365
1366 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1367 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1368 // TODO we could have a mix of half and full precision outputs,
1369 // we really need to figure out half-precision from IR3_REG_HALF
1370 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1371 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1372 }
1373
1374 tu_cs_emit_regs(cs,
1375 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1376
1377 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1378 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1379 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1380 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1381 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1382
1383 tu_cs_emit_regs(cs,
1384 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1385
1386 uint32_t gras_su_depth_plane_cntl = 0;
1387 uint32_t rb_depth_plane_cntl = 0;
1388 if (fs->no_earlyz || fs->writes_pos) {
1389 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1390 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1391 }
1392
1393 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1394 tu_cs_emit(cs, gras_su_depth_plane_cntl);
1395
1396 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1397 tu_cs_emit(cs, rb_depth_plane_cntl);
1398 }
1399
1400 static void
1401 tu6_emit_shader_object(struct tu_cs *cs,
1402 gl_shader_stage stage,
1403 const struct ir3_shader_variant *variant,
1404 const struct tu_bo *binary_bo,
1405 uint32_t binary_offset)
1406 {
1407 uint16_t reg;
1408 uint8_t opcode;
1409 enum a6xx_state_block sb;
1410 switch (stage) {
1411 case MESA_SHADER_VERTEX:
1412 reg = REG_A6XX_SP_VS_OBJ_START_LO;
1413 opcode = CP_LOAD_STATE6_GEOM;
1414 sb = SB6_VS_SHADER;
1415 break;
1416 case MESA_SHADER_TESS_CTRL:
1417 reg = REG_A6XX_SP_HS_OBJ_START_LO;
1418 opcode = CP_LOAD_STATE6_GEOM;
1419 sb = SB6_HS_SHADER;
1420 break;
1421 case MESA_SHADER_TESS_EVAL:
1422 reg = REG_A6XX_SP_DS_OBJ_START_LO;
1423 opcode = CP_LOAD_STATE6_GEOM;
1424 sb = SB6_DS_SHADER;
1425 break;
1426 case MESA_SHADER_GEOMETRY:
1427 reg = REG_A6XX_SP_GS_OBJ_START_LO;
1428 opcode = CP_LOAD_STATE6_GEOM;
1429 sb = SB6_GS_SHADER;
1430 break;
1431 case MESA_SHADER_FRAGMENT:
1432 reg = REG_A6XX_SP_FS_OBJ_START_LO;
1433 opcode = CP_LOAD_STATE6_FRAG;
1434 sb = SB6_FS_SHADER;
1435 break;
1436 case MESA_SHADER_COMPUTE:
1437 reg = REG_A6XX_SP_CS_OBJ_START_LO;
1438 opcode = CP_LOAD_STATE6_FRAG;
1439 sb = SB6_CS_SHADER;
1440 break;
1441 default:
1442 unreachable("invalid gl_shader_stage");
1443 opcode = CP_LOAD_STATE6_GEOM;
1444 sb = SB6_VS_SHADER;
1445 break;
1446 }
1447
1448 if (!variant->instrlen) {
1449 tu_cs_emit_pkt4(cs, reg, 2);
1450 tu_cs_emit_qw(cs, 0);
1451 return;
1452 }
1453
1454 assert(variant->type == stage);
1455
1456 const uint64_t binary_iova = binary_bo->iova + binary_offset;
1457 assert((binary_iova & 0xf) == 0);
1458 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1459 * of the shader. this could be a potential source of problems at some point
1460 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1461 */
1462
1463 tu_cs_emit_pkt4(cs, reg, 2);
1464 tu_cs_emit_qw(cs, binary_iova);
1465
1466 /* always indirect */
1467 const bool indirect = true;
1468 if (indirect) {
1469 tu_cs_emit_pkt7(cs, opcode, 3);
1470 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1471 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1472 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1473 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1474 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1475 tu_cs_emit_qw(cs, binary_iova);
1476 } else {
1477 const void *binary = binary_bo->map + binary_offset;
1478
1479 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
1480 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1481 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1482 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1483 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1484 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1485 tu_cs_emit_qw(cs, 0);
1486 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
1487 }
1488 }
1489
1490 static void
1491 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
1492 uint32_t opcode, enum a6xx_state_block block)
1493 {
1494 /* dummy variant */
1495 if (!v->shader)
1496 return;
1497
1498 const struct ir3_const_state *const_state = &v->shader->const_state;
1499 uint32_t base = const_state->offsets.immediate;
1500 int size = const_state->immediates_count;
1501
1502 /* truncate size to avoid writing constants that shader
1503 * does not use:
1504 */
1505 size = MIN2(size + base, v->constlen) - base;
1506
1507 if (size <= 0)
1508 return;
1509
1510 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1511 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1512 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1513 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1514 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1515 CP_LOAD_STATE6_0_NUM_UNIT(size));
1516 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1517 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1518
1519 for (unsigned i = 0; i < size; i++) {
1520 tu_cs_emit(cs, const_state->immediates[i].val[0]);
1521 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1522 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1523 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1524 }
1525 }
1526
1527 static void
1528 tu6_emit_geometry_consts(struct tu_cs *cs,
1529 const struct ir3_shader_variant *vs,
1530 const struct ir3_shader_variant *gs) {
1531 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1532
1533 uint32_t params[4] = {
1534 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1535 vs->shader->output_size * 4, /* vertex stride */
1536 0,
1537 0,
1538 };
1539 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1540 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1541 ARRAY_SIZE(params), params);
1542
1543 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1544 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1545 ARRAY_SIZE(params), params);
1546 }
1547
1548 static void
1549 tu6_emit_program(struct tu_cs *cs,
1550 const struct tu_pipeline_builder *builder,
1551 const struct tu_bo *binary_bo,
1552 bool binning_pass,
1553 struct tu_streamout_state *tf)
1554 {
1555 static const struct ir3_shader_variant dummy_variant = {
1556 .type = MESA_SHADER_NONE
1557 };
1558 assert(builder->shaders[MESA_SHADER_VERTEX]);
1559 const struct ir3_shader_variant *vs =
1560 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1561 const struct ir3_shader_variant *hs =
1562 builder->shaders[MESA_SHADER_TESS_CTRL]
1563 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1564 : &dummy_variant;
1565 const struct ir3_shader_variant *ds =
1566 builder->shaders[MESA_SHADER_TESS_EVAL]
1567 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1568 : &dummy_variant;
1569 const struct ir3_shader_variant *gs =
1570 builder->shaders[MESA_SHADER_GEOMETRY]
1571 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1572 : &dummy_variant;
1573 const struct ir3_shader_variant *fs =
1574 builder->shaders[MESA_SHADER_FRAGMENT]
1575 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1576 : &dummy_variant;
1577 bool has_gs = gs->type != MESA_SHADER_NONE;
1578
1579 if (binning_pass) {
1580 /* if we have streamout, use full VS in binning pass, as the
1581 * binning pass VS will have outputs on other than position/psize
1582 * stripped out:
1583 */
1584 if (vs->shader->stream_output.num_outputs == 0)
1585 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1586 fs = &dummy_variant;
1587 }
1588
1589 tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1590 tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1591 tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1592 tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1593 tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1594
1595 tu6_emit_vpc(cs, vs, gs, fs, binning_pass, tf);
1596 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1597 tu6_emit_fs_inputs(cs, fs);
1598 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1599 builder->use_dual_src_blend);
1600
1601 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1602 binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1603 if (has_gs)
1604 tu6_emit_shader_object(cs, MESA_SHADER_GEOMETRY, gs, binary_bo,
1605 builder->shader_offsets[MESA_SHADER_GEOMETRY]);
1606 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1607 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1608
1609 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1610 if (has_gs) {
1611 tu6_emit_immediates(cs, gs, CP_LOAD_STATE6_GEOM, SB6_GS_SHADER);
1612 tu6_emit_geometry_consts(cs, vs, gs);
1613 }
1614 if (!binning_pass)
1615 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1616 }
1617
1618 static void
1619 tu6_emit_vertex_input(struct tu_cs *cs,
1620 const struct ir3_shader_variant *vs,
1621 const VkPipelineVertexInputStateCreateInfo *info,
1622 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1623 uint32_t *count)
1624 {
1625 uint32_t vfd_fetch_idx = 0;
1626 uint32_t vfd_decode_idx = 0;
1627 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1628
1629 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1630 const VkVertexInputBindingDescription *binding =
1631 &info->pVertexBindingDescriptions[i];
1632
1633 tu_cs_emit_regs(cs,
1634 A6XX_VFD_FETCH_STRIDE(vfd_fetch_idx, binding->stride));
1635
1636 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1637 binding_instanced |= 1 << binding->binding;
1638
1639 bindings[vfd_fetch_idx] = binding->binding;
1640 vfd_fetch_idx++;
1641 }
1642
1643 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1644
1645 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1646 const VkVertexInputAttributeDescription *attr =
1647 &info->pVertexAttributeDescriptions[i];
1648 uint32_t binding_idx, input_idx;
1649
1650 for (binding_idx = 0; binding_idx < vfd_fetch_idx; binding_idx++) {
1651 if (bindings[binding_idx] == attr->binding)
1652 break;
1653 }
1654 assert(binding_idx < vfd_fetch_idx);
1655
1656 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1657 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1658 break;
1659 }
1660
1661 /* attribute not used, skip it */
1662 if (input_idx == vs->inputs_count)
1663 continue;
1664
1665 const struct tu_native_format format = tu6_format_vtx(attr->format);
1666 tu_cs_emit_regs(cs,
1667 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1668 .idx = binding_idx,
1669 .offset = attr->offset,
1670 .instanced = binding_instanced & (1 << attr->binding),
1671 .format = format.fmt,
1672 .swap = format.swap,
1673 .unk30 = 1,
1674 ._float = !vk_format_is_int(attr->format)),
1675 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1676
1677 tu_cs_emit_regs(cs,
1678 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1679 .writemask = vs->inputs[input_idx].compmask,
1680 .regid = vs->inputs[input_idx].regid));
1681
1682 vfd_decode_idx++;
1683 }
1684
1685 tu_cs_emit_regs(cs,
1686 A6XX_VFD_CONTROL_0(
1687 .fetch_cnt = vfd_fetch_idx,
1688 .decode_cnt = vfd_decode_idx));
1689
1690 *count = vfd_fetch_idx;
1691 }
1692
1693 static uint32_t
1694 tu6_guardband_adj(uint32_t v)
1695 {
1696 if (v > 256)
1697 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1698 else
1699 return 511;
1700 }
1701
1702 void
1703 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1704 {
1705 float offsets[3];
1706 float scales[3];
1707 scales[0] = viewport->width / 2.0f;
1708 scales[1] = viewport->height / 2.0f;
1709 scales[2] = viewport->maxDepth - viewport->minDepth;
1710 offsets[0] = viewport->x + scales[0];
1711 offsets[1] = viewport->y + scales[1];
1712 offsets[2] = viewport->minDepth;
1713
1714 VkOffset2D min;
1715 VkOffset2D max;
1716 min.x = (int32_t) viewport->x;
1717 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1718 if (viewport->height >= 0.0f) {
1719 min.y = (int32_t) viewport->y;
1720 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1721 } else {
1722 min.y = (int32_t)(viewport->y + viewport->height);
1723 max.y = (int32_t) ceilf(viewport->y);
1724 }
1725 /* the spec allows viewport->height to be 0.0f */
1726 if (min.y == max.y)
1727 max.y++;
1728 assert(min.x >= 0 && min.x < max.x);
1729 assert(min.y >= 0 && min.y < max.y);
1730
1731 VkExtent2D guardband_adj;
1732 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1733 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1734
1735 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1736 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1737 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1738 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1739 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1740 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1741 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1742
1743 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1744 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1745 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1746 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1747 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1748
1749 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1750 tu_cs_emit(cs,
1751 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1752 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1753
1754 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1755 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1756
1757 tu_cs_emit_regs(cs,
1758 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1759 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1760
1761 tu_cs_emit_regs(cs,
1762 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1763 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1764 }
1765
1766 void
1767 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1768 {
1769 const VkOffset2D min = scissor->offset;
1770 const VkOffset2D max = {
1771 scissor->offset.x + scissor->extent.width,
1772 scissor->offset.y + scissor->extent.height,
1773 };
1774
1775 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1776 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1777 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1778 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1779 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1780 }
1781
1782 void
1783 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1784 {
1785 if (!samp_loc) {
1786 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1787 tu_cs_emit(cs, 0);
1788
1789 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1790 tu_cs_emit(cs, 0);
1791
1792 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1793 tu_cs_emit(cs, 0);
1794 return;
1795 }
1796
1797 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1798 assert(samp_loc->sampleLocationGridSize.width == 1);
1799 assert(samp_loc->sampleLocationGridSize.height == 1);
1800
1801 uint32_t sample_config =
1802 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1803 uint32_t sample_locations = 0;
1804 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1805 sample_locations |=
1806 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1807 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1808 }
1809
1810 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1811 tu_cs_emit(cs, sample_config);
1812 tu_cs_emit(cs, sample_locations);
1813
1814 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1815 tu_cs_emit(cs, sample_config);
1816 tu_cs_emit(cs, sample_locations);
1817
1818 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1819 tu_cs_emit(cs, sample_config);
1820 tu_cs_emit(cs, sample_locations);
1821 }
1822
1823 static void
1824 tu6_emit_gras_unknowns(struct tu_cs *cs)
1825 {
1826 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1827 tu_cs_emit(cs, 0x0);
1828 }
1829
1830 static void
1831 tu6_emit_point_size(struct tu_cs *cs)
1832 {
1833 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1834 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1835 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1836 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1837 }
1838
1839 static uint32_t
1840 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1841 VkSampleCountFlagBits samples)
1842 {
1843 uint32_t gras_su_cntl = 0;
1844
1845 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1846 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1847 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1848 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1849
1850 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1851 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1852
1853 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1854
1855 if (rast_info->depthBiasEnable)
1856 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1857
1858 if (samples > VK_SAMPLE_COUNT_1_BIT)
1859 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1860
1861 return gras_su_cntl;
1862 }
1863
1864 void
1865 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1866 uint32_t gras_su_cntl,
1867 float line_width)
1868 {
1869 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1870 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1871
1872 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1873 tu_cs_emit(cs, gras_su_cntl);
1874 }
1875
1876 void
1877 tu6_emit_depth_bias(struct tu_cs *cs,
1878 float constant_factor,
1879 float clamp,
1880 float slope_factor)
1881 {
1882 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1883 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1884 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1885 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1886 }
1887
1888 static void
1889 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1890 {
1891 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1892 tu_cs_emit(cs, 0);
1893 }
1894
1895 static void
1896 tu6_emit_depth_control(struct tu_cs *cs,
1897 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1898 const VkPipelineRasterizationStateCreateInfo *rast_info)
1899 {
1900 assert(!ds_info->depthBoundsTestEnable);
1901
1902 uint32_t rb_depth_cntl = 0;
1903 if (ds_info->depthTestEnable) {
1904 rb_depth_cntl |=
1905 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1906 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1907 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1908
1909 if (rast_info->depthClampEnable)
1910 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1911
1912 if (ds_info->depthWriteEnable)
1913 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1914 }
1915
1916 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1917 tu_cs_emit(cs, rb_depth_cntl);
1918 }
1919
1920 static void
1921 tu6_emit_stencil_control(struct tu_cs *cs,
1922 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1923 {
1924 uint32_t rb_stencil_control = 0;
1925 if (ds_info->stencilTestEnable) {
1926 const VkStencilOpState *front = &ds_info->front;
1927 const VkStencilOpState *back = &ds_info->back;
1928 rb_stencil_control |=
1929 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1930 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1931 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1932 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1933 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1934 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1935 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1936 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1937 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1938 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1939 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1940 }
1941
1942 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1943 tu_cs_emit(cs, rb_stencil_control);
1944 }
1945
1946 void
1947 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1948 {
1949 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1950 tu_cs_emit(
1951 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1952 }
1953
1954 void
1955 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1956 {
1957 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1958 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1959 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1960 }
1961
1962 void
1963 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1964 {
1965 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1966 tu_cs_emit(cs,
1967 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1968 }
1969
1970 static uint32_t
1971 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1972 bool has_alpha)
1973 {
1974 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1975 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1976 has_alpha ? att->srcColorBlendFactor
1977 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1978 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1979 has_alpha ? att->dstColorBlendFactor
1980 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1981 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1982 const enum adreno_rb_blend_factor src_alpha_factor =
1983 tu6_blend_factor(att->srcAlphaBlendFactor);
1984 const enum adreno_rb_blend_factor dst_alpha_factor =
1985 tu6_blend_factor(att->dstAlphaBlendFactor);
1986
1987 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1988 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1989 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1990 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1991 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1992 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1993 }
1994
1995 static uint32_t
1996 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1997 uint32_t rb_mrt_control_rop,
1998 bool is_int,
1999 bool has_alpha)
2000 {
2001 uint32_t rb_mrt_control =
2002 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
2003
2004 /* ignore blending and logic op for integer attachments */
2005 if (is_int) {
2006 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
2007 return rb_mrt_control;
2008 }
2009
2010 rb_mrt_control |= rb_mrt_control_rop;
2011
2012 if (att->blendEnable) {
2013 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
2014
2015 if (has_alpha)
2016 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
2017 }
2018
2019 return rb_mrt_control;
2020 }
2021
2022 static void
2023 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
2024 const VkPipelineColorBlendStateCreateInfo *blend_info,
2025 const VkFormat attachment_formats[MAX_RTS],
2026 uint32_t *blend_enable_mask)
2027 {
2028 *blend_enable_mask = 0;
2029
2030 bool rop_reads_dst = false;
2031 uint32_t rb_mrt_control_rop = 0;
2032 if (blend_info->logicOpEnable) {
2033 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
2034 rb_mrt_control_rop =
2035 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
2036 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
2037 }
2038
2039 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
2040 const VkPipelineColorBlendAttachmentState *att =
2041 &blend_info->pAttachments[i];
2042 const VkFormat format = attachment_formats[i];
2043
2044 uint32_t rb_mrt_control = 0;
2045 uint32_t rb_mrt_blend_control = 0;
2046 if (format != VK_FORMAT_UNDEFINED) {
2047 const bool is_int = vk_format_is_int(format);
2048 const bool has_alpha = vk_format_has_alpha(format);
2049
2050 rb_mrt_control =
2051 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
2052 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
2053
2054 if (att->blendEnable || rop_reads_dst)
2055 *blend_enable_mask |= 1 << i;
2056 }
2057
2058 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
2059 tu_cs_emit(cs, rb_mrt_control);
2060 tu_cs_emit(cs, rb_mrt_blend_control);
2061 }
2062 }
2063
2064 static void
2065 tu6_emit_blend_control(struct tu_cs *cs,
2066 uint32_t blend_enable_mask,
2067 bool dual_src_blend,
2068 const VkPipelineMultisampleStateCreateInfo *msaa_info)
2069 {
2070 assert(!msaa_info->alphaToOneEnable);
2071
2072 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
2073 if (blend_enable_mask)
2074 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
2075 if (dual_src_blend)
2076 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE;
2077 if (msaa_info->alphaToCoverageEnable)
2078 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
2079
2080 const uint32_t sample_mask =
2081 msaa_info->pSampleMask ? *msaa_info->pSampleMask
2082 : ((1 << msaa_info->rasterizationSamples) - 1);
2083
2084 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
2085 uint32_t rb_blend_cntl =
2086 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
2087 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
2088 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
2089 if (dual_src_blend)
2090 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE;
2091 if (msaa_info->alphaToCoverageEnable)
2092 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
2093
2094 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
2095 tu_cs_emit(cs, sp_blend_cntl);
2096
2097 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
2098 tu_cs_emit(cs, rb_blend_cntl);
2099 }
2100
2101 void
2102 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
2103 {
2104 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2105 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
2106 }
2107
2108 static VkResult
2109 tu_pipeline_create(struct tu_device *dev,
2110 struct tu_pipeline_layout *layout,
2111 bool compute,
2112 const VkAllocationCallbacks *pAllocator,
2113 struct tu_pipeline **out_pipeline)
2114 {
2115 struct tu_pipeline *pipeline =
2116 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
2117 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2118 if (!pipeline)
2119 return VK_ERROR_OUT_OF_HOST_MEMORY;
2120
2121 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
2122
2123 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
2124 * that LOAD_STATE can potentially take up a large amount of space so we
2125 * calculate its size explicitly.
2126 */
2127 unsigned load_state_size = tu6_load_state_size(layout, compute);
2128 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size);
2129 if (result != VK_SUCCESS) {
2130 vk_free2(&dev->alloc, pAllocator, pipeline);
2131 return result;
2132 }
2133
2134 *out_pipeline = pipeline;
2135
2136 return VK_SUCCESS;
2137 }
2138
2139 static VkResult
2140 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
2141 {
2142 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
2143 NULL
2144 };
2145 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
2146 gl_shader_stage stage =
2147 tu_shader_stage(builder->create_info->pStages[i].stage);
2148 stage_infos[stage] = &builder->create_info->pStages[i];
2149 }
2150
2151 struct tu_shader_compile_options options;
2152 tu_shader_compile_options_init(&options, builder->create_info);
2153
2154 /* compile shaders in reverse order */
2155 struct tu_shader *next_stage_shader = NULL;
2156 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
2157 stage > MESA_SHADER_NONE; stage--) {
2158 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
2159 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
2160 continue;
2161
2162 struct tu_shader *shader =
2163 tu_shader_create(builder->device, stage, stage_info, builder->layout,
2164 builder->alloc);
2165 if (!shader)
2166 return VK_ERROR_OUT_OF_HOST_MEMORY;
2167
2168 VkResult result =
2169 tu_shader_compile(builder->device, shader, next_stage_shader,
2170 &options, builder->alloc);
2171 if (result != VK_SUCCESS)
2172 return result;
2173
2174 builder->shaders[stage] = shader;
2175 builder->shader_offsets[stage] = builder->shader_total_size;
2176 builder->shader_total_size +=
2177 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
2178
2179 next_stage_shader = shader;
2180 }
2181
2182 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2183 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2184 const struct ir3_shader_variant *variant;
2185
2186 if (vs->ir3_shader.stream_output.num_outputs)
2187 variant = &vs->variants[0];
2188 else
2189 variant = &vs->variants[1];
2190
2191 builder->binning_vs_offset = builder->shader_total_size;
2192 builder->shader_total_size +=
2193 sizeof(uint32_t) * variant->info.sizedwords;
2194 }
2195
2196 return VK_SUCCESS;
2197 }
2198
2199 static VkResult
2200 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
2201 struct tu_pipeline *pipeline)
2202 {
2203 struct tu_bo *bo = &pipeline->program.binary_bo;
2204
2205 VkResult result =
2206 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
2207 if (result != VK_SUCCESS)
2208 return result;
2209
2210 result = tu_bo_map(builder->device, bo);
2211 if (result != VK_SUCCESS)
2212 return result;
2213
2214 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2215 const struct tu_shader *shader = builder->shaders[i];
2216 if (!shader)
2217 continue;
2218
2219 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
2220 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
2221 }
2222
2223 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2224 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2225 const struct ir3_shader_variant *variant;
2226 void *bin;
2227
2228 if (vs->ir3_shader.stream_output.num_outputs) {
2229 variant = &vs->variants[0];
2230 bin = vs->binary;
2231 } else {
2232 variant = &vs->variants[1];
2233 bin = vs->binning_binary;
2234 }
2235
2236 memcpy(bo->map + builder->binning_vs_offset, bin,
2237 sizeof(uint32_t) * variant->info.sizedwords);
2238 }
2239
2240 return VK_SUCCESS;
2241 }
2242
2243 static void
2244 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2245 struct tu_pipeline *pipeline)
2246 {
2247 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2248 builder->create_info->pDynamicState;
2249
2250 if (!dynamic_info)
2251 return;
2252
2253 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2254 pipeline->dynamic_state.mask |=
2255 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
2256 }
2257 }
2258
2259 static void
2260 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2261 struct tu_shader *shader,
2262 struct ir3_shader_variant *v)
2263 {
2264 link->ubo_state = v->shader->ubo_state;
2265 link->const_state = v->shader->const_state;
2266 link->constlen = v->constlen;
2267 link->push_consts = shader->push_consts;
2268 }
2269
2270 static void
2271 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2272 struct tu_pipeline *pipeline)
2273 {
2274 struct tu_cs prog_cs;
2275 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2276 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
2277 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2278
2279 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2280 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
2281 pipeline->program.binning_state_ib =
2282 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2283
2284 VkShaderStageFlags stages = 0;
2285 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2286 stages |= builder->create_info->pStages[i].stage;
2287 }
2288 pipeline->active_stages = stages;
2289
2290 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2291 if (!builder->shaders[i])
2292 continue;
2293
2294 tu_pipeline_set_linkage(&pipeline->program.link[i],
2295 builder->shaders[i],
2296 &builder->shaders[i]->variants[0]);
2297 }
2298
2299 if (builder->shaders[MESA_SHADER_FRAGMENT]) {
2300 memcpy(pipeline->program.input_attachment_idx,
2301 builder->shaders[MESA_SHADER_FRAGMENT]->attachment_idx,
2302 sizeof(pipeline->program.input_attachment_idx));
2303 }
2304 }
2305
2306 static void
2307 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2308 struct tu_pipeline *pipeline)
2309 {
2310 const VkPipelineVertexInputStateCreateInfo *vi_info =
2311 builder->create_info->pVertexInputState;
2312 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2313
2314 struct tu_cs vi_cs;
2315 tu_cs_begin_sub_stream(&pipeline->cs,
2316 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2317 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
2318 pipeline->vi.bindings, &pipeline->vi.count);
2319 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2320
2321 if (vs->has_binning_pass) {
2322 tu_cs_begin_sub_stream(&pipeline->cs,
2323 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2324 tu6_emit_vertex_input(
2325 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
2326 &pipeline->vi.binning_count);
2327 pipeline->vi.binning_state_ib =
2328 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2329 }
2330 }
2331
2332 static void
2333 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2334 struct tu_pipeline *pipeline)
2335 {
2336 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2337 builder->create_info->pInputAssemblyState;
2338
2339 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2340 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2341 }
2342
2343 static void
2344 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2345 struct tu_pipeline *pipeline)
2346 {
2347 /* The spec says:
2348 *
2349 * pViewportState is a pointer to an instance of the
2350 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2351 * pipeline has rasterization disabled."
2352 *
2353 * We leave the relevant registers stale in that case.
2354 */
2355 if (builder->rasterizer_discard)
2356 return;
2357
2358 const VkPipelineViewportStateCreateInfo *vp_info =
2359 builder->create_info->pViewportState;
2360
2361 struct tu_cs vp_cs;
2362 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
2363
2364 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2365 assert(vp_info->viewportCount == 1);
2366 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
2367 }
2368
2369 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2370 assert(vp_info->scissorCount == 1);
2371 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
2372 }
2373
2374 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
2375 }
2376
2377 static void
2378 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2379 struct tu_pipeline *pipeline)
2380 {
2381 const VkPipelineRasterizationStateCreateInfo *rast_info =
2382 builder->create_info->pRasterizationState;
2383
2384 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2385
2386 struct tu_cs rast_cs;
2387 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
2388
2389
2390 tu_cs_emit_regs(&rast_cs,
2391 A6XX_GRAS_CL_CNTL(
2392 .znear_clip_disable = rast_info->depthClampEnable,
2393 .zfar_clip_disable = rast_info->depthClampEnable,
2394 .unk5 = rast_info->depthClampEnable,
2395 .zero_gb_scale_z = 1,
2396 .vp_clip_code_ignore = 1));
2397 /* move to hw ctx init? */
2398 tu6_emit_gras_unknowns(&rast_cs);
2399 tu6_emit_point_size(&rast_cs);
2400
2401 const uint32_t gras_su_cntl =
2402 tu6_gras_su_cntl(rast_info, builder->samples);
2403
2404 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
2405 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
2406
2407 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
2408 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
2409 rast_info->depthBiasClamp,
2410 rast_info->depthBiasSlopeFactor);
2411 }
2412
2413 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
2414
2415 pipeline->rast.gras_su_cntl = gras_su_cntl;
2416 }
2417
2418 static void
2419 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2420 struct tu_pipeline *pipeline)
2421 {
2422 /* The spec says:
2423 *
2424 * pDepthStencilState is a pointer to an instance of the
2425 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2426 * the pipeline has rasterization disabled or if the subpass of the
2427 * render pass the pipeline is created against does not use a
2428 * depth/stencil attachment.
2429 *
2430 * Disable both depth and stencil tests if there is no ds attachment,
2431 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2432 * only the separate stencil attachment
2433 */
2434 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2435 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2436 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2437 ? builder->create_info->pDepthStencilState
2438 : &dummy_ds_info;
2439 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2440 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2441 ? ds_info : &dummy_ds_info;
2442
2443 struct tu_cs ds_cs;
2444 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2445
2446 /* move to hw ctx init? */
2447 tu6_emit_alpha_control_disable(&ds_cs);
2448
2449 tu6_emit_depth_control(&ds_cs, ds_info_depth,
2450 builder->create_info->pRasterizationState);
2451 tu6_emit_stencil_control(&ds_cs, ds_info);
2452
2453 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2454 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2455 ds_info->back.compareMask);
2456 }
2457 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2458 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2459 ds_info->back.writeMask);
2460 }
2461 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2462 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2463 ds_info->back.reference);
2464 }
2465
2466 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2467 }
2468
2469 static void
2470 tu_pipeline_builder_parse_multisample_and_color_blend(
2471 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2472 {
2473 /* The spec says:
2474 *
2475 * pMultisampleState is a pointer to an instance of the
2476 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2477 * has rasterization disabled.
2478 *
2479 * Also,
2480 *
2481 * pColorBlendState is a pointer to an instance of the
2482 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2483 * pipeline has rasterization disabled or if the subpass of the render
2484 * pass the pipeline is created against does not use any color
2485 * attachments.
2486 *
2487 * We leave the relevant registers stale when rasterization is disabled.
2488 */
2489 if (builder->rasterizer_discard)
2490 return;
2491
2492 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2493 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2494 builder->create_info->pMultisampleState;
2495 const VkPipelineColorBlendStateCreateInfo *blend_info =
2496 builder->use_color_attachments ? builder->create_info->pColorBlendState
2497 : &dummy_blend_info;
2498
2499 struct tu_cs blend_cs;
2500 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 18, &blend_cs);
2501
2502 uint32_t blend_enable_mask;
2503 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2504 builder->color_attachment_formats,
2505 &blend_enable_mask);
2506
2507 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2508 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2509
2510 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SAMPLE_LOCATIONS)) {
2511 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2512 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2513 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2514
2515 if (sample_locations && sample_locations->sampleLocationsEnable)
2516 samp_loc = &sample_locations->sampleLocationsInfo;
2517
2518 tu6_emit_sample_locations(&blend_cs, samp_loc);
2519 }
2520
2521 tu6_emit_blend_control(&blend_cs, blend_enable_mask,
2522 builder->use_dual_src_blend, msaa_info);
2523
2524 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2525 }
2526
2527 static void
2528 tu_pipeline_finish(struct tu_pipeline *pipeline,
2529 struct tu_device *dev,
2530 const VkAllocationCallbacks *alloc)
2531 {
2532 tu_cs_finish(&pipeline->cs);
2533
2534 if (pipeline->program.binary_bo.gem_handle)
2535 tu_bo_finish(dev, &pipeline->program.binary_bo);
2536 }
2537
2538 static VkResult
2539 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2540 struct tu_pipeline **pipeline)
2541 {
2542 VkResult result = tu_pipeline_create(builder->device, builder->layout,
2543 false, builder->alloc, pipeline);
2544 if (result != VK_SUCCESS)
2545 return result;
2546
2547 (*pipeline)->layout = builder->layout;
2548
2549 /* compile and upload shaders */
2550 result = tu_pipeline_builder_compile_shaders(builder);
2551 if (result == VK_SUCCESS)
2552 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2553 if (result != VK_SUCCESS) {
2554 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2555 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2556 *pipeline = VK_NULL_HANDLE;
2557
2558 return result;
2559 }
2560
2561 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2562 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2563 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2564 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2565 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2566 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2567 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2568 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2569 tu6_emit_load_state(*pipeline, false);
2570
2571 /* we should have reserved enough space upfront such that the CS never
2572 * grows
2573 */
2574 assert((*pipeline)->cs.bo_count == 1);
2575
2576 return VK_SUCCESS;
2577 }
2578
2579 static void
2580 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2581 {
2582 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2583 if (!builder->shaders[i])
2584 continue;
2585 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2586 }
2587 }
2588
2589 static void
2590 tu_pipeline_builder_init_graphics(
2591 struct tu_pipeline_builder *builder,
2592 struct tu_device *dev,
2593 struct tu_pipeline_cache *cache,
2594 const VkGraphicsPipelineCreateInfo *create_info,
2595 const VkAllocationCallbacks *alloc)
2596 {
2597 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2598
2599 *builder = (struct tu_pipeline_builder) {
2600 .device = dev,
2601 .cache = cache,
2602 .create_info = create_info,
2603 .alloc = alloc,
2604 .layout = layout,
2605 };
2606
2607 builder->rasterizer_discard =
2608 create_info->pRasterizationState->rasterizerDiscardEnable;
2609
2610 if (builder->rasterizer_discard) {
2611 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2612 } else {
2613 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2614
2615 const struct tu_render_pass *pass =
2616 tu_render_pass_from_handle(create_info->renderPass);
2617 const struct tu_subpass *subpass =
2618 &pass->subpasses[create_info->subpass];
2619
2620 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2621 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2622 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2623
2624 assert(subpass->color_count == 0 ||
2625 !create_info->pColorBlendState ||
2626 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2627 builder->color_attachment_count = subpass->color_count;
2628 for (uint32_t i = 0; i < subpass->color_count; i++) {
2629 const uint32_t a = subpass->color_attachments[i].attachment;
2630 if (a == VK_ATTACHMENT_UNUSED)
2631 continue;
2632
2633 builder->color_attachment_formats[i] = pass->attachments[a].format;
2634 builder->use_color_attachments = true;
2635 }
2636
2637 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2638 builder->color_attachment_count++;
2639 builder->use_dual_src_blend = true;
2640 }
2641 }
2642 }
2643
2644 static VkResult
2645 tu_graphics_pipeline_create(VkDevice device,
2646 VkPipelineCache pipelineCache,
2647 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2648 const VkAllocationCallbacks *pAllocator,
2649 VkPipeline *pPipeline)
2650 {
2651 TU_FROM_HANDLE(tu_device, dev, device);
2652 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2653
2654 struct tu_pipeline_builder builder;
2655 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2656 pCreateInfo, pAllocator);
2657
2658 struct tu_pipeline *pipeline = NULL;
2659 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2660 tu_pipeline_builder_finish(&builder);
2661
2662 if (result == VK_SUCCESS)
2663 *pPipeline = tu_pipeline_to_handle(pipeline);
2664 else
2665 *pPipeline = VK_NULL_HANDLE;
2666
2667 return result;
2668 }
2669
2670 VkResult
2671 tu_CreateGraphicsPipelines(VkDevice device,
2672 VkPipelineCache pipelineCache,
2673 uint32_t count,
2674 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2675 const VkAllocationCallbacks *pAllocator,
2676 VkPipeline *pPipelines)
2677 {
2678 VkResult final_result = VK_SUCCESS;
2679
2680 for (uint32_t i = 0; i < count; i++) {
2681 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2682 &pCreateInfos[i], pAllocator,
2683 &pPipelines[i]);
2684
2685 if (result != VK_SUCCESS)
2686 final_result = result;
2687 }
2688
2689 return final_result;
2690 }
2691
2692 static void
2693 tu6_emit_compute_program(struct tu_cs *cs,
2694 struct tu_shader *shader,
2695 const struct tu_bo *binary_bo)
2696 {
2697 const struct ir3_shader_variant *v = &shader->variants[0];
2698
2699 tu6_emit_cs_config(cs, shader, v);
2700
2701 /* The compute program is the only one in the pipeline, so 0 offset. */
2702 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2703
2704 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2705 }
2706
2707 static VkResult
2708 tu_compute_upload_shader(VkDevice device,
2709 struct tu_pipeline *pipeline,
2710 struct tu_shader *shader)
2711 {
2712 TU_FROM_HANDLE(tu_device, dev, device);
2713 struct tu_bo *bo = &pipeline->program.binary_bo;
2714 struct ir3_shader_variant *v = &shader->variants[0];
2715
2716 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2717 VkResult result =
2718 tu_bo_init_new(dev, bo, shader_size);
2719 if (result != VK_SUCCESS)
2720 return result;
2721
2722 result = tu_bo_map(dev, bo);
2723 if (result != VK_SUCCESS)
2724 return result;
2725
2726 memcpy(bo->map, shader->binary, shader_size);
2727
2728 return VK_SUCCESS;
2729 }
2730
2731
2732 static VkResult
2733 tu_compute_pipeline_create(VkDevice device,
2734 VkPipelineCache _cache,
2735 const VkComputePipelineCreateInfo *pCreateInfo,
2736 const VkAllocationCallbacks *pAllocator,
2737 VkPipeline *pPipeline)
2738 {
2739 TU_FROM_HANDLE(tu_device, dev, device);
2740 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2741 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2742 VkResult result;
2743
2744 struct tu_pipeline *pipeline;
2745
2746 *pPipeline = VK_NULL_HANDLE;
2747
2748 result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline);
2749 if (result != VK_SUCCESS)
2750 return result;
2751
2752 pipeline->layout = layout;
2753
2754 struct tu_shader_compile_options options;
2755 tu_shader_compile_options_init(&options, NULL);
2756
2757 struct tu_shader *shader =
2758 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2759 if (!shader) {
2760 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2761 goto fail;
2762 }
2763
2764 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2765 if (result != VK_SUCCESS)
2766 goto fail;
2767
2768 struct ir3_shader_variant *v = &shader->variants[0];
2769
2770 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2771 shader, v);
2772
2773 result = tu_compute_upload_shader(device, pipeline, shader);
2774 if (result != VK_SUCCESS)
2775 goto fail;
2776
2777 for (int i = 0; i < 3; i++)
2778 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2779
2780 struct tu_cs prog_cs;
2781 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2782 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2783 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2784
2785 tu6_emit_load_state(pipeline, true);
2786
2787 *pPipeline = tu_pipeline_to_handle(pipeline);
2788 return VK_SUCCESS;
2789
2790 fail:
2791 if (shader)
2792 tu_shader_destroy(dev, shader, pAllocator);
2793
2794 tu_pipeline_finish(pipeline, dev, pAllocator);
2795 vk_free2(&dev->alloc, pAllocator, pipeline);
2796
2797 return result;
2798 }
2799
2800 VkResult
2801 tu_CreateComputePipelines(VkDevice device,
2802 VkPipelineCache pipelineCache,
2803 uint32_t count,
2804 const VkComputePipelineCreateInfo *pCreateInfos,
2805 const VkAllocationCallbacks *pAllocator,
2806 VkPipeline *pPipelines)
2807 {
2808 VkResult final_result = VK_SUCCESS;
2809
2810 for (uint32_t i = 0; i < count; i++) {
2811 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2812 &pCreateInfos[i],
2813 pAllocator, &pPipelines[i]);
2814 if (result != VK_SUCCESS)
2815 final_result = result;
2816 }
2817
2818 return final_result;
2819 }
2820
2821 void
2822 tu_DestroyPipeline(VkDevice _device,
2823 VkPipeline _pipeline,
2824 const VkAllocationCallbacks *pAllocator)
2825 {
2826 TU_FROM_HANDLE(tu_device, dev, _device);
2827 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2828
2829 if (!_pipeline)
2830 return;
2831
2832 tu_pipeline_finish(pipeline, dev, pAllocator);
2833 vk_free2(&dev->alloc, pAllocator, pipeline);
2834 }