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tu: Don't invalidate irrelevant state when changing pipeline
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static void
46 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
47 enum a6xx_state_block sb, unsigned base, unsigned offset,
48 unsigned count)
49 {
50 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
51 * clear if emitting more packets will even help anything. Presumably the
52 * descriptor cache is relatively small, and these packets stop doing
53 * anything when there are too many descriptors.
54 */
55 tu_cs_emit_pkt7(cs, opcode, 3);
56 tu_cs_emit(cs,
57 CP_LOAD_STATE6_0_STATE_TYPE(st) |
58 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
59 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
60 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
61 tu_cs_emit_qw(cs, offset | (base << 28));
62 }
63
64 static unsigned
65 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
66 {
67 const unsigned load_state_size = 4;
68 unsigned size = 0;
69 for (unsigned i = 0; i < layout->num_sets; i++) {
70 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
71 for (unsigned j = 0; j < set_layout->binding_count; j++) {
72 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
73 unsigned count = 0;
74 /* Note: some users, like amber for example, pass in
75 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
76 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
77 */
78 VkShaderStageFlags stages = compute ?
79 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
80 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
81 unsigned stage_count = util_bitcount(stages);
82 switch (binding->type) {
83 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
84 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
85 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
86 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
87 /* IBO-backed resources only need one packet for all graphics stages */
88 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
89 count += 1;
90 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
91 count += 1;
92 break;
93 case VK_DESCRIPTOR_TYPE_SAMPLER:
94 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
95 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
96 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
97 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
98 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
99 /* Textures and UBO's needs a packet for each stage */
100 count = stage_count;
101 break;
102 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
103 /* Because of how we pack combined images and samplers, we
104 * currently can't use one packet for the whole array.
105 */
106 count = stage_count * binding->array_size * 2;
107 break;
108 default:
109 unreachable("bad descriptor type");
110 }
111 size += count * load_state_size;
112 }
113 }
114 return size;
115 }
116
117 static void
118 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
119 {
120 unsigned size = tu6_load_state_size(pipeline->layout, compute);
121 if (size == 0)
122 return;
123
124 struct tu_cs cs;
125 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
126
127 struct tu_pipeline_layout *layout = pipeline->layout;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 /* From 13.2.7. Descriptor Set Binding:
130 *
131 * A compatible descriptor set must be bound for all set numbers that
132 * any shaders in a pipeline access, at the time that a draw or
133 * dispatch command is recorded to execute using that pipeline.
134 * However, if none of the shaders in a pipeline statically use any
135 * bindings with a particular set number, then no descriptor set need
136 * be bound for that set number, even if the pipeline layout includes
137 * a non-trivial descriptor set layout for that set number.
138 *
139 * This means that descriptor sets unused by the pipeline may have a
140 * garbage or 0 BINDLESS_BASE register, which will cause context faults
141 * when prefetching descriptors from these sets. Skip prefetching for
142 * descriptors from them to avoid this. This is also an optimization,
143 * since these prefetches would be useless.
144 */
145 if (!(pipeline->active_desc_sets & (1u << i)))
146 continue;
147
148 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
149 for (unsigned j = 0; j < set_layout->binding_count; j++) {
150 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
151 unsigned base = i;
152 unsigned offset = binding->offset / 4;
153 /* Note: some users, like amber for example, pass in
154 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
155 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
156 */
157 VkShaderStageFlags stages = compute ?
158 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
159 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
160 unsigned count = binding->array_size;
161 if (count == 0 || stages == 0)
162 continue;
163 switch (binding->type) {
164 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
165 base = MAX_SETS;
166 offset = (layout->set[i].dynamic_offset_start +
167 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
168 /* fallthrough */
169 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
170 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
171 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
172 /* IBO-backed resources only need one packet for all graphics stages */
173 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
174 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
175 base, offset, count);
176 }
177 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
178 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
179 base, offset, count);
180 }
181 break;
182 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
183 /* nothing - input attachment doesn't use bindless */
184 break;
185 case VK_DESCRIPTOR_TYPE_SAMPLER:
186 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
187 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
188 tu_foreach_stage(stage, stages) {
189 emit_load_state(&cs, tu6_stage2opcode(stage),
190 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
191 ST6_SHADER : ST6_CONSTANTS,
192 tu6_stage2texsb(stage), base, offset, count);
193 }
194 break;
195 }
196 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
197 base = MAX_SETS;
198 offset = (layout->set[i].dynamic_offset_start +
199 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
200 /* fallthrough */
201 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
202 tu_foreach_stage(stage, stages) {
203 emit_load_state(&cs, tu6_stage2opcode(stage), ST6_UBO,
204 tu6_stage2shadersb(stage), base, offset, count);
205 }
206 break;
207 }
208 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
209 tu_foreach_stage(stage, stages) {
210 /* TODO: We could emit less CP_LOAD_STATE6 if we used
211 * struct-of-arrays instead of array-of-structs.
212 */
213 for (unsigned i = 0; i < count; i++) {
214 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
215 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
216 emit_load_state(&cs, tu6_stage2opcode(stage),
217 ST6_CONSTANTS, tu6_stage2texsb(stage),
218 base, tex_offset, 1);
219 emit_load_state(&cs, tu6_stage2opcode(stage),
220 ST6_SHADER, tu6_stage2texsb(stage),
221 base, sam_offset, 1);
222 }
223 }
224 break;
225 }
226 default:
227 unreachable("bad descriptor type");
228 }
229 }
230 }
231
232 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
233 }
234
235 struct tu_pipeline_builder
236 {
237 struct tu_device *device;
238 struct tu_pipeline_cache *cache;
239 struct tu_pipeline_layout *layout;
240 const VkAllocationCallbacks *alloc;
241 const VkGraphicsPipelineCreateInfo *create_info;
242
243 struct tu_shader *shaders[MESA_SHADER_STAGES];
244 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
245 struct ir3_shader_variant *binning_variant;
246 uint64_t shader_iova[MESA_SHADER_STAGES];
247 uint64_t binning_vs_iova;
248
249 bool rasterizer_discard;
250 /* these states are affectd by rasterizer_discard */
251 VkSampleCountFlagBits samples;
252 bool use_color_attachments;
253 bool use_dual_src_blend;
254 uint32_t color_attachment_count;
255 VkFormat color_attachment_formats[MAX_RTS];
256 VkFormat depth_attachment_format;
257 uint32_t render_components;
258 };
259
260 static bool
261 tu_logic_op_reads_dst(VkLogicOp op)
262 {
263 switch (op) {
264 case VK_LOGIC_OP_CLEAR:
265 case VK_LOGIC_OP_COPY:
266 case VK_LOGIC_OP_COPY_INVERTED:
267 case VK_LOGIC_OP_SET:
268 return false;
269 default:
270 return true;
271 }
272 }
273
274 static VkBlendFactor
275 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
276 {
277 /* treat dst alpha as 1.0 and avoid reading it */
278 switch (factor) {
279 case VK_BLEND_FACTOR_DST_ALPHA:
280 return VK_BLEND_FACTOR_ONE;
281 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
282 return VK_BLEND_FACTOR_ZERO;
283 default:
284 return factor;
285 }
286 }
287
288 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
289 {
290 switch (factor) {
291 case VK_BLEND_FACTOR_SRC1_COLOR:
292 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
293 case VK_BLEND_FACTOR_SRC1_ALPHA:
294 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
295 return true;
296 default:
297 return false;
298 }
299 }
300
301 static bool
302 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
303 {
304 if (!info)
305 return false;
306
307 for (unsigned i = 0; i < info->attachmentCount; i++) {
308 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
309 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
310 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
311 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
312 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
313 return true;
314 }
315
316 return false;
317 }
318
319 void
320 tu6_emit_xs_config(struct tu_cs *cs,
321 gl_shader_stage stage, /* xs->type, but xs may be NULL */
322 const struct ir3_shader_variant *xs,
323 uint64_t binary_iova)
324 {
325 static const struct xs_config {
326 uint16_t reg_sp_xs_ctrl;
327 uint16_t reg_sp_xs_config;
328 uint16_t reg_hlsq_xs_ctrl;
329 uint16_t reg_sp_vs_obj_start;
330 } xs_config[] = {
331 [MESA_SHADER_VERTEX] = {
332 REG_A6XX_SP_VS_CTRL_REG0,
333 REG_A6XX_SP_VS_CONFIG,
334 REG_A6XX_HLSQ_VS_CNTL,
335 REG_A6XX_SP_VS_OBJ_START_LO,
336 },
337 [MESA_SHADER_TESS_CTRL] = {
338 REG_A6XX_SP_HS_CTRL_REG0,
339 REG_A6XX_SP_HS_CONFIG,
340 REG_A6XX_HLSQ_HS_CNTL,
341 REG_A6XX_SP_HS_OBJ_START_LO,
342 },
343 [MESA_SHADER_TESS_EVAL] = {
344 REG_A6XX_SP_DS_CTRL_REG0,
345 REG_A6XX_SP_DS_CONFIG,
346 REG_A6XX_HLSQ_DS_CNTL,
347 REG_A6XX_SP_DS_OBJ_START_LO,
348 },
349 [MESA_SHADER_GEOMETRY] = {
350 REG_A6XX_SP_GS_CTRL_REG0,
351 REG_A6XX_SP_GS_CONFIG,
352 REG_A6XX_HLSQ_GS_CNTL,
353 REG_A6XX_SP_GS_OBJ_START_LO,
354 },
355 [MESA_SHADER_FRAGMENT] = {
356 REG_A6XX_SP_FS_CTRL_REG0,
357 REG_A6XX_SP_FS_CONFIG,
358 REG_A6XX_HLSQ_FS_CNTL,
359 REG_A6XX_SP_FS_OBJ_START_LO,
360 },
361 [MESA_SHADER_COMPUTE] = {
362 REG_A6XX_SP_CS_CTRL_REG0,
363 REG_A6XX_SP_CS_CONFIG,
364 REG_A6XX_HLSQ_CS_CNTL,
365 REG_A6XX_SP_CS_OBJ_START_LO,
366 },
367 };
368 const struct xs_config *cfg = &xs_config[stage];
369
370 if (!xs) {
371 /* shader stage disabled */
372 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
373 tu_cs_emit(cs, 0);
374
375 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
376 tu_cs_emit(cs, 0);
377 return;
378 }
379
380 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
381 enum a3xx_threadsize threadsize = FOUR_QUADS;
382
383 /* TODO:
384 * the "threadsize" field may have nothing to do with threadsize,
385 * use a value that matches the blob until it is figured out
386 */
387 if (xs->type == MESA_SHADER_GEOMETRY)
388 threadsize = TWO_QUADS;
389
390 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
391 tu_cs_emit(cs,
392 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
393 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
394 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs->info.max_half_reg + 1) |
395 COND(xs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
396 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
397 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
398 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
399 /* only fragment shader sets VARYING bit */
400 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
401 /* unknown bit, seems unnecessary */
402 COND(is_fs, 0x1000000));
403
404 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
405 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
406 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
407 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
408 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
409 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
410 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
411 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
412 tu_cs_emit(cs, xs->instrlen);
413
414 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
415 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) |
416 A6XX_HLSQ_VS_CNTL_ENABLED);
417
418 /* emit program binary
419 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
420 */
421
422 assert((binary_iova & 0x7f) == 0);
423
424 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
425 tu_cs_emit_qw(cs, binary_iova);
426
427 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
428 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
429 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
430 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
431 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
432 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
433 tu_cs_emit_qw(cs, binary_iova);
434
435 /* emit immediates */
436
437 const struct ir3_const_state *const_state = ir3_const_state(xs);
438 uint32_t base = const_state->offsets.immediate;
439 int size = const_state->immediates_count;
440
441 /* truncate size to avoid writing constants that shader
442 * does not use:
443 */
444 size = MIN2(size + base, xs->constlen) - base;
445
446 if (size <= 0)
447 return;
448
449 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + size * 4);
450 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
451 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
452 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
453 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
454 CP_LOAD_STATE6_0_NUM_UNIT(size));
455 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
456 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
457
458 for (unsigned i = 0; i < size; i++) {
459 tu_cs_emit(cs, const_state->immediates[i].val[0]);
460 tu_cs_emit(cs, const_state->immediates[i].val[1]);
461 tu_cs_emit(cs, const_state->immediates[i].val[2]);
462 tu_cs_emit(cs, const_state->immediates[i].val[3]);
463 }
464 }
465
466 static void
467 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
468 const struct ir3_shader_variant *v,
469 uint32_t binary_iova)
470 {
471 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
472 .cs_state = true,
473 .cs_ibo = true));
474
475 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
476
477 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
478 tu_cs_emit(cs, 0x41);
479
480 uint32_t local_invocation_id =
481 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
482 uint32_t work_group_id =
483 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
484
485 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
486 tu_cs_emit(cs,
487 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
488 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
489 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
490 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
491 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
492 }
493
494 static void
495 tu6_emit_vs_system_values(struct tu_cs *cs,
496 const struct ir3_shader_variant *vs,
497 const struct ir3_shader_variant *hs,
498 const struct ir3_shader_variant *ds,
499 const struct ir3_shader_variant *gs,
500 bool primid_passthru)
501 {
502 const uint32_t vertexid_regid =
503 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
504 const uint32_t instanceid_regid =
505 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
506 const uint32_t tess_coord_x_regid = hs ?
507 ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD) :
508 regid(63, 0);
509 const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ?
510 tess_coord_x_regid + 1 :
511 regid(63, 0);
512 const uint32_t hs_patch_regid = hs ?
513 ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
514 regid(63, 0);
515 const uint32_t ds_patch_regid = hs ?
516 ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
517 regid(63, 0);
518 const uint32_t hs_invocation_regid = hs ?
519 ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) :
520 regid(63, 0);
521 const uint32_t primitiveid_regid = gs ?
522 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
523 regid(63, 0);
524 const uint32_t gsheader_regid = gs ?
525 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
526 regid(63, 0);
527
528 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
529 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
530 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
531 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
532 0xfc000000);
533 tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
534 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
535 tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
536 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
537 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
538 0xfc);
539 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
540 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
541 0xfc00); /* VFD_CONTROL_5 */
542 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
543 }
544
545 /* Add any missing varyings needed for stream-out. Otherwise varyings not
546 * used by fragment shader will be stripped out.
547 */
548 static void
549 tu6_link_streamout(struct ir3_shader_linkage *l,
550 const struct ir3_shader_variant *v)
551 {
552 const struct ir3_stream_output_info *info = &v->shader->stream_output;
553
554 /*
555 * First, any stream-out varyings not already in linkage map (ie. also
556 * consumed by frag shader) need to be added:
557 */
558 for (unsigned i = 0; i < info->num_outputs; i++) {
559 const struct ir3_stream_output *out = &info->output[i];
560 unsigned compmask =
561 (1 << (out->num_components + out->start_component)) - 1;
562 unsigned k = out->register_index;
563 unsigned idx, nextloc = 0;
564
565 /* psize/pos need to be the last entries in linkage map, and will
566 * get added link_stream_out, so skip over them:
567 */
568 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
569 v->outputs[k].slot == VARYING_SLOT_POS)
570 continue;
571
572 for (idx = 0; idx < l->cnt; idx++) {
573 if (l->var[idx].regid == v->outputs[k].regid)
574 break;
575 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
576 }
577
578 /* add if not already in linkage map: */
579 if (idx == l->cnt)
580 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
581
582 /* expand component-mask if needed, ie streaming out all components
583 * but frag shader doesn't consume all components:
584 */
585 if (compmask & ~l->var[idx].compmask) {
586 l->var[idx].compmask |= compmask;
587 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
588 util_last_bit(l->var[idx].compmask));
589 }
590 }
591 }
592
593 static void
594 tu6_setup_streamout(struct tu_cs *cs,
595 const struct ir3_shader_variant *v,
596 struct ir3_shader_linkage *l)
597 {
598 const struct ir3_stream_output_info *info = &v->shader->stream_output;
599 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2] = {};
600 uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {};
601 uint32_t prog_count = align(l->max_loc, 2) / 2;
602
603 /* TODO: streamout state should be in a non-GMEM draw state */
604
605 /* no streamout: */
606 if (info->num_outputs == 0) {
607 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
608 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
609 tu_cs_emit(cs, 0);
610 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
611 tu_cs_emit(cs, 0);
612 return;
613 }
614
615 /* is there something to do with info->stride[i]? */
616
617 for (unsigned i = 0; i < info->num_outputs; i++) {
618 const struct ir3_stream_output *out = &info->output[i];
619 unsigned k = out->register_index;
620 unsigned idx;
621
622 /* Skip it, if there's an unused reg in the middle of outputs. */
623 if (v->outputs[k].regid == INVALID_REG)
624 continue;
625
626 ncomp[out->output_buffer] += out->num_components;
627
628 /* linkage map sorted by order frag shader wants things, so
629 * a bit less ideal here..
630 */
631 for (idx = 0; idx < l->cnt; idx++)
632 if (l->var[idx].regid == v->outputs[k].regid)
633 break;
634
635 debug_assert(idx < l->cnt);
636
637 for (unsigned j = 0; j < out->num_components; j++) {
638 unsigned c = j + out->start_component;
639 unsigned loc = l->var[idx].loc + c;
640 unsigned off = j + out->dst_offset; /* in dwords */
641
642 if (loc & 1) {
643 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
644 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
645 A6XX_VPC_SO_PROG_B_OFF(off * 4);
646 } else {
647 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
648 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
649 A6XX_VPC_SO_PROG_A_OFF(off * 4);
650 }
651 }
652 }
653
654 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count);
655 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
656 tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE |
657 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
658 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
659 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
660 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
661 for (uint32_t i = 0; i < 4; i++) {
662 tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
663 tu_cs_emit(cs, ncomp[i]);
664 }
665 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
666 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
667 tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
668 for (uint32_t i = 0; i < prog_count; i++) {
669 tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
670 tu_cs_emit(cs, prog[i]);
671 }
672 }
673
674 static void
675 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
676 enum a6xx_state_block block, uint32_t offset,
677 uint32_t size, uint32_t *dwords) {
678 assert(size % 4 == 0);
679
680 tu_cs_emit_pkt7(cs, opcode, 3 + size);
681 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
682 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
683 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
684 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
685 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
686
687 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
688 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
689 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
690
691 tu_cs_emit_array(cs, dwords, size);
692 }
693
694 static void
695 tu6_emit_link_map(struct tu_cs *cs,
696 const struct ir3_shader_variant *producer,
697 const struct ir3_shader_variant *consumer,
698 enum a6xx_state_block sb)
699 {
700 const struct ir3_const_state *const_state = ir3_const_state(consumer);
701 uint32_t base = const_state->offsets.primitive_map;
702 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
703 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
704 int size = DIV_ROUND_UP(num_loc, 4);
705
706 size = (MIN2(size + base, consumer->constlen) - base) * 4;
707 if (size <= 0)
708 return;
709
710 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, sb, 0, size,
711 patch_locs);
712 }
713
714 static uint16_t
715 gl_primitive_to_tess(uint16_t primitive) {
716 switch (primitive) {
717 case GL_POINTS:
718 return TESS_POINTS;
719 case GL_LINE_STRIP:
720 return TESS_LINES;
721 case GL_TRIANGLE_STRIP:
722 return TESS_CW_TRIS;
723 default:
724 unreachable("");
725 }
726 }
727
728 void
729 tu6_emit_vpc(struct tu_cs *cs,
730 const struct ir3_shader_variant *vs,
731 const struct ir3_shader_variant *hs,
732 const struct ir3_shader_variant *ds,
733 const struct ir3_shader_variant *gs,
734 const struct ir3_shader_variant *fs)
735 {
736 /* note: doesn't compile as static because of the array regs.. */
737 const struct reg_config {
738 uint16_t reg_sp_xs_out_reg;
739 uint16_t reg_sp_xs_vpc_dst_reg;
740 uint16_t reg_vpc_xs_pack;
741 uint16_t reg_vpc_xs_clip_cntl;
742 uint16_t reg_gras_xs_cl_cntl;
743 uint16_t reg_pc_xs_out_cntl;
744 uint16_t reg_sp_xs_primitive_cntl;
745 uint16_t reg_vpc_xs_layer_cntl;
746 uint16_t reg_gras_xs_layer_cntl;
747 } reg_config[] = {
748 [MESA_SHADER_VERTEX] = {
749 REG_A6XX_SP_VS_OUT_REG(0),
750 REG_A6XX_SP_VS_VPC_DST_REG(0),
751 REG_A6XX_VPC_VS_PACK,
752 REG_A6XX_VPC_VS_CLIP_CNTL,
753 REG_A6XX_GRAS_VS_CL_CNTL,
754 REG_A6XX_PC_VS_OUT_CNTL,
755 REG_A6XX_SP_VS_PRIMITIVE_CNTL,
756 REG_A6XX_VPC_VS_LAYER_CNTL,
757 REG_A6XX_GRAS_VS_LAYER_CNTL
758 },
759 [MESA_SHADER_TESS_EVAL] = {
760 REG_A6XX_SP_DS_OUT_REG(0),
761 REG_A6XX_SP_DS_VPC_DST_REG(0),
762 REG_A6XX_VPC_DS_PACK,
763 REG_A6XX_VPC_DS_CLIP_CNTL,
764 REG_A6XX_GRAS_DS_CL_CNTL,
765 REG_A6XX_PC_DS_OUT_CNTL,
766 REG_A6XX_SP_DS_PRIMITIVE_CNTL,
767 REG_A6XX_VPC_DS_LAYER_CNTL,
768 REG_A6XX_GRAS_DS_LAYER_CNTL
769 },
770 [MESA_SHADER_GEOMETRY] = {
771 REG_A6XX_SP_GS_OUT_REG(0),
772 REG_A6XX_SP_GS_VPC_DST_REG(0),
773 REG_A6XX_VPC_GS_PACK,
774 REG_A6XX_VPC_GS_CLIP_CNTL,
775 REG_A6XX_GRAS_GS_CL_CNTL,
776 REG_A6XX_PC_GS_OUT_CNTL,
777 REG_A6XX_SP_GS_PRIMITIVE_CNTL,
778 REG_A6XX_VPC_GS_LAYER_CNTL,
779 REG_A6XX_GRAS_GS_LAYER_CNTL
780 },
781 };
782
783 const struct ir3_shader_variant *last_shader;
784 if (gs) {
785 last_shader = gs;
786 } else if (hs) {
787 last_shader = ds;
788 } else {
789 last_shader = vs;
790 }
791
792 const struct reg_config *cfg = &reg_config[last_shader->type];
793
794 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
795 if (fs)
796 ir3_link_shaders(&linkage, last_shader, fs, true);
797
798 if (last_shader->shader->stream_output.num_outputs)
799 tu6_link_streamout(&linkage, last_shader);
800
801 /* We do this after linking shaders in order to know whether PrimID
802 * passthrough needs to be enabled.
803 */
804 bool primid_passthru = linkage.primid_loc != 0xff;
805 tu6_emit_vs_system_values(cs, vs, hs, ds, gs, primid_passthru);
806
807 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
808 tu_cs_emit(cs, ~linkage.varmask[0]);
809 tu_cs_emit(cs, ~linkage.varmask[1]);
810 tu_cs_emit(cs, ~linkage.varmask[2]);
811 tu_cs_emit(cs, ~linkage.varmask[3]);
812
813 /* a6xx finds position/pointsize at the end */
814 const uint32_t position_regid =
815 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
816 const uint32_t pointsize_regid =
817 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
818 const uint32_t layer_regid =
819 ir3_find_output_regid(last_shader, VARYING_SLOT_LAYER);
820 uint32_t primitive_regid = gs ?
821 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) : regid(63, 0);
822 uint32_t flags_regid = gs ?
823 ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3) : 0;
824
825 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
826 if (layer_regid != regid(63, 0)) {
827 layer_loc = linkage.max_loc;
828 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
829 }
830 if (position_regid != regid(63, 0)) {
831 position_loc = linkage.max_loc;
832 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
833 }
834 if (pointsize_regid != regid(63, 0)) {
835 pointsize_loc = linkage.max_loc;
836 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
837 }
838
839 tu6_setup_streamout(cs, last_shader, &linkage);
840
841 /* map outputs of the last shader to VPC */
842 assert(linkage.cnt <= 32);
843 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
844 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
845 uint32_t sp_out[16];
846 uint32_t sp_vpc_dst[8];
847 for (uint32_t i = 0; i < linkage.cnt; i++) {
848 ((uint16_t *) sp_out)[i] =
849 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
850 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
851 ((uint8_t *) sp_vpc_dst)[i] =
852 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
853 }
854
855 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_out_reg, sp_out_count);
856 tu_cs_emit_array(cs, sp_out, sp_out_count);
857
858 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_vpc_dst_reg, sp_vpc_dst_count);
859 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
860
861 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_pack, 1);
862 tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
863 A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) |
864 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc));
865
866 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_clip_cntl, 1);
867 tu_cs_emit(cs, 0xffff00);
868
869 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_cl_cntl, 1);
870 tu_cs_emit(cs, 0);
871
872 tu_cs_emit_pkt4(cs, cfg->reg_pc_xs_out_cntl, 1);
873 tu_cs_emit(cs, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
874 CONDREG(pointsize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
875 CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
876 CONDREG(primitive_regid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID));
877
878 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_primitive_cntl, 1);
879 tu_cs_emit(cs, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt) |
880 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
881
882 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_layer_cntl, 1);
883 tu_cs_emit(cs, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
884
885 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_layer_cntl, 1);
886 tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
887
888 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
889 tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
890
891 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
892 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
893 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
894 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
895 A6XX_VPC_CNTL_0_UNKLOC(0xff));
896
897 if (hs) {
898 shader_info *hs_info = &hs->shader->nir->info;
899 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
900 tu_cs_emit(cs, hs_info->tess.tcs_vertices_out);
901
902 /* Total attribute slots in HS incoming patch. */
903 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9801, 1);
904 tu_cs_emit(cs,
905 hs_info->tess.tcs_vertices_out * vs->output_size / 4);
906
907 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
908 tu_cs_emit(cs, vs->output_size);
909 /* In SPIR-V generated from GLSL, the tessellation primitive params are
910 * are specified in the tess eval shader, but in SPIR-V generated from
911 * HLSL, they are specified in the tess control shader. */
912 shader_info *tess_info =
913 ds->shader->nir->info.tess.spacing == TESS_SPACING_UNSPECIFIED ?
914 &hs->shader->nir->info : &ds->shader->nir->info;
915 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_CNTL, 1);
916 uint32_t output;
917 if (tess_info->tess.point_mode)
918 output = TESS_POINTS;
919 else if (tess_info->tess.primitive_mode == GL_ISOLINES)
920 output = TESS_LINES;
921 else if (tess_info->tess.ccw)
922 output = TESS_CCW_TRIS;
923 else
924 output = TESS_CW_TRIS;
925
926 enum a6xx_tess_spacing spacing;
927 switch (tess_info->tess.spacing) {
928 case TESS_SPACING_EQUAL:
929 spacing = TESS_EQUAL;
930 break;
931 case TESS_SPACING_FRACTIONAL_ODD:
932 spacing = TESS_FRACTIONAL_ODD;
933 break;
934 case TESS_SPACING_FRACTIONAL_EVEN:
935 spacing = TESS_FRACTIONAL_EVEN;
936 break;
937 case TESS_SPACING_UNSPECIFIED:
938 default:
939 unreachable("invalid tess spacing");
940 }
941 tu_cs_emit(cs, A6XX_PC_TESS_CNTL_SPACING(spacing) |
942 A6XX_PC_TESS_CNTL_OUTPUT(output));
943
944 tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
945 tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER);
946 }
947
948
949 if (gs) {
950 uint32_t vertices_out, invocations, output, vec4_size;
951 /* this detects the tu_clear_blit path, which doesn't set ->nir */
952 if (gs->shader->nir) {
953 if (hs) {
954 tu6_emit_link_map(cs, ds, gs, SB6_GS_SHADER);
955 } else {
956 tu6_emit_link_map(cs, vs, gs, SB6_GS_SHADER);
957 }
958 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
959 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
960 invocations = gs->shader->nir->info.gs.invocations - 1;
961 /* Size of per-primitive alloction in ldlw memory in vec4s. */
962 vec4_size = gs->shader->nir->info.gs.vertices_in *
963 DIV_ROUND_UP(vs->output_size, 4);
964 } else {
965 vertices_out = 3;
966 output = TESS_CW_TRIS;
967 invocations = 0;
968 vec4_size = 0;
969 }
970
971 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
972 tu_cs_emit(cs,
973 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
974 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
975 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
976
977 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
978 tu_cs_emit(cs, 0);
979
980 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
981 tu_cs_emit(cs, 0xff);
982
983 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
984 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
985
986 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
987 tu_cs_emit(cs, 0);
988
989 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
990 tu_cs_emit(cs, vs->output_size);
991 }
992 }
993
994 static int
995 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
996 uint32_t index,
997 uint8_t *interp_mode,
998 uint8_t *ps_repl_mode)
999 {
1000 enum
1001 {
1002 INTERP_SMOOTH = 0,
1003 INTERP_FLAT = 1,
1004 INTERP_ZERO = 2,
1005 INTERP_ONE = 3,
1006 };
1007 enum
1008 {
1009 PS_REPL_NONE = 0,
1010 PS_REPL_S = 1,
1011 PS_REPL_T = 2,
1012 PS_REPL_ONE_MINUS_T = 3,
1013 };
1014
1015 const uint32_t compmask = fs->inputs[index].compmask;
1016
1017 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1018 * fourth component occupy three consecutive varying slots
1019 */
1020 int shift = 0;
1021 *interp_mode = 0;
1022 *ps_repl_mode = 0;
1023 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1024 if (compmask & 0x1) {
1025 *ps_repl_mode |= PS_REPL_S << shift;
1026 shift += 2;
1027 }
1028 if (compmask & 0x2) {
1029 *ps_repl_mode |= PS_REPL_T << shift;
1030 shift += 2;
1031 }
1032 if (compmask & 0x4) {
1033 *interp_mode |= INTERP_ZERO << shift;
1034 shift += 2;
1035 }
1036 if (compmask & 0x8) {
1037 *interp_mode |= INTERP_ONE << 6;
1038 shift += 2;
1039 }
1040 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1041 fs->inputs[index].rasterflat) {
1042 for (int i = 0; i < 4; i++) {
1043 if (compmask & (1 << i)) {
1044 *interp_mode |= INTERP_FLAT << shift;
1045 shift += 2;
1046 }
1047 }
1048 }
1049
1050 return shift;
1051 }
1052
1053 static void
1054 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1055 const struct ir3_shader_variant *fs)
1056 {
1057 uint32_t interp_modes[8] = { 0 };
1058 uint32_t ps_repl_modes[8] = { 0 };
1059
1060 if (fs) {
1061 for (int i = -1;
1062 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1063
1064 /* get the mode for input i */
1065 uint8_t interp_mode;
1066 uint8_t ps_repl_mode;
1067 const int bits =
1068 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1069
1070 /* OR the mode into the array */
1071 const uint32_t inloc = fs->inputs[i].inloc * 2;
1072 uint32_t n = inloc / 32;
1073 uint32_t shift = inloc % 32;
1074 interp_modes[n] |= interp_mode << shift;
1075 ps_repl_modes[n] |= ps_repl_mode << shift;
1076 if (shift + bits > 32) {
1077 n++;
1078 shift = 32 - shift;
1079
1080 interp_modes[n] |= interp_mode >> shift;
1081 ps_repl_modes[n] |= ps_repl_mode >> shift;
1082 }
1083 }
1084 }
1085
1086 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1087 tu_cs_emit_array(cs, interp_modes, 8);
1088
1089 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1090 tu_cs_emit_array(cs, ps_repl_modes, 8);
1091 }
1092
1093 void
1094 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1095 {
1096 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1097 uint32_t ij_regid[IJ_COUNT];
1098 uint32_t smask_in_regid;
1099
1100 bool sample_shading = fs->per_samp | fs->key.sample_shading;
1101 bool enable_varyings = fs->total_in > 0;
1102
1103 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1104 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1105 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1106 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1107 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1108 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
1109 ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
1110
1111 if (VALIDREG(ij_regid[IJ_LINEAR_SAMPLE]))
1112 tu_finishme("linear sample varying");
1113
1114 if (VALIDREG(ij_regid[IJ_LINEAR_CENTROID]))
1115 tu_finishme("linear centroid varying");
1116
1117 if (fs->num_sampler_prefetch > 0) {
1118 assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
1119 /* also, it seems like ij_pix is *required* to be r0.x */
1120 assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
1121 }
1122
1123 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1124 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1125 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1126 0x7000); // XXX);
1127 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1128 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1129 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1130 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1131 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1132 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1133 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1134 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1135 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1136 }
1137
1138 if (fs->num_sampler_prefetch > 0) {
1139 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1140 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1141 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1142 tu_cs_emit(cs,
1143 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1144 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1145 }
1146 }
1147
1148 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1149 tu_cs_emit(cs, 0x7);
1150 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1151 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1152 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1153 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
1154 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
1155 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
1156 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
1157 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
1158 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1159 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1160 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
1161 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
1162 tu_cs_emit(cs, 0xfc);
1163
1164 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1165 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1166
1167 bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
1168 bool need_size_persamp = false;
1169 if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
1170 if (sample_shading)
1171 need_size_persamp = true;
1172 else
1173 need_size = true;
1174 }
1175 if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
1176 need_size = true;
1177
1178 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1179 tu_cs_emit(cs,
1180 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
1181 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
1182 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
1183 COND(need_size, A6XX_GRAS_CNTL_SIZE) |
1184 COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1185 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
1186
1187 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1188 tu_cs_emit(cs,
1189 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
1190 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
1191 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
1192 COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
1193 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1194 COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1195 COND(fs->fragcoord_compmask != 0,
1196 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
1197 tu_cs_emit(cs,
1198 /* these two bits (UNK4/UNK5) relate to fragcoord
1199 * without them, fragcoord is the same for all samples
1200 */
1201 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) |
1202 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) |
1203 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1204 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1205 CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
1206 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1207
1208 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1209 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1210
1211 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1212 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1213
1214 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1215 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1216 }
1217
1218 static void
1219 tu6_emit_fs_outputs(struct tu_cs *cs,
1220 const struct ir3_shader_variant *fs,
1221 uint32_t mrt_count, bool dual_src_blend,
1222 uint32_t render_components,
1223 bool is_s8_uint)
1224 {
1225 uint32_t smask_regid, posz_regid;
1226
1227 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1228 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1229
1230 uint32_t fragdata_regid[8];
1231 if (fs->color0_mrt) {
1232 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1233 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1234 fragdata_regid[i] = fragdata_regid[0];
1235 } else {
1236 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1237 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1238 }
1239
1240 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1241 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1242 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1243 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
1244 0xfc000000);
1245 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1246
1247 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1248 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1249 // TODO we could have a mix of half and full precision outputs,
1250 // we really need to figure out half-precision from IR3_REG_HALF
1251 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1252 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1253 }
1254
1255 tu_cs_emit_regs(cs,
1256 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1257
1258 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1259 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1260 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1261 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1262 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1263
1264 tu_cs_emit_regs(cs,
1265 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1266
1267 enum a6xx_ztest_mode zmode;
1268
1269 if (fs->no_earlyz || fs->has_kill || fs->writes_pos || is_s8_uint) {
1270 zmode = A6XX_LATE_Z;
1271 } else {
1272 zmode = A6XX_EARLY_Z;
1273 }
1274
1275 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1276 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1277
1278 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1279 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1280 }
1281
1282 static void
1283 tu6_emit_geom_tess_consts(struct tu_cs *cs,
1284 const struct ir3_shader_variant *vs,
1285 const struct ir3_shader_variant *hs,
1286 const struct ir3_shader_variant *ds,
1287 const struct ir3_shader_variant *gs,
1288 uint32_t cps_per_patch)
1289 {
1290 uint32_t num_vertices =
1291 hs ? cps_per_patch : gs->shader->nir->info.gs.vertices_in;
1292
1293 uint32_t vs_params[4] = {
1294 vs->output_size * num_vertices * 4, /* vs primitive stride */
1295 vs->output_size * 4, /* vs vertex stride */
1296 0,
1297 0,
1298 };
1299 uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param;
1300 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1301 ARRAY_SIZE(vs_params), vs_params);
1302
1303 if (hs) {
1304 assert(ds->type != MESA_SHADER_NONE);
1305 uint32_t hs_params[4] = {
1306 vs->output_size * num_vertices * 4, /* hs primitive stride */
1307 vs->output_size * 4, /* hs vertex stride */
1308 hs->output_size,
1309 cps_per_patch,
1310 };
1311
1312 uint32_t hs_base = hs->const_state->offsets.primitive_param;
1313 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, hs_base, SB6_HS_SHADER, 0,
1314 ARRAY_SIZE(hs_params), hs_params);
1315 if (gs)
1316 num_vertices = gs->shader->nir->info.gs.vertices_in;
1317
1318 uint32_t ds_params[4] = {
1319 ds->output_size * num_vertices * 4, /* ds primitive stride */
1320 ds->output_size * 4, /* ds vertex stride */
1321 hs->output_size, /* hs vertex stride (dwords) */
1322 hs->shader->nir->info.tess.tcs_vertices_out
1323 };
1324
1325 uint32_t ds_base = ds->const_state->offsets.primitive_param;
1326 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, ds_base, SB6_DS_SHADER, 0,
1327 ARRAY_SIZE(ds_params), ds_params);
1328 }
1329
1330 if (gs) {
1331 const struct ir3_shader_variant *prev = ds ? ds : vs;
1332 uint32_t gs_params[4] = {
1333 prev->output_size * num_vertices * 4, /* gs primitive stride */
1334 prev->output_size * 4, /* gs vertex stride */
1335 0,
1336 0,
1337 };
1338 uint32_t gs_base = gs->const_state->offsets.primitive_param;
1339 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1340 ARRAY_SIZE(gs_params), gs_params);
1341 }
1342 }
1343
1344 static void
1345 tu6_emit_program(struct tu_cs *cs,
1346 struct tu_pipeline_builder *builder,
1347 bool binning_pass)
1348 {
1349 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
1350 const struct ir3_shader_variant *bs = builder->binning_variant;
1351 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
1352 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
1353 const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
1354 const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
1355 gl_shader_stage stage = MESA_SHADER_VERTEX;
1356
1357 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1358
1359 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
1360 .vs_state = true,
1361 .hs_state = true,
1362 .ds_state = true,
1363 .gs_state = true,
1364 .fs_state = true,
1365 .gfx_ibo = true));
1366
1367 /* Don't use the binning pass variant when GS is present because we don't
1368 * support compiling correct binning pass variants with GS.
1369 */
1370 if (binning_pass && !gs) {
1371 vs = bs;
1372 tu6_emit_xs_config(cs, stage, bs, builder->binning_vs_iova);
1373 stage++;
1374 }
1375
1376 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1377 const struct ir3_shader_variant *xs = builder->variants[stage];
1378
1379 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1380 fs = xs = NULL;
1381
1382 tu6_emit_xs_config(cs, stage, xs, builder->shader_iova[stage]);
1383 }
1384
1385 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1386 tu_cs_emit(cs, 0);
1387
1388 tu6_emit_vpc(cs, vs, hs, ds, gs, fs);
1389 tu6_emit_vpc_varying_modes(cs, fs);
1390
1391 if (fs) {
1392 tu6_emit_fs_inputs(cs, fs);
1393 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1394 builder->use_dual_src_blend,
1395 builder->render_components,
1396 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1397 } else {
1398 /* TODO: check if these can be skipped if fs is disabled */
1399 struct ir3_shader_variant dummy_variant = {};
1400 tu6_emit_fs_inputs(cs, &dummy_variant);
1401 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1402 builder->use_dual_src_blend,
1403 builder->render_components,
1404 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1405 }
1406
1407 if (gs || hs) {
1408 uint32_t cps_per_patch = builder->create_info->pTessellationState ?
1409 builder->create_info->pTessellationState->patchControlPoints : 0;
1410 tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch);
1411 }
1412 }
1413
1414 static void
1415 tu6_emit_vertex_input(struct tu_cs *cs,
1416 const struct ir3_shader_variant *vs,
1417 const VkPipelineVertexInputStateCreateInfo *info,
1418 uint32_t *bindings_used)
1419 {
1420 uint32_t vfd_decode_idx = 0;
1421 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1422 uint32_t step_rate[MAX_VBS];
1423
1424 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1425 const VkVertexInputBindingDescription *binding =
1426 &info->pVertexBindingDescriptions[i];
1427
1428 tu_cs_emit_regs(cs,
1429 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1430
1431 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1432 binding_instanced |= 1 << binding->binding;
1433
1434 *bindings_used |= 1 << binding->binding;
1435 step_rate[binding->binding] = 1;
1436 }
1437
1438 const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_state =
1439 vk_find_struct_const(info->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1440 if (div_state) {
1441 for (uint32_t i = 0; i < div_state->vertexBindingDivisorCount; i++) {
1442 const VkVertexInputBindingDivisorDescriptionEXT *desc =
1443 &div_state->pVertexBindingDivisors[i];
1444 step_rate[desc->binding] = desc->divisor;
1445 }
1446 }
1447
1448 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1449
1450 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1451 const VkVertexInputAttributeDescription *attr =
1452 &info->pVertexAttributeDescriptions[i];
1453 uint32_t input_idx;
1454
1455 assert(*bindings_used & BIT(attr->binding));
1456
1457 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1458 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1459 break;
1460 }
1461
1462 /* attribute not used, skip it */
1463 if (input_idx == vs->inputs_count)
1464 continue;
1465
1466 const struct tu_native_format format = tu6_format_vtx(attr->format);
1467 tu_cs_emit_regs(cs,
1468 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1469 .idx = attr->binding,
1470 .offset = attr->offset,
1471 .instanced = binding_instanced & (1 << attr->binding),
1472 .format = format.fmt,
1473 .swap = format.swap,
1474 .unk30 = 1,
1475 ._float = !vk_format_is_int(attr->format)),
1476 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, step_rate[attr->binding]));
1477
1478 tu_cs_emit_regs(cs,
1479 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1480 .writemask = vs->inputs[input_idx].compmask,
1481 .regid = vs->inputs[input_idx].regid));
1482
1483 vfd_decode_idx++;
1484 }
1485
1486 tu_cs_emit_regs(cs,
1487 A6XX_VFD_CONTROL_0(
1488 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1489 .decode_cnt = vfd_decode_idx));
1490 }
1491
1492 static uint32_t
1493 tu6_guardband_adj(uint32_t v)
1494 {
1495 if (v > 256)
1496 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1497 else
1498 return 511;
1499 }
1500
1501 void
1502 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1503 {
1504 float offsets[3];
1505 float scales[3];
1506 scales[0] = viewport->width / 2.0f;
1507 scales[1] = viewport->height / 2.0f;
1508 scales[2] = viewport->maxDepth - viewport->minDepth;
1509 offsets[0] = viewport->x + scales[0];
1510 offsets[1] = viewport->y + scales[1];
1511 offsets[2] = viewport->minDepth;
1512
1513 VkOffset2D min;
1514 VkOffset2D max;
1515 min.x = (int32_t) viewport->x;
1516 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1517 if (viewport->height >= 0.0f) {
1518 min.y = (int32_t) viewport->y;
1519 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1520 } else {
1521 min.y = (int32_t)(viewport->y + viewport->height);
1522 max.y = (int32_t) ceilf(viewport->y);
1523 }
1524 /* the spec allows viewport->height to be 0.0f */
1525 if (min.y == max.y)
1526 max.y++;
1527 assert(min.x >= 0 && min.x < max.x);
1528 assert(min.y >= 0 && min.y < max.y);
1529
1530 VkExtent2D guardband_adj;
1531 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1532 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1533
1534 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1535 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1536 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1537 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1538 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1539 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1540 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1541
1542 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1543 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1544 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1545 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1546 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1547
1548 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1549 tu_cs_emit(cs,
1550 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1551 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1552
1553 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1554 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1555
1556 tu_cs_emit_regs(cs,
1557 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1558 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1559
1560 tu_cs_emit_regs(cs,
1561 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1562 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1563 }
1564
1565 void
1566 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1567 {
1568 VkOffset2D min = scissor->offset;
1569 VkOffset2D max = {
1570 scissor->offset.x + scissor->extent.width,
1571 scissor->offset.y + scissor->extent.height,
1572 };
1573
1574 /* special case for empty scissor with max == 0 to avoid overflow */
1575 if (max.x == 0)
1576 min.x = max.x = 1;
1577 if (max.y == 0)
1578 min.y = max.y = 1;
1579
1580 /* avoid overflow with large scissor
1581 * note the max will be limited to min - 1, so that empty scissor works
1582 */
1583 uint32_t scissor_max = BITFIELD_MASK(15);
1584 min.x = MIN2(scissor_max, min.x);
1585 min.y = MIN2(scissor_max, min.y);
1586 max.x = MIN2(scissor_max, max.x);
1587 max.y = MIN2(scissor_max, max.y);
1588
1589 tu_cs_emit_regs(cs,
1590 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0(.x = min.x, .y = min.y),
1591 A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0(.x = max.x - 1, .y = max.y - 1));
1592 }
1593
1594 void
1595 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1596 {
1597 if (!samp_loc) {
1598 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1599 tu_cs_emit(cs, 0);
1600
1601 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1602 tu_cs_emit(cs, 0);
1603
1604 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1605 tu_cs_emit(cs, 0);
1606 return;
1607 }
1608
1609 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1610 assert(samp_loc->sampleLocationGridSize.width == 1);
1611 assert(samp_loc->sampleLocationGridSize.height == 1);
1612
1613 uint32_t sample_config =
1614 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1615 uint32_t sample_locations = 0;
1616 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1617 sample_locations |=
1618 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1619 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1620 }
1621
1622 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1623 tu_cs_emit(cs, sample_config);
1624 tu_cs_emit(cs, sample_locations);
1625
1626 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1627 tu_cs_emit(cs, sample_config);
1628 tu_cs_emit(cs, sample_locations);
1629
1630 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1631 tu_cs_emit(cs, sample_config);
1632 tu_cs_emit(cs, sample_locations);
1633 }
1634
1635 static uint32_t
1636 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1637 VkSampleCountFlagBits samples)
1638 {
1639 uint32_t gras_su_cntl = 0;
1640
1641 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1642 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1643 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1644 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1645
1646 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1647 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1648
1649 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1650
1651 if (rast_info->depthBiasEnable)
1652 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1653
1654 if (samples > VK_SAMPLE_COUNT_1_BIT)
1655 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1656
1657 return gras_su_cntl;
1658 }
1659
1660 void
1661 tu6_emit_depth_bias(struct tu_cs *cs,
1662 float constant_factor,
1663 float clamp,
1664 float slope_factor)
1665 {
1666 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1667 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1668 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1669 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1670 }
1671
1672 static void
1673 tu6_emit_depth_control(struct tu_cs *cs,
1674 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1675 const VkPipelineRasterizationStateCreateInfo *rast_info)
1676 {
1677 uint32_t rb_depth_cntl = 0;
1678 if (ds_info->depthTestEnable) {
1679 rb_depth_cntl |=
1680 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1681 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1682 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
1683
1684 if (rast_info->depthClampEnable)
1685 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1686
1687 if (ds_info->depthWriteEnable)
1688 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1689 }
1690
1691 if (ds_info->depthBoundsTestEnable)
1692 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1693
1694 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1695 tu_cs_emit(cs, rb_depth_cntl);
1696 }
1697
1698 static void
1699 tu6_emit_stencil_control(struct tu_cs *cs,
1700 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1701 {
1702 uint32_t rb_stencil_control = 0;
1703 if (ds_info->stencilTestEnable) {
1704 const VkStencilOpState *front = &ds_info->front;
1705 const VkStencilOpState *back = &ds_info->back;
1706 rb_stencil_control |=
1707 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1708 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1709 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1710 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1711 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1712 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1713 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1714 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1715 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1716 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1717 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1718 }
1719
1720 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1721 tu_cs_emit(cs, rb_stencil_control);
1722 }
1723
1724 static uint32_t
1725 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1726 bool has_alpha)
1727 {
1728 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1729 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1730 has_alpha ? att->srcColorBlendFactor
1731 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1732 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1733 has_alpha ? att->dstColorBlendFactor
1734 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1735 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1736 const enum adreno_rb_blend_factor src_alpha_factor =
1737 tu6_blend_factor(att->srcAlphaBlendFactor);
1738 const enum adreno_rb_blend_factor dst_alpha_factor =
1739 tu6_blend_factor(att->dstAlphaBlendFactor);
1740
1741 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1742 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1743 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1744 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1745 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1746 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1747 }
1748
1749 static uint32_t
1750 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1751 uint32_t rb_mrt_control_rop,
1752 bool is_int,
1753 bool has_alpha)
1754 {
1755 uint32_t rb_mrt_control =
1756 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1757
1758 /* ignore blending and logic op for integer attachments */
1759 if (is_int) {
1760 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1761 return rb_mrt_control;
1762 }
1763
1764 rb_mrt_control |= rb_mrt_control_rop;
1765
1766 if (att->blendEnable) {
1767 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1768
1769 if (has_alpha)
1770 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1771 }
1772
1773 return rb_mrt_control;
1774 }
1775
1776 static void
1777 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1778 const VkPipelineColorBlendStateCreateInfo *blend_info,
1779 const VkFormat attachment_formats[MAX_RTS],
1780 uint32_t *blend_enable_mask)
1781 {
1782 *blend_enable_mask = 0;
1783
1784 bool rop_reads_dst = false;
1785 uint32_t rb_mrt_control_rop = 0;
1786 if (blend_info->logicOpEnable) {
1787 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1788 rb_mrt_control_rop =
1789 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1790 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1791 }
1792
1793 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1794 const VkPipelineColorBlendAttachmentState *att =
1795 &blend_info->pAttachments[i];
1796 const VkFormat format = attachment_formats[i];
1797
1798 uint32_t rb_mrt_control = 0;
1799 uint32_t rb_mrt_blend_control = 0;
1800 if (format != VK_FORMAT_UNDEFINED) {
1801 const bool is_int = vk_format_is_int(format);
1802 const bool has_alpha = vk_format_has_alpha(format);
1803
1804 rb_mrt_control =
1805 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1806 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1807
1808 if (att->blendEnable || rop_reads_dst)
1809 *blend_enable_mask |= 1 << i;
1810 }
1811
1812 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1813 tu_cs_emit(cs, rb_mrt_control);
1814 tu_cs_emit(cs, rb_mrt_blend_control);
1815 }
1816 }
1817
1818 static void
1819 tu6_emit_blend_control(struct tu_cs *cs,
1820 uint32_t blend_enable_mask,
1821 bool dual_src_blend,
1822 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1823 {
1824 const uint32_t sample_mask =
1825 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1826 : ((1 << msaa_info->rasterizationSamples) - 1);
1827
1828 tu_cs_emit_regs(cs,
1829 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1830 .dual_color_in_enable = dual_src_blend,
1831 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1832 .unk8 = true));
1833
1834 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1835 tu_cs_emit_regs(cs,
1836 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1837 .independent_blend = true,
1838 .sample_mask = sample_mask,
1839 .dual_color_in_enable = dual_src_blend,
1840 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1841 .alpha_to_one = msaa_info->alphaToOneEnable));
1842 }
1843
1844 static VkResult
1845 tu_pipeline_allocate_cs(struct tu_device *dev,
1846 struct tu_pipeline *pipeline,
1847 struct tu_pipeline_builder *builder,
1848 struct ir3_shader_variant *compute)
1849 {
1850 uint32_t size = 2048 + tu6_load_state_size(pipeline->layout, compute);
1851
1852 /* graphics case: */
1853 if (builder) {
1854 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1855 if (builder->variants[i])
1856 size += builder->variants[i]->info.sizedwords;
1857 }
1858
1859 size += builder->binning_variant->info.sizedwords;
1860 } else {
1861 size += compute->info.sizedwords;
1862 }
1863
1864 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, size);
1865
1866 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1867 * that LOAD_STATE can potentially take up a large amount of space so we
1868 * calculate its size explicitly.
1869 */
1870 return tu_cs_reserve_space(&pipeline->cs, size);
1871 }
1872
1873 static void
1874 tu_pipeline_shader_key_init(struct ir3_shader_key *key,
1875 const VkGraphicsPipelineCreateInfo *pipeline_info)
1876 {
1877 for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
1878 if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
1879 key->has_gs = true;
1880 break;
1881 }
1882 }
1883
1884 if (pipeline_info->pRasterizationState->rasterizerDiscardEnable)
1885 return;
1886
1887 const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
1888 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
1889 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1890 if (msaa_info->rasterizationSamples > 1 ||
1891 /* also set msaa key when sample location is not the default
1892 * since this affects varying interpolation */
1893 (sample_locations && sample_locations->sampleLocationsEnable)) {
1894 key->msaa = true;
1895 }
1896
1897 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1898 if (msaa_info->sampleShadingEnable)
1899 key->sample_shading = true;
1900
1901 /* We set this after we compile to NIR because we need the prim mode */
1902 key->tessellation = IR3_TESS_NONE;
1903 }
1904
1905 static uint32_t
1906 tu6_get_tessmode(struct tu_shader* shader)
1907 {
1908 uint32_t primitive_mode = shader->ir3_shader->nir->info.tess.primitive_mode;
1909 switch (primitive_mode) {
1910 case GL_ISOLINES:
1911 return IR3_TESS_ISOLINES;
1912 case GL_TRIANGLES:
1913 return IR3_TESS_TRIANGLES;
1914 case GL_QUADS:
1915 return IR3_TESS_QUADS;
1916 case GL_NONE:
1917 return IR3_TESS_NONE;
1918 default:
1919 unreachable("bad tessmode");
1920 }
1921 }
1922
1923 static uint64_t
1924 tu_upload_variant(struct tu_pipeline *pipeline,
1925 const struct ir3_shader_variant *variant)
1926 {
1927 struct tu_cs_memory memory;
1928
1929 if (!variant)
1930 return 0;
1931
1932 /* this expects to get enough alignment because shaders are allocated first
1933 * and sizedwords is always aligned correctly
1934 * note: an assert in tu6_emit_xs_config validates the alignment
1935 */
1936 tu_cs_alloc(&pipeline->cs, variant->info.sizedwords, 1, &memory);
1937
1938 memcpy(memory.map, variant->bin, sizeof(uint32_t) * variant->info.sizedwords);
1939 return memory.iova;
1940 }
1941
1942 static VkResult
1943 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
1944 struct tu_pipeline *pipeline)
1945 {
1946 const struct ir3_compiler *compiler = builder->device->compiler;
1947 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1948 NULL
1949 };
1950 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1951 gl_shader_stage stage =
1952 vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage);
1953 stage_infos[stage] = &builder->create_info->pStages[i];
1954 }
1955
1956 struct ir3_shader_key key = {};
1957 tu_pipeline_shader_key_init(&key, builder->create_info);
1958
1959 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1960 stage < MESA_SHADER_STAGES; stage++) {
1961 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1962 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
1963 continue;
1964
1965 struct tu_shader *shader =
1966 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1967 builder->alloc);
1968 if (!shader)
1969 return VK_ERROR_OUT_OF_HOST_MEMORY;
1970
1971 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
1972 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
1973 * the mode is specified in the tessellation control shader. */
1974 if ((stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_TESS_CTRL) &&
1975 key.tessellation == IR3_TESS_NONE) {
1976 key.tessellation = tu6_get_tessmode(shader);
1977 }
1978
1979 builder->shaders[stage] = shader;
1980 }
1981
1982 struct tu_shader *gs = builder->shaders[MESA_SHADER_GEOMETRY];
1983 key.layer_zero =
1984 !gs || !(gs->ir3_shader->nir->info.outputs_written & VARYING_SLOT_LAYER);
1985
1986 pipeline->tess.patch_type = key.tessellation;
1987
1988 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1989 stage < MESA_SHADER_STAGES; stage++) {
1990 if (!builder->shaders[stage])
1991 continue;
1992
1993 bool created;
1994 builder->variants[stage] =
1995 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
1996 &key, false, &created);
1997 if (!builder->variants[stage])
1998 return VK_ERROR_OUT_OF_HOST_MEMORY;
1999 }
2000
2001 uint32_t safe_constlens = ir3_trim_constlen(builder->variants, compiler);
2002
2003 key.safe_constlen = true;
2004
2005 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2006 stage < MESA_SHADER_STAGES; stage++) {
2007 if (!builder->shaders[stage])
2008 continue;
2009
2010 if (safe_constlens & (1 << stage)) {
2011 bool created;
2012 builder->variants[stage] =
2013 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2014 &key, false, &created);
2015 if (!builder->variants[stage])
2016 return VK_ERROR_OUT_OF_HOST_MEMORY;
2017 }
2018 }
2019
2020 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2021 struct ir3_shader_variant *variant;
2022
2023 if (vs->ir3_shader->stream_output.num_outputs ||
2024 !ir3_has_binning_vs(&key)) {
2025 variant = builder->variants[MESA_SHADER_VERTEX];
2026 } else {
2027 bool created;
2028 key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX));
2029 variant = ir3_shader_get_variant(vs->ir3_shader, &key,
2030 true, &created);
2031 if (!variant)
2032 return VK_ERROR_OUT_OF_HOST_MEMORY;
2033 }
2034
2035 builder->binning_variant = variant;
2036
2037 return VK_SUCCESS;
2038 }
2039
2040 static void
2041 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2042 struct tu_pipeline *pipeline)
2043 {
2044 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2045 builder->create_info->pDynamicState;
2046
2047 if (!dynamic_info)
2048 return;
2049
2050 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2051 VkDynamicState state = dynamic_info->pDynamicStates[i];
2052 switch (state) {
2053 case VK_DYNAMIC_STATE_VIEWPORT ... VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2054 pipeline->dynamic_state_mask |= BIT(state);
2055 break;
2056 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
2057 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS);
2058 break;
2059 default:
2060 assert(!"unsupported dynamic state");
2061 break;
2062 }
2063 }
2064 }
2065
2066 static void
2067 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2068 struct tu_shader *shader,
2069 struct ir3_shader_variant *v)
2070 {
2071 link->const_state = *ir3_const_state(v);
2072 link->constlen = v->constlen;
2073 link->push_consts = shader->push_consts;
2074 }
2075
2076 static void
2077 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2078 struct tu_pipeline *pipeline)
2079 {
2080 struct tu_cs prog_cs;
2081 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2082 tu6_emit_program(&prog_cs, builder, false);
2083 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2084
2085 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2086 tu6_emit_program(&prog_cs, builder, true);
2087 pipeline->program.binning_state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2088
2089 VkShaderStageFlags stages = 0;
2090 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2091 stages |= builder->create_info->pStages[i].stage;
2092 }
2093 pipeline->active_stages = stages;
2094
2095 uint32_t desc_sets = 0;
2096 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2097 if (!builder->shaders[i])
2098 continue;
2099
2100 tu_pipeline_set_linkage(&pipeline->program.link[i],
2101 builder->shaders[i],
2102 builder->variants[i]);
2103 desc_sets |= builder->shaders[i]->active_desc_sets;
2104 }
2105 pipeline->active_desc_sets = desc_sets;
2106 }
2107
2108 static void
2109 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2110 struct tu_pipeline *pipeline)
2111 {
2112 const VkPipelineVertexInputStateCreateInfo *vi_info =
2113 builder->create_info->pVertexInputState;
2114 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
2115 const struct ir3_shader_variant *bs = builder->binning_variant;
2116
2117 struct tu_cs vi_cs;
2118 tu_cs_begin_sub_stream(&pipeline->cs,
2119 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2120 tu6_emit_vertex_input(&vi_cs, vs, vi_info,
2121 &pipeline->vi.bindings_used);
2122 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2123
2124 if (bs) {
2125 tu_cs_begin_sub_stream(&pipeline->cs,
2126 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2127 tu6_emit_vertex_input(
2128 &vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
2129 pipeline->vi.binning_state_ib =
2130 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2131 }
2132 }
2133
2134 static void
2135 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2136 struct tu_pipeline *pipeline)
2137 {
2138 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2139 builder->create_info->pInputAssemblyState;
2140
2141 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2142 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2143 }
2144
2145 static bool
2146 tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs,
2147 uint32_t id, uint32_t size)
2148 {
2149 struct tu_cs_memory memory;
2150
2151 if (pipeline->dynamic_state_mask & BIT(id))
2152 return false;
2153
2154 /* TODO: share this logc with tu_cmd_dynamic_state */
2155 tu_cs_alloc(&pipeline->cs, size, 1, &memory);
2156 tu_cs_init_external(cs, memory.map, memory.map + size);
2157 tu_cs_begin(cs);
2158 tu_cs_reserve_space(cs, size);
2159
2160 assert(id < ARRAY_SIZE(pipeline->dynamic_state));
2161 pipeline->dynamic_state[id].iova = memory.iova;
2162 pipeline->dynamic_state[id].size = size;
2163 return true;
2164 }
2165
2166 static void
2167 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder,
2168 struct tu_pipeline *pipeline)
2169 {
2170 const VkPipelineTessellationStateCreateInfo *tess_info =
2171 builder->create_info->pTessellationState;
2172
2173 if (!tess_info)
2174 return;
2175
2176 assert(pipeline->ia.primtype == DI_PT_PATCHES0);
2177 assert(tess_info->patchControlPoints <= 32);
2178 pipeline->ia.primtype += tess_info->patchControlPoints;
2179 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info =
2180 vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2181 pipeline->tess.upper_left_domain_origin = !domain_info ||
2182 domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
2183 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
2184 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
2185 pipeline->tess.param_stride = hs->output_size * 4;
2186 pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1;
2187 pipeline->tess.ds_bo_regid = ds->const_state->offsets.primitive_param + 1;
2188 }
2189
2190 static void
2191 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2192 struct tu_pipeline *pipeline)
2193 {
2194 /* The spec says:
2195 *
2196 * pViewportState is a pointer to an instance of the
2197 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2198 * pipeline has rasterization disabled."
2199 *
2200 * We leave the relevant registers stale in that case.
2201 */
2202 if (builder->rasterizer_discard)
2203 return;
2204
2205 const VkPipelineViewportStateCreateInfo *vp_info =
2206 builder->create_info->pViewportState;
2207
2208 struct tu_cs cs;
2209
2210 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_VIEWPORT, 18))
2211 tu6_emit_viewport(&cs, vp_info->pViewports);
2212
2213 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_SCISSOR, 3))
2214 tu6_emit_scissor(&cs, vp_info->pScissors);
2215 }
2216
2217 static void
2218 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2219 struct tu_pipeline *pipeline)
2220 {
2221 const VkPipelineRasterizationStateCreateInfo *rast_info =
2222 builder->create_info->pRasterizationState;
2223
2224 enum a6xx_polygon_mode mode = tu6_polygon_mode(rast_info->polygonMode);
2225
2226 struct tu_cs cs;
2227 tu_cs_begin_sub_stream(&pipeline->cs, 9, &cs);
2228
2229 tu_cs_emit_regs(&cs,
2230 A6XX_GRAS_CL_CNTL(
2231 .znear_clip_disable = rast_info->depthClampEnable,
2232 .zfar_clip_disable = rast_info->depthClampEnable,
2233 .unk5 = rast_info->depthClampEnable,
2234 .zero_gb_scale_z = 1,
2235 .vp_clip_code_ignore = 1));
2236
2237 tu_cs_emit_regs(&cs,
2238 A6XX_VPC_POLYGON_MODE(.mode = mode));
2239
2240 tu_cs_emit_regs(&cs,
2241 A6XX_PC_POLYGON_MODE(.mode = mode));
2242
2243 /* move to hw ctx init? */
2244 tu_cs_emit_regs(&cs,
2245 A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
2246 A6XX_GRAS_SU_POINT_SIZE(1.0f));
2247
2248 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2249
2250 pipeline->gras_su_cntl =
2251 tu6_gras_su_cntl(rast_info, builder->samples);
2252
2253 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_LINE_WIDTH, 2)) {
2254 pipeline->gras_su_cntl |=
2255 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info->lineWidth / 2.0f);
2256 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = pipeline->gras_su_cntl));
2257 }
2258
2259 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BIAS, 4)) {
2260 tu6_emit_depth_bias(&cs, rast_info->depthBiasConstantFactor,
2261 rast_info->depthBiasClamp,
2262 rast_info->depthBiasSlopeFactor);
2263 }
2264
2265 }
2266
2267 static void
2268 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2269 struct tu_pipeline *pipeline)
2270 {
2271 /* The spec says:
2272 *
2273 * pDepthStencilState is a pointer to an instance of the
2274 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2275 * the pipeline has rasterization disabled or if the subpass of the
2276 * render pass the pipeline is created against does not use a
2277 * depth/stencil attachment.
2278 *
2279 * Disable both depth and stencil tests if there is no ds attachment,
2280 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2281 * only the separate stencil attachment
2282 */
2283 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2284 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2285 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2286 ? builder->create_info->pDepthStencilState
2287 : &dummy_ds_info;
2288 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2289 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2290 ? ds_info : &dummy_ds_info;
2291
2292 struct tu_cs cs;
2293 tu_cs_begin_sub_stream(&pipeline->cs, 6, &cs);
2294
2295 /* move to hw ctx init? */
2296 tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
2297 tu6_emit_depth_control(&cs, ds_info_depth,
2298 builder->create_info->pRasterizationState);
2299 tu6_emit_stencil_control(&cs, ds_info);
2300
2301 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2302
2303 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
2304 tu_cs_emit_regs(&cs,
2305 A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
2306 A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
2307 }
2308
2309 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
2310 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
2311 .bfmask = ds_info->back.compareMask & 0xff));
2312 }
2313
2314 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2)) {
2315 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.wrmask = ds_info->front.writeMask & 0xff,
2316 .bfwrmask = ds_info->back.writeMask & 0xff));
2317 }
2318
2319 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2)) {
2320 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.ref = ds_info->front.reference & 0xff,
2321 .bfref = ds_info->back.reference & 0xff));
2322 }
2323 }
2324
2325 static void
2326 tu_pipeline_builder_parse_multisample_and_color_blend(
2327 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2328 {
2329 /* The spec says:
2330 *
2331 * pMultisampleState is a pointer to an instance of the
2332 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2333 * has rasterization disabled.
2334 *
2335 * Also,
2336 *
2337 * pColorBlendState is a pointer to an instance of the
2338 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2339 * pipeline has rasterization disabled or if the subpass of the render
2340 * pass the pipeline is created against does not use any color
2341 * attachments.
2342 *
2343 * We leave the relevant registers stale when rasterization is disabled.
2344 */
2345 if (builder->rasterizer_discard)
2346 return;
2347
2348 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2349 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2350 builder->create_info->pMultisampleState;
2351 const VkPipelineColorBlendStateCreateInfo *blend_info =
2352 builder->use_color_attachments ? builder->create_info->pColorBlendState
2353 : &dummy_blend_info;
2354
2355 struct tu_cs cs;
2356 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 4, &cs);
2357
2358 uint32_t blend_enable_mask;
2359 tu6_emit_rb_mrt_controls(&cs, blend_info,
2360 builder->color_attachment_formats,
2361 &blend_enable_mask);
2362
2363 tu6_emit_blend_control(&cs, blend_enable_mask,
2364 builder->use_dual_src_blend, msaa_info);
2365
2366 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
2367
2368 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5)) {
2369 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2370 tu_cs_emit_array(&cs, (const uint32_t *) blend_info->blendConstants, 4);
2371 }
2372
2373 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2374 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2375 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2376
2377 if (sample_locations && sample_locations->sampleLocationsEnable)
2378 samp_loc = &sample_locations->sampleLocationsInfo;
2379
2380 if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
2381 samp_loc ? 9 : 6)) {
2382 tu6_emit_sample_locations(&cs, samp_loc);
2383 }
2384 }
2385
2386 static void
2387 tu_pipeline_finish(struct tu_pipeline *pipeline,
2388 struct tu_device *dev,
2389 const VkAllocationCallbacks *alloc)
2390 {
2391 tu_cs_finish(&pipeline->cs);
2392 }
2393
2394 static VkResult
2395 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2396 struct tu_pipeline **pipeline)
2397 {
2398 VkResult result;
2399
2400 *pipeline = vk_object_zalloc(&builder->device->vk, builder->alloc,
2401 sizeof(**pipeline), VK_OBJECT_TYPE_PIPELINE);
2402 if (!*pipeline)
2403 return VK_ERROR_OUT_OF_HOST_MEMORY;
2404
2405 (*pipeline)->layout = builder->layout;
2406
2407 /* compile and upload shaders */
2408 result = tu_pipeline_builder_compile_shaders(builder, *pipeline);
2409 if (result != VK_SUCCESS) {
2410 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2411 return result;
2412 }
2413
2414 result = tu_pipeline_allocate_cs(builder->device, *pipeline, builder, NULL);
2415 if (result != VK_SUCCESS) {
2416 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2417 return result;
2418 }
2419
2420 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2421 builder->shader_iova[i] = tu_upload_variant(*pipeline, builder->variants[i]);
2422
2423 builder->binning_vs_iova =
2424 tu_upload_variant(*pipeline, builder->binning_variant);
2425
2426 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2427 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2428 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2429 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2430 tu_pipeline_builder_parse_tessellation(builder, *pipeline);
2431 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2432 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2433 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2434 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2435 tu6_emit_load_state(*pipeline, false);
2436
2437 /* we should have reserved enough space upfront such that the CS never
2438 * grows
2439 */
2440 assert((*pipeline)->cs.bo_count == 1);
2441
2442 return VK_SUCCESS;
2443 }
2444
2445 static void
2446 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2447 {
2448 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2449 if (!builder->shaders[i])
2450 continue;
2451 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2452 }
2453 }
2454
2455 static void
2456 tu_pipeline_builder_init_graphics(
2457 struct tu_pipeline_builder *builder,
2458 struct tu_device *dev,
2459 struct tu_pipeline_cache *cache,
2460 const VkGraphicsPipelineCreateInfo *create_info,
2461 const VkAllocationCallbacks *alloc)
2462 {
2463 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2464
2465 *builder = (struct tu_pipeline_builder) {
2466 .device = dev,
2467 .cache = cache,
2468 .create_info = create_info,
2469 .alloc = alloc,
2470 .layout = layout,
2471 };
2472
2473 builder->rasterizer_discard =
2474 create_info->pRasterizationState->rasterizerDiscardEnable;
2475
2476 if (builder->rasterizer_discard) {
2477 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2478 } else {
2479 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2480
2481 const struct tu_render_pass *pass =
2482 tu_render_pass_from_handle(create_info->renderPass);
2483 const struct tu_subpass *subpass =
2484 &pass->subpasses[create_info->subpass];
2485
2486 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2487 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2488 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2489
2490 assert(subpass->color_count == 0 ||
2491 !create_info->pColorBlendState ||
2492 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2493 builder->color_attachment_count = subpass->color_count;
2494 for (uint32_t i = 0; i < subpass->color_count; i++) {
2495 const uint32_t a = subpass->color_attachments[i].attachment;
2496 if (a == VK_ATTACHMENT_UNUSED)
2497 continue;
2498
2499 builder->color_attachment_formats[i] = pass->attachments[a].format;
2500 builder->use_color_attachments = true;
2501 builder->render_components |= 0xf << (i * 4);
2502 }
2503
2504 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2505 builder->color_attachment_count++;
2506 builder->use_dual_src_blend = true;
2507 /* dual source blending has an extra fs output in the 2nd slot */
2508 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2509 builder->render_components |= 0xf << 4;
2510 }
2511 }
2512 }
2513
2514 static VkResult
2515 tu_graphics_pipeline_create(VkDevice device,
2516 VkPipelineCache pipelineCache,
2517 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2518 const VkAllocationCallbacks *pAllocator,
2519 VkPipeline *pPipeline)
2520 {
2521 TU_FROM_HANDLE(tu_device, dev, device);
2522 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2523
2524 struct tu_pipeline_builder builder;
2525 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2526 pCreateInfo, pAllocator);
2527
2528 struct tu_pipeline *pipeline = NULL;
2529 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2530 tu_pipeline_builder_finish(&builder);
2531
2532 if (result == VK_SUCCESS)
2533 *pPipeline = tu_pipeline_to_handle(pipeline);
2534 else
2535 *pPipeline = VK_NULL_HANDLE;
2536
2537 return result;
2538 }
2539
2540 VkResult
2541 tu_CreateGraphicsPipelines(VkDevice device,
2542 VkPipelineCache pipelineCache,
2543 uint32_t count,
2544 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2545 const VkAllocationCallbacks *pAllocator,
2546 VkPipeline *pPipelines)
2547 {
2548 VkResult final_result = VK_SUCCESS;
2549
2550 for (uint32_t i = 0; i < count; i++) {
2551 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2552 &pCreateInfos[i], pAllocator,
2553 &pPipelines[i]);
2554
2555 if (result != VK_SUCCESS)
2556 final_result = result;
2557 }
2558
2559 return final_result;
2560 }
2561
2562 static VkResult
2563 tu_compute_pipeline_create(VkDevice device,
2564 VkPipelineCache _cache,
2565 const VkComputePipelineCreateInfo *pCreateInfo,
2566 const VkAllocationCallbacks *pAllocator,
2567 VkPipeline *pPipeline)
2568 {
2569 TU_FROM_HANDLE(tu_device, dev, device);
2570 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2571 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2572 VkResult result;
2573
2574 struct tu_pipeline *pipeline;
2575
2576 *pPipeline = VK_NULL_HANDLE;
2577
2578 pipeline = vk_object_zalloc(&dev->vk, pAllocator, sizeof(*pipeline),
2579 VK_OBJECT_TYPE_PIPELINE);
2580 if (!pipeline)
2581 return VK_ERROR_OUT_OF_HOST_MEMORY;
2582
2583 pipeline->layout = layout;
2584
2585 struct ir3_shader_key key = {};
2586
2587 struct tu_shader *shader =
2588 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2589 if (!shader) {
2590 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2591 goto fail;
2592 }
2593
2594 pipeline->active_desc_sets = shader->active_desc_sets;
2595
2596 bool created;
2597 struct ir3_shader_variant *v =
2598 ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
2599 if (!v) {
2600 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2601 goto fail;
2602 }
2603
2604 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2605 shader, v);
2606
2607 result = tu_pipeline_allocate_cs(dev, pipeline, NULL, v);
2608 if (result != VK_SUCCESS)
2609 goto fail;
2610
2611 uint64_t shader_iova = tu_upload_variant(pipeline, v);
2612
2613 for (int i = 0; i < 3; i++)
2614 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2615
2616 struct tu_cs prog_cs;
2617 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2618 tu6_emit_cs_config(&prog_cs, shader, v, shader_iova);
2619 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2620
2621 tu6_emit_load_state(pipeline, true);
2622
2623 *pPipeline = tu_pipeline_to_handle(pipeline);
2624 return VK_SUCCESS;
2625
2626 fail:
2627 if (shader)
2628 tu_shader_destroy(dev, shader, pAllocator);
2629
2630 vk_object_free(&dev->vk, pAllocator, pipeline);
2631
2632 return result;
2633 }
2634
2635 VkResult
2636 tu_CreateComputePipelines(VkDevice device,
2637 VkPipelineCache pipelineCache,
2638 uint32_t count,
2639 const VkComputePipelineCreateInfo *pCreateInfos,
2640 const VkAllocationCallbacks *pAllocator,
2641 VkPipeline *pPipelines)
2642 {
2643 VkResult final_result = VK_SUCCESS;
2644
2645 for (uint32_t i = 0; i < count; i++) {
2646 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2647 &pCreateInfos[i],
2648 pAllocator, &pPipelines[i]);
2649 if (result != VK_SUCCESS)
2650 final_result = result;
2651 }
2652
2653 return final_result;
2654 }
2655
2656 void
2657 tu_DestroyPipeline(VkDevice _device,
2658 VkPipeline _pipeline,
2659 const VkAllocationCallbacks *pAllocator)
2660 {
2661 TU_FROM_HANDLE(tu_device, dev, _device);
2662 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2663
2664 if (!_pipeline)
2665 return;
2666
2667 tu_pipeline_finish(pipeline, dev, pAllocator);
2668 vk_object_free(&dev->vk, pAllocator, pipeline);
2669 }