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freedreno/regs: update a6xx PC regs
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static void
46 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
47 enum a6xx_state_block sb, unsigned base, unsigned offset,
48 unsigned count)
49 {
50 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
51 * clear if emitting more packets will even help anything. Presumably the
52 * descriptor cache is relatively small, and these packets stop doing
53 * anything when there are too many descriptors.
54 */
55 tu_cs_emit_pkt7(cs, opcode, 3);
56 tu_cs_emit(cs,
57 CP_LOAD_STATE6_0_STATE_TYPE(st) |
58 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
59 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
60 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
61 tu_cs_emit_qw(cs, offset | (base << 28));
62 }
63
64 static unsigned
65 tu6_load_state_size(struct tu_pipeline *pipeline, bool compute)
66 {
67 const unsigned load_state_size = 4;
68 unsigned size = 0;
69 for (unsigned i = 0; i < pipeline->layout->num_sets; i++) {
70 if (pipeline && !(pipeline->active_desc_sets & (1u << i)))
71 continue;
72
73 struct tu_descriptor_set_layout *set_layout = pipeline->layout->set[i].layout;
74 for (unsigned j = 0; j < set_layout->binding_count; j++) {
75 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
76 unsigned count = 0;
77 /* Note: some users, like amber for example, pass in
78 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
79 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
80 */
81 VkShaderStageFlags stages = compute ?
82 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
83 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
84 unsigned stage_count = util_bitcount(stages);
85
86 if (!binding->array_size)
87 continue;
88
89 switch (binding->type) {
90 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
91 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
92 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
93 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
94 /* IBO-backed resources only need one packet for all graphics stages */
95 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
96 count += 1;
97 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
98 count += 1;
99 break;
100 case VK_DESCRIPTOR_TYPE_SAMPLER:
101 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
102 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
103 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
104 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
105 /* Textures and UBO's needs a packet for each stage */
106 count = stage_count;
107 break;
108 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
109 /* Because of how we pack combined images and samplers, we
110 * currently can't use one packet for the whole array.
111 */
112 count = stage_count * binding->array_size * 2;
113 break;
114 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
115 break;
116 default:
117 unreachable("bad descriptor type");
118 }
119 size += count * load_state_size;
120 }
121 }
122 return size;
123 }
124
125 static void
126 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
127 {
128 unsigned size = tu6_load_state_size(pipeline, compute);
129 if (size == 0)
130 return;
131
132 struct tu_cs cs;
133 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
134
135 struct tu_pipeline_layout *layout = pipeline->layout;
136 for (unsigned i = 0; i < layout->num_sets; i++) {
137 /* From 13.2.7. Descriptor Set Binding:
138 *
139 * A compatible descriptor set must be bound for all set numbers that
140 * any shaders in a pipeline access, at the time that a draw or
141 * dispatch command is recorded to execute using that pipeline.
142 * However, if none of the shaders in a pipeline statically use any
143 * bindings with a particular set number, then no descriptor set need
144 * be bound for that set number, even if the pipeline layout includes
145 * a non-trivial descriptor set layout for that set number.
146 *
147 * This means that descriptor sets unused by the pipeline may have a
148 * garbage or 0 BINDLESS_BASE register, which will cause context faults
149 * when prefetching descriptors from these sets. Skip prefetching for
150 * descriptors from them to avoid this. This is also an optimization,
151 * since these prefetches would be useless.
152 */
153 if (!(pipeline->active_desc_sets & (1u << i)))
154 continue;
155
156 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
157 for (unsigned j = 0; j < set_layout->binding_count; j++) {
158 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
159 unsigned base = i;
160 unsigned offset = binding->offset / 4;
161 /* Note: some users, like amber for example, pass in
162 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
163 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
164 */
165 VkShaderStageFlags stages = compute ?
166 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
167 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
168 unsigned count = binding->array_size;
169 if (count == 0 || stages == 0)
170 continue;
171 switch (binding->type) {
172 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
173 base = MAX_SETS;
174 offset = (layout->set[i].dynamic_offset_start +
175 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
176 /* fallthrough */
177 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
178 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
179 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
180 /* IBO-backed resources only need one packet for all graphics stages */
181 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
182 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
183 base, offset, count);
184 }
185 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
186 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
187 base, offset, count);
188 }
189 break;
190 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
191 /* nothing - input attachment doesn't use bindless */
192 break;
193 case VK_DESCRIPTOR_TYPE_SAMPLER:
194 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
195 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
196 tu_foreach_stage(stage, stages) {
197 emit_load_state(&cs, tu6_stage2opcode(stage),
198 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
199 ST6_SHADER : ST6_CONSTANTS,
200 tu6_stage2texsb(stage), base, offset, count);
201 }
202 break;
203 }
204 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
205 base = MAX_SETS;
206 offset = (layout->set[i].dynamic_offset_start +
207 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
208 /* fallthrough */
209 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
210 tu_foreach_stage(stage, stages) {
211 emit_load_state(&cs, tu6_stage2opcode(stage), ST6_UBO,
212 tu6_stage2shadersb(stage), base, offset, count);
213 }
214 break;
215 }
216 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
217 tu_foreach_stage(stage, stages) {
218 /* TODO: We could emit less CP_LOAD_STATE6 if we used
219 * struct-of-arrays instead of array-of-structs.
220 */
221 for (unsigned i = 0; i < count; i++) {
222 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
223 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
224 emit_load_state(&cs, tu6_stage2opcode(stage),
225 ST6_CONSTANTS, tu6_stage2texsb(stage),
226 base, tex_offset, 1);
227 emit_load_state(&cs, tu6_stage2opcode(stage),
228 ST6_SHADER, tu6_stage2texsb(stage),
229 base, sam_offset, 1);
230 }
231 }
232 break;
233 }
234 default:
235 unreachable("bad descriptor type");
236 }
237 }
238 }
239
240 pipeline->load_state = tu_cs_end_draw_state(&pipeline->cs, &cs);
241 }
242
243 struct tu_pipeline_builder
244 {
245 struct tu_device *device;
246 struct tu_pipeline_cache *cache;
247 struct tu_pipeline_layout *layout;
248 const VkAllocationCallbacks *alloc;
249 const VkGraphicsPipelineCreateInfo *create_info;
250
251 struct tu_shader *shaders[MESA_SHADER_STAGES];
252 struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
253 struct ir3_shader_variant *binning_variant;
254 uint64_t shader_iova[MESA_SHADER_STAGES];
255 uint64_t binning_vs_iova;
256
257 bool rasterizer_discard;
258 /* these states are affectd by rasterizer_discard */
259 VkSampleCountFlagBits samples;
260 bool use_color_attachments;
261 bool use_dual_src_blend;
262 uint32_t color_attachment_count;
263 VkFormat color_attachment_formats[MAX_RTS];
264 VkFormat depth_attachment_format;
265 uint32_t render_components;
266 };
267
268 static bool
269 tu_logic_op_reads_dst(VkLogicOp op)
270 {
271 switch (op) {
272 case VK_LOGIC_OP_CLEAR:
273 case VK_LOGIC_OP_COPY:
274 case VK_LOGIC_OP_COPY_INVERTED:
275 case VK_LOGIC_OP_SET:
276 return false;
277 default:
278 return true;
279 }
280 }
281
282 static VkBlendFactor
283 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
284 {
285 /* treat dst alpha as 1.0 and avoid reading it */
286 switch (factor) {
287 case VK_BLEND_FACTOR_DST_ALPHA:
288 return VK_BLEND_FACTOR_ONE;
289 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
290 return VK_BLEND_FACTOR_ZERO;
291 default:
292 return factor;
293 }
294 }
295
296 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor)
297 {
298 switch (factor) {
299 case VK_BLEND_FACTOR_SRC1_COLOR:
300 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
301 case VK_BLEND_FACTOR_SRC1_ALPHA:
302 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
303 return true;
304 default:
305 return false;
306 }
307 }
308
309 static bool
310 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo *info)
311 {
312 if (!info)
313 return false;
314
315 for (unsigned i = 0; i < info->attachmentCount; i++) {
316 const VkPipelineColorBlendAttachmentState *blend = &info->pAttachments[i];
317 if (tu_blend_factor_is_dual_src(blend->srcColorBlendFactor) ||
318 tu_blend_factor_is_dual_src(blend->dstColorBlendFactor) ||
319 tu_blend_factor_is_dual_src(blend->srcAlphaBlendFactor) ||
320 tu_blend_factor_is_dual_src(blend->dstAlphaBlendFactor))
321 return true;
322 }
323
324 return false;
325 }
326
327 void
328 tu6_emit_xs_config(struct tu_cs *cs,
329 gl_shader_stage stage, /* xs->type, but xs may be NULL */
330 const struct ir3_shader_variant *xs,
331 uint64_t binary_iova)
332 {
333 static const struct xs_config {
334 uint16_t reg_sp_xs_ctrl;
335 uint16_t reg_sp_xs_config;
336 uint16_t reg_hlsq_xs_ctrl;
337 uint16_t reg_sp_vs_obj_start;
338 } xs_config[] = {
339 [MESA_SHADER_VERTEX] = {
340 REG_A6XX_SP_VS_CTRL_REG0,
341 REG_A6XX_SP_VS_CONFIG,
342 REG_A6XX_HLSQ_VS_CNTL,
343 REG_A6XX_SP_VS_OBJ_START_LO,
344 },
345 [MESA_SHADER_TESS_CTRL] = {
346 REG_A6XX_SP_HS_CTRL_REG0,
347 REG_A6XX_SP_HS_CONFIG,
348 REG_A6XX_HLSQ_HS_CNTL,
349 REG_A6XX_SP_HS_OBJ_START_LO,
350 },
351 [MESA_SHADER_TESS_EVAL] = {
352 REG_A6XX_SP_DS_CTRL_REG0,
353 REG_A6XX_SP_DS_CONFIG,
354 REG_A6XX_HLSQ_DS_CNTL,
355 REG_A6XX_SP_DS_OBJ_START_LO,
356 },
357 [MESA_SHADER_GEOMETRY] = {
358 REG_A6XX_SP_GS_CTRL_REG0,
359 REG_A6XX_SP_GS_CONFIG,
360 REG_A6XX_HLSQ_GS_CNTL,
361 REG_A6XX_SP_GS_OBJ_START_LO,
362 },
363 [MESA_SHADER_FRAGMENT] = {
364 REG_A6XX_SP_FS_CTRL_REG0,
365 REG_A6XX_SP_FS_CONFIG,
366 REG_A6XX_HLSQ_FS_CNTL,
367 REG_A6XX_SP_FS_OBJ_START_LO,
368 },
369 [MESA_SHADER_COMPUTE] = {
370 REG_A6XX_SP_CS_CTRL_REG0,
371 REG_A6XX_SP_CS_CONFIG,
372 REG_A6XX_HLSQ_CS_CNTL,
373 REG_A6XX_SP_CS_OBJ_START_LO,
374 },
375 };
376 const struct xs_config *cfg = &xs_config[stage];
377
378 if (!xs) {
379 /* shader stage disabled */
380 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 1);
381 tu_cs_emit(cs, 0);
382
383 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
384 tu_cs_emit(cs, 0);
385 return;
386 }
387
388 bool is_fs = xs->type == MESA_SHADER_FRAGMENT;
389 enum a3xx_threadsize threadsize = FOUR_QUADS;
390
391 /* TODO:
392 * the "threadsize" field may have nothing to do with threadsize,
393 * use a value that matches the blob until it is figured out
394 */
395 if (xs->type == MESA_SHADER_GEOMETRY)
396 threadsize = TWO_QUADS;
397
398 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_ctrl, 1);
399 tu_cs_emit(cs,
400 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize) |
401 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs->info.max_reg + 1) |
402 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs->info.max_half_reg + 1) |
403 COND(xs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
404 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs->branchstack) |
405 COND(xs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
406 COND(xs->need_fine_derivatives, A6XX_SP_VS_CTRL_REG0_DIFF_FINE) |
407 /* only fragment shader sets VARYING bit */
408 COND(xs->total_in && is_fs, A6XX_SP_FS_CTRL_REG0_VARYING) |
409 /* unknown bit, seems unnecessary */
410 COND(is_fs, 0x1000000));
411
412 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_config, 2);
413 tu_cs_emit(cs, A6XX_SP_VS_CONFIG_ENABLED |
414 COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
415 COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
416 COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
417 COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
418 A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
419 A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
420 tu_cs_emit(cs, xs->instrlen);
421
422 tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
423 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) |
424 A6XX_HLSQ_VS_CNTL_ENABLED);
425
426 /* emit program binary
427 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
428 */
429
430 assert((binary_iova & 0x7f) == 0);
431
432 tu_cs_emit_pkt4(cs, cfg->reg_sp_vs_obj_start, 2);
433 tu_cs_emit_qw(cs, binary_iova);
434
435 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
436 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
437 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
438 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
439 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
440 CP_LOAD_STATE6_0_NUM_UNIT(xs->instrlen));
441 tu_cs_emit_qw(cs, binary_iova);
442
443 /* emit immediates */
444
445 const struct ir3_const_state *const_state = ir3_const_state(xs);
446 uint32_t base = const_state->offsets.immediate;
447 int size = const_state->immediates_count;
448
449 /* truncate size to avoid writing constants that shader
450 * does not use:
451 */
452 size = MIN2(size + base, xs->constlen) - base;
453
454 if (size <= 0)
455 return;
456
457 tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + size * 4);
458 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
459 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
460 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
461 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage)) |
462 CP_LOAD_STATE6_0_NUM_UNIT(size));
463 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
464 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
465
466 for (unsigned i = 0; i < size; i++) {
467 tu_cs_emit(cs, const_state->immediates[i].val[0]);
468 tu_cs_emit(cs, const_state->immediates[i].val[1]);
469 tu_cs_emit(cs, const_state->immediates[i].val[2]);
470 tu_cs_emit(cs, const_state->immediates[i].val[3]);
471 }
472 }
473
474 static void
475 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
476 const struct ir3_shader_variant *v,
477 uint32_t binary_iova)
478 {
479 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
480 .cs_state = true,
481 .cs_ibo = true));
482
483 tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
484
485 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
486 tu_cs_emit(cs, 0x41);
487
488 uint32_t local_invocation_id =
489 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
490 uint32_t work_group_id =
491 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
492
493 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
494 tu_cs_emit(cs,
495 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
496 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
497 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
498 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
499 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
500 }
501
502 static void
503 tu6_emit_vs_system_values(struct tu_cs *cs,
504 const struct ir3_shader_variant *vs,
505 const struct ir3_shader_variant *hs,
506 const struct ir3_shader_variant *ds,
507 const struct ir3_shader_variant *gs,
508 bool primid_passthru)
509 {
510 const uint32_t vertexid_regid =
511 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
512 const uint32_t instanceid_regid =
513 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
514 const uint32_t tess_coord_x_regid = hs ?
515 ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD) :
516 regid(63, 0);
517 const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ?
518 tess_coord_x_regid + 1 :
519 regid(63, 0);
520 const uint32_t hs_patch_regid = hs ?
521 ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
522 regid(63, 0);
523 const uint32_t ds_patch_regid = hs ?
524 ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
525 regid(63, 0);
526 const uint32_t hs_invocation_regid = hs ?
527 ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) :
528 regid(63, 0);
529 const uint32_t primitiveid_regid = gs ?
530 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
531 regid(63, 0);
532 const uint32_t gsheader_regid = gs ?
533 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
534 regid(63, 0);
535
536 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
537 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
538 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
539 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
540 0xfc000000);
541 tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
542 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
543 tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
544 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
545 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
546 0xfc);
547 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
548 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
549 0xfc00); /* VFD_CONTROL_5 */
550 tu_cs_emit(cs, COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
551 }
552
553 /* Add any missing varyings needed for stream-out. Otherwise varyings not
554 * used by fragment shader will be stripped out.
555 */
556 static void
557 tu6_link_streamout(struct ir3_shader_linkage *l,
558 const struct ir3_shader_variant *v)
559 {
560 const struct ir3_stream_output_info *info = &v->shader->stream_output;
561
562 /*
563 * First, any stream-out varyings not already in linkage map (ie. also
564 * consumed by frag shader) need to be added:
565 */
566 for (unsigned i = 0; i < info->num_outputs; i++) {
567 const struct ir3_stream_output *out = &info->output[i];
568 unsigned compmask =
569 (1 << (out->num_components + out->start_component)) - 1;
570 unsigned k = out->register_index;
571 unsigned idx, nextloc = 0;
572
573 /* psize/pos need to be the last entries in linkage map, and will
574 * get added link_stream_out, so skip over them:
575 */
576 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
577 v->outputs[k].slot == VARYING_SLOT_POS)
578 continue;
579
580 for (idx = 0; idx < l->cnt; idx++) {
581 if (l->var[idx].regid == v->outputs[k].regid)
582 break;
583 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
584 }
585
586 /* add if not already in linkage map: */
587 if (idx == l->cnt)
588 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
589
590 /* expand component-mask if needed, ie streaming out all components
591 * but frag shader doesn't consume all components:
592 */
593 if (compmask & ~l->var[idx].compmask) {
594 l->var[idx].compmask |= compmask;
595 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
596 util_last_bit(l->var[idx].compmask));
597 }
598 }
599 }
600
601 static void
602 tu6_setup_streamout(struct tu_cs *cs,
603 const struct ir3_shader_variant *v,
604 struct ir3_shader_linkage *l)
605 {
606 const struct ir3_stream_output_info *info = &v->shader->stream_output;
607 uint32_t prog[IR3_MAX_SO_OUTPUTS * 2] = {};
608 uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {};
609 uint32_t prog_count = align(l->max_loc, 2) / 2;
610
611 /* TODO: streamout state should be in a non-GMEM draw state */
612
613 /* no streamout: */
614 if (info->num_outputs == 0) {
615 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
616 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
617 tu_cs_emit(cs, 0);
618 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
619 tu_cs_emit(cs, 0);
620 return;
621 }
622
623 /* is there something to do with info->stride[i]? */
624
625 for (unsigned i = 0; i < info->num_outputs; i++) {
626 const struct ir3_stream_output *out = &info->output[i];
627 unsigned k = out->register_index;
628 unsigned idx;
629
630 /* Skip it, if there's an unused reg in the middle of outputs. */
631 if (v->outputs[k].regid == INVALID_REG)
632 continue;
633
634 ncomp[out->output_buffer] += out->num_components;
635
636 /* linkage map sorted by order frag shader wants things, so
637 * a bit less ideal here..
638 */
639 for (idx = 0; idx < l->cnt; idx++)
640 if (l->var[idx].regid == v->outputs[k].regid)
641 break;
642
643 debug_assert(idx < l->cnt);
644
645 for (unsigned j = 0; j < out->num_components; j++) {
646 unsigned c = j + out->start_component;
647 unsigned loc = l->var[idx].loc + c;
648 unsigned off = j + out->dst_offset; /* in dwords */
649
650 if (loc & 1) {
651 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
652 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
653 A6XX_VPC_SO_PROG_B_OFF(off * 4);
654 } else {
655 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
656 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
657 A6XX_VPC_SO_PROG_A_OFF(off * 4);
658 }
659 }
660 }
661
662 tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count);
663 tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
664 tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE |
665 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
666 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
667 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
668 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
669 for (uint32_t i = 0; i < 4; i++) {
670 tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
671 tu_cs_emit(cs, ncomp[i]);
672 }
673 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
674 tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
675 tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
676 for (uint32_t i = 0; i < prog_count; i++) {
677 tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
678 tu_cs_emit(cs, prog[i]);
679 }
680 }
681
682 static void
683 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
684 enum a6xx_state_block block, uint32_t offset,
685 uint32_t size, uint32_t *dwords) {
686 assert(size % 4 == 0);
687
688 tu_cs_emit_pkt7(cs, opcode, 3 + size);
689 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
690 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
691 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
692 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
693 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
694
695 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
696 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
697 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
698
699 tu_cs_emit_array(cs, dwords, size);
700 }
701
702 static void
703 tu6_emit_link_map(struct tu_cs *cs,
704 const struct ir3_shader_variant *producer,
705 const struct ir3_shader_variant *consumer,
706 enum a6xx_state_block sb)
707 {
708 const struct ir3_const_state *const_state = ir3_const_state(consumer);
709 uint32_t base = const_state->offsets.primitive_map;
710 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
711 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
712 int size = DIV_ROUND_UP(num_loc, 4);
713
714 size = (MIN2(size + base, consumer->constlen) - base) * 4;
715 if (size <= 0)
716 return;
717
718 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, sb, 0, size,
719 patch_locs);
720 }
721
722 static uint16_t
723 gl_primitive_to_tess(uint16_t primitive) {
724 switch (primitive) {
725 case GL_POINTS:
726 return TESS_POINTS;
727 case GL_LINE_STRIP:
728 return TESS_LINES;
729 case GL_TRIANGLE_STRIP:
730 return TESS_CW_TRIS;
731 default:
732 unreachable("");
733 }
734 }
735
736 void
737 tu6_emit_vpc(struct tu_cs *cs,
738 const struct ir3_shader_variant *vs,
739 const struct ir3_shader_variant *hs,
740 const struct ir3_shader_variant *ds,
741 const struct ir3_shader_variant *gs,
742 const struct ir3_shader_variant *fs)
743 {
744 /* note: doesn't compile as static because of the array regs.. */
745 const struct reg_config {
746 uint16_t reg_sp_xs_out_reg;
747 uint16_t reg_sp_xs_vpc_dst_reg;
748 uint16_t reg_vpc_xs_pack;
749 uint16_t reg_vpc_xs_clip_cntl;
750 uint16_t reg_gras_xs_cl_cntl;
751 uint16_t reg_pc_xs_out_cntl;
752 uint16_t reg_sp_xs_primitive_cntl;
753 uint16_t reg_vpc_xs_layer_cntl;
754 uint16_t reg_gras_xs_layer_cntl;
755 } reg_config[] = {
756 [MESA_SHADER_VERTEX] = {
757 REG_A6XX_SP_VS_OUT_REG(0),
758 REG_A6XX_SP_VS_VPC_DST_REG(0),
759 REG_A6XX_VPC_VS_PACK,
760 REG_A6XX_VPC_VS_CLIP_CNTL,
761 REG_A6XX_GRAS_VS_CL_CNTL,
762 REG_A6XX_PC_VS_OUT_CNTL,
763 REG_A6XX_SP_VS_PRIMITIVE_CNTL,
764 REG_A6XX_VPC_VS_LAYER_CNTL,
765 REG_A6XX_GRAS_VS_LAYER_CNTL
766 },
767 [MESA_SHADER_TESS_EVAL] = {
768 REG_A6XX_SP_DS_OUT_REG(0),
769 REG_A6XX_SP_DS_VPC_DST_REG(0),
770 REG_A6XX_VPC_DS_PACK,
771 REG_A6XX_VPC_DS_CLIP_CNTL,
772 REG_A6XX_GRAS_DS_CL_CNTL,
773 REG_A6XX_PC_DS_OUT_CNTL,
774 REG_A6XX_SP_DS_PRIMITIVE_CNTL,
775 REG_A6XX_VPC_DS_LAYER_CNTL,
776 REG_A6XX_GRAS_DS_LAYER_CNTL
777 },
778 [MESA_SHADER_GEOMETRY] = {
779 REG_A6XX_SP_GS_OUT_REG(0),
780 REG_A6XX_SP_GS_VPC_DST_REG(0),
781 REG_A6XX_VPC_GS_PACK,
782 REG_A6XX_VPC_GS_CLIP_CNTL,
783 REG_A6XX_GRAS_GS_CL_CNTL,
784 REG_A6XX_PC_GS_OUT_CNTL,
785 REG_A6XX_SP_GS_PRIMITIVE_CNTL,
786 REG_A6XX_VPC_GS_LAYER_CNTL,
787 REG_A6XX_GRAS_GS_LAYER_CNTL
788 },
789 };
790
791 const struct ir3_shader_variant *last_shader;
792 if (gs) {
793 last_shader = gs;
794 } else if (hs) {
795 last_shader = ds;
796 } else {
797 last_shader = vs;
798 }
799
800 const struct reg_config *cfg = &reg_config[last_shader->type];
801
802 struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
803 if (fs)
804 ir3_link_shaders(&linkage, last_shader, fs, true);
805
806 if (last_shader->shader->stream_output.num_outputs)
807 tu6_link_streamout(&linkage, last_shader);
808
809 /* We do this after linking shaders in order to know whether PrimID
810 * passthrough needs to be enabled.
811 */
812 bool primid_passthru = linkage.primid_loc != 0xff;
813 tu6_emit_vs_system_values(cs, vs, hs, ds, gs, primid_passthru);
814
815 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
816 tu_cs_emit(cs, ~linkage.varmask[0]);
817 tu_cs_emit(cs, ~linkage.varmask[1]);
818 tu_cs_emit(cs, ~linkage.varmask[2]);
819 tu_cs_emit(cs, ~linkage.varmask[3]);
820
821 /* a6xx finds position/pointsize at the end */
822 const uint32_t position_regid =
823 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
824 const uint32_t pointsize_regid =
825 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
826 const uint32_t layer_regid =
827 ir3_find_output_regid(last_shader, VARYING_SLOT_LAYER);
828 uint32_t primitive_regid = gs ?
829 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) : regid(63, 0);
830 uint32_t flags_regid = gs ?
831 ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3) : 0;
832
833 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
834 if (layer_regid != regid(63, 0)) {
835 layer_loc = linkage.max_loc;
836 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
837 }
838 if (position_regid != regid(63, 0)) {
839 position_loc = linkage.max_loc;
840 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
841 }
842 if (pointsize_regid != regid(63, 0)) {
843 pointsize_loc = linkage.max_loc;
844 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
845 }
846
847 tu6_setup_streamout(cs, last_shader, &linkage);
848
849 /* map outputs of the last shader to VPC */
850 assert(linkage.cnt <= 32);
851 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
852 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
853 uint32_t sp_out[16];
854 uint32_t sp_vpc_dst[8];
855 for (uint32_t i = 0; i < linkage.cnt; i++) {
856 ((uint16_t *) sp_out)[i] =
857 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
858 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
859 ((uint8_t *) sp_vpc_dst)[i] =
860 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
861 }
862
863 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_out_reg, sp_out_count);
864 tu_cs_emit_array(cs, sp_out, sp_out_count);
865
866 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_vpc_dst_reg, sp_vpc_dst_count);
867 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
868
869 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_pack, 1);
870 tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
871 A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) |
872 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc));
873
874 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_clip_cntl, 1);
875 tu_cs_emit(cs, 0xffff00);
876
877 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_cl_cntl, 1);
878 tu_cs_emit(cs, 0);
879
880 tu_cs_emit_pkt4(cs, cfg->reg_pc_xs_out_cntl, 1);
881 tu_cs_emit(cs, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
882 CONDREG(pointsize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
883 CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
884 CONDREG(primitive_regid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID));
885
886 tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_primitive_cntl, 1);
887 tu_cs_emit(cs, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt) |
888 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
889
890 tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_layer_cntl, 1);
891 tu_cs_emit(cs, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
892
893 tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_layer_cntl, 1);
894 tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
895
896 tu_cs_emit_regs(cs, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
897
898 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
899 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
900 COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
901 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
902 A6XX_VPC_CNTL_0_UNKLOC(0xff));
903
904 if (hs) {
905 shader_info *hs_info = &hs->shader->nir->info;
906 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
907 tu_cs_emit(cs, hs_info->tess.tcs_vertices_out);
908
909 /* Total attribute slots in HS incoming patch. */
910 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9801, 1);
911 tu_cs_emit(cs,
912 hs_info->tess.tcs_vertices_out * vs->output_size / 4);
913
914 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
915 tu_cs_emit(cs, vs->output_size);
916 /* In SPIR-V generated from GLSL, the tessellation primitive params are
917 * are specified in the tess eval shader, but in SPIR-V generated from
918 * HLSL, they are specified in the tess control shader. */
919 shader_info *tess_info =
920 ds->shader->nir->info.tess.spacing == TESS_SPACING_UNSPECIFIED ?
921 &hs->shader->nir->info : &ds->shader->nir->info;
922 tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_CNTL, 1);
923 uint32_t output;
924 if (tess_info->tess.point_mode)
925 output = TESS_POINTS;
926 else if (tess_info->tess.primitive_mode == GL_ISOLINES)
927 output = TESS_LINES;
928 else if (tess_info->tess.ccw)
929 output = TESS_CCW_TRIS;
930 else
931 output = TESS_CW_TRIS;
932
933 enum a6xx_tess_spacing spacing;
934 switch (tess_info->tess.spacing) {
935 case TESS_SPACING_EQUAL:
936 spacing = TESS_EQUAL;
937 break;
938 case TESS_SPACING_FRACTIONAL_ODD:
939 spacing = TESS_FRACTIONAL_ODD;
940 break;
941 case TESS_SPACING_FRACTIONAL_EVEN:
942 spacing = TESS_FRACTIONAL_EVEN;
943 break;
944 case TESS_SPACING_UNSPECIFIED:
945 default:
946 unreachable("invalid tess spacing");
947 }
948 tu_cs_emit(cs, A6XX_PC_TESS_CNTL_SPACING(spacing) |
949 A6XX_PC_TESS_CNTL_OUTPUT(output));
950
951 tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
952 tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER);
953 }
954
955
956 if (gs) {
957 uint32_t vertices_out, invocations, output, vec4_size;
958 /* this detects the tu_clear_blit path, which doesn't set ->nir */
959 if (gs->shader->nir) {
960 if (hs) {
961 tu6_emit_link_map(cs, ds, gs, SB6_GS_SHADER);
962 } else {
963 tu6_emit_link_map(cs, vs, gs, SB6_GS_SHADER);
964 }
965 vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
966 output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
967 invocations = gs->shader->nir->info.gs.invocations - 1;
968 /* Size of per-primitive alloction in ldlw memory in vec4s. */
969 vec4_size = gs->shader->nir->info.gs.vertices_in *
970 DIV_ROUND_UP(vs->output_size, 4);
971 } else {
972 vertices_out = 3;
973 output = TESS_CW_TRIS;
974 invocations = 0;
975 vec4_size = 0;
976 }
977
978 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
979 tu_cs_emit(cs,
980 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
981 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
982 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
983
984 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
985 tu_cs_emit(cs, 0);
986
987 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
988 tu_cs_emit(cs, 0xff);
989
990 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
991 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
992
993 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
994 tu_cs_emit(cs, 0);
995
996 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
997 tu_cs_emit(cs, vs->output_size);
998 }
999 }
1000
1001 static int
1002 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1003 uint32_t index,
1004 uint8_t *interp_mode,
1005 uint8_t *ps_repl_mode)
1006 {
1007 enum
1008 {
1009 INTERP_SMOOTH = 0,
1010 INTERP_FLAT = 1,
1011 INTERP_ZERO = 2,
1012 INTERP_ONE = 3,
1013 };
1014 enum
1015 {
1016 PS_REPL_NONE = 0,
1017 PS_REPL_S = 1,
1018 PS_REPL_T = 2,
1019 PS_REPL_ONE_MINUS_T = 3,
1020 };
1021
1022 const uint32_t compmask = fs->inputs[index].compmask;
1023
1024 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1025 * fourth component occupy three consecutive varying slots
1026 */
1027 int shift = 0;
1028 *interp_mode = 0;
1029 *ps_repl_mode = 0;
1030 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1031 if (compmask & 0x1) {
1032 *ps_repl_mode |= PS_REPL_S << shift;
1033 shift += 2;
1034 }
1035 if (compmask & 0x2) {
1036 *ps_repl_mode |= PS_REPL_T << shift;
1037 shift += 2;
1038 }
1039 if (compmask & 0x4) {
1040 *interp_mode |= INTERP_ZERO << shift;
1041 shift += 2;
1042 }
1043 if (compmask & 0x8) {
1044 *interp_mode |= INTERP_ONE << 6;
1045 shift += 2;
1046 }
1047 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1048 fs->inputs[index].rasterflat) {
1049 for (int i = 0; i < 4; i++) {
1050 if (compmask & (1 << i)) {
1051 *interp_mode |= INTERP_FLAT << shift;
1052 shift += 2;
1053 }
1054 }
1055 }
1056
1057 return shift;
1058 }
1059
1060 static void
1061 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1062 const struct ir3_shader_variant *fs)
1063 {
1064 uint32_t interp_modes[8] = { 0 };
1065 uint32_t ps_repl_modes[8] = { 0 };
1066
1067 if (fs) {
1068 for (int i = -1;
1069 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1070
1071 /* get the mode for input i */
1072 uint8_t interp_mode;
1073 uint8_t ps_repl_mode;
1074 const int bits =
1075 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1076
1077 /* OR the mode into the array */
1078 const uint32_t inloc = fs->inputs[i].inloc * 2;
1079 uint32_t n = inloc / 32;
1080 uint32_t shift = inloc % 32;
1081 interp_modes[n] |= interp_mode << shift;
1082 ps_repl_modes[n] |= ps_repl_mode << shift;
1083 if (shift + bits > 32) {
1084 n++;
1085 shift = 32 - shift;
1086
1087 interp_modes[n] |= interp_mode >> shift;
1088 ps_repl_modes[n] |= ps_repl_mode >> shift;
1089 }
1090 }
1091 }
1092
1093 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1094 tu_cs_emit_array(cs, interp_modes, 8);
1095
1096 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1097 tu_cs_emit_array(cs, ps_repl_modes, 8);
1098 }
1099
1100 void
1101 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1102 {
1103 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1104 uint32_t ij_regid[IJ_COUNT];
1105 uint32_t smask_in_regid;
1106
1107 bool sample_shading = fs->per_samp | fs->key.sample_shading;
1108 bool enable_varyings = fs->total_in > 0;
1109
1110 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1111 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1112 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1113 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1114 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1115 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
1116 ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
1117
1118 if (VALIDREG(ij_regid[IJ_LINEAR_SAMPLE]))
1119 tu_finishme("linear sample varying");
1120
1121 if (VALIDREG(ij_regid[IJ_LINEAR_CENTROID]))
1122 tu_finishme("linear centroid varying");
1123
1124 if (fs->num_sampler_prefetch > 0) {
1125 assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
1126 /* also, it seems like ij_pix is *required* to be r0.x */
1127 assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
1128 }
1129
1130 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1131 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1132 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1133 0x7000); // XXX);
1134 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1135 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1136 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1137 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1138 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1139 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1140 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1141 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1142 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1143 }
1144
1145 if (fs->num_sampler_prefetch > 0) {
1146 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1147 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1148 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1149 tu_cs_emit(cs,
1150 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1151 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1152 }
1153 }
1154
1155 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1156 tu_cs_emit(cs, 0x7);
1157 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1158 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1159 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1160 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
1161 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
1162 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
1163 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
1164 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
1165 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1166 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1167 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
1168 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
1169 tu_cs_emit(cs, 0xfc);
1170
1171 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1172 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1173
1174 bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
1175 bool need_size_persamp = false;
1176 if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
1177 if (sample_shading)
1178 need_size_persamp = true;
1179 else
1180 need_size = true;
1181 }
1182 if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
1183 need_size = true;
1184
1185 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1186 tu_cs_emit(cs,
1187 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
1188 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
1189 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
1190 COND(need_size, A6XX_GRAS_CNTL_SIZE) |
1191 COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1192 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
1193
1194 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1195 tu_cs_emit(cs,
1196 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
1197 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
1198 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
1199 COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
1200 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1201 COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1202 COND(fs->fragcoord_compmask != 0,
1203 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
1204 tu_cs_emit(cs,
1205 /* these two bits (UNK4/UNK5) relate to fragcoord
1206 * without them, fragcoord is the same for all samples
1207 */
1208 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) |
1209 COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) |
1210 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1211 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1212 CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
1213 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1214
1215 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1216 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1217
1218 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1219 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1220
1221 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1222 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1223 }
1224
1225 static void
1226 tu6_emit_fs_outputs(struct tu_cs *cs,
1227 const struct ir3_shader_variant *fs,
1228 uint32_t mrt_count, bool dual_src_blend,
1229 uint32_t render_components,
1230 bool is_s8_uint)
1231 {
1232 uint32_t smask_regid, posz_regid;
1233
1234 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1235 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1236
1237 uint32_t fragdata_regid[8];
1238 if (fs->color0_mrt) {
1239 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1240 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1241 fragdata_regid[i] = fragdata_regid[0];
1242 } else {
1243 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1244 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1245 }
1246
1247 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1248 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1249 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1250 COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
1251 0xfc000000);
1252 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1253
1254 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1255 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1256 // TODO we could have a mix of half and full precision outputs,
1257 // we really need to figure out half-precision from IR3_REG_HALF
1258 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1259 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1260 }
1261
1262 tu_cs_emit_regs(cs,
1263 A6XX_SP_FS_RENDER_COMPONENTS(.dword = render_components));
1264
1265 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1266 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1267 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
1268 COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
1269 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1270
1271 tu_cs_emit_regs(cs,
1272 A6XX_RB_RENDER_COMPONENTS(.dword = render_components));
1273
1274 enum a6xx_ztest_mode zmode;
1275
1276 if (fs->no_earlyz || fs->has_kill || fs->writes_pos || is_s8_uint) {
1277 zmode = A6XX_LATE_Z;
1278 } else {
1279 zmode = A6XX_EARLY_Z;
1280 }
1281
1282 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1283 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1284
1285 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1286 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
1287 }
1288
1289 static void
1290 tu6_emit_geom_tess_consts(struct tu_cs *cs,
1291 const struct ir3_shader_variant *vs,
1292 const struct ir3_shader_variant *hs,
1293 const struct ir3_shader_variant *ds,
1294 const struct ir3_shader_variant *gs,
1295 uint32_t cps_per_patch)
1296 {
1297 uint32_t num_vertices =
1298 hs ? cps_per_patch : gs->shader->nir->info.gs.vertices_in;
1299
1300 uint32_t vs_params[4] = {
1301 vs->output_size * num_vertices * 4, /* vs primitive stride */
1302 vs->output_size * 4, /* vs vertex stride */
1303 0,
1304 0,
1305 };
1306 uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param;
1307 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1308 ARRAY_SIZE(vs_params), vs_params);
1309
1310 if (hs) {
1311 assert(ds->type != MESA_SHADER_NONE);
1312 uint32_t hs_params[4] = {
1313 vs->output_size * num_vertices * 4, /* hs primitive stride */
1314 vs->output_size * 4, /* hs vertex stride */
1315 hs->output_size,
1316 cps_per_patch,
1317 };
1318
1319 uint32_t hs_base = hs->const_state->offsets.primitive_param;
1320 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, hs_base, SB6_HS_SHADER, 0,
1321 ARRAY_SIZE(hs_params), hs_params);
1322 if (gs)
1323 num_vertices = gs->shader->nir->info.gs.vertices_in;
1324
1325 uint32_t ds_params[4] = {
1326 ds->output_size * num_vertices * 4, /* ds primitive stride */
1327 ds->output_size * 4, /* ds vertex stride */
1328 hs->output_size, /* hs vertex stride (dwords) */
1329 hs->shader->nir->info.tess.tcs_vertices_out
1330 };
1331
1332 uint32_t ds_base = ds->const_state->offsets.primitive_param;
1333 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, ds_base, SB6_DS_SHADER, 0,
1334 ARRAY_SIZE(ds_params), ds_params);
1335 }
1336
1337 if (gs) {
1338 const struct ir3_shader_variant *prev = ds ? ds : vs;
1339 uint32_t gs_params[4] = {
1340 prev->output_size * num_vertices * 4, /* gs primitive stride */
1341 prev->output_size * 4, /* gs vertex stride */
1342 0,
1343 0,
1344 };
1345 uint32_t gs_base = gs->const_state->offsets.primitive_param;
1346 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1347 ARRAY_SIZE(gs_params), gs_params);
1348 }
1349 }
1350
1351 static void
1352 tu6_emit_program(struct tu_cs *cs,
1353 struct tu_pipeline_builder *builder,
1354 bool binning_pass)
1355 {
1356 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
1357 const struct ir3_shader_variant *bs = builder->binning_variant;
1358 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
1359 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
1360 const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
1361 const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
1362 gl_shader_stage stage = MESA_SHADER_VERTEX;
1363
1364 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
1365
1366 tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
1367 .vs_state = true,
1368 .hs_state = true,
1369 .ds_state = true,
1370 .gs_state = true,
1371 .fs_state = true,
1372 .gfx_ibo = true));
1373
1374 /* Don't use the binning pass variant when GS is present because we don't
1375 * support compiling correct binning pass variants with GS.
1376 */
1377 if (binning_pass && !gs) {
1378 vs = bs;
1379 tu6_emit_xs_config(cs, stage, bs, builder->binning_vs_iova);
1380 stage++;
1381 }
1382
1383 for (; stage < ARRAY_SIZE(builder->shaders); stage++) {
1384 const struct ir3_shader_variant *xs = builder->variants[stage];
1385
1386 if (stage == MESA_SHADER_FRAGMENT && binning_pass)
1387 fs = xs = NULL;
1388
1389 tu6_emit_xs_config(cs, stage, xs, builder->shader_iova[stage]);
1390 }
1391
1392 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
1393 tu_cs_emit(cs, 0);
1394
1395 tu6_emit_vpc(cs, vs, hs, ds, gs, fs);
1396 tu6_emit_vpc_varying_modes(cs, fs);
1397
1398 if (fs) {
1399 tu6_emit_fs_inputs(cs, fs);
1400 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
1401 builder->use_dual_src_blend,
1402 builder->render_components,
1403 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1404 } else {
1405 /* TODO: check if these can be skipped if fs is disabled */
1406 struct ir3_shader_variant dummy_variant = {};
1407 tu6_emit_fs_inputs(cs, &dummy_variant);
1408 tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
1409 builder->use_dual_src_blend,
1410 builder->render_components,
1411 builder->depth_attachment_format == VK_FORMAT_S8_UINT);
1412 }
1413
1414 if (gs || hs) {
1415 uint32_t cps_per_patch = builder->create_info->pTessellationState ?
1416 builder->create_info->pTessellationState->patchControlPoints : 0;
1417 tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch);
1418 }
1419 }
1420
1421 static void
1422 tu6_emit_vertex_input(struct tu_cs *cs,
1423 const struct ir3_shader_variant *vs,
1424 const VkPipelineVertexInputStateCreateInfo *info,
1425 uint32_t *bindings_used)
1426 {
1427 uint32_t vfd_decode_idx = 0;
1428 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1429 uint32_t step_rate[MAX_VBS];
1430
1431 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1432 const VkVertexInputBindingDescription *binding =
1433 &info->pVertexBindingDescriptions[i];
1434
1435 tu_cs_emit_regs(cs,
1436 A6XX_VFD_FETCH_STRIDE(binding->binding, binding->stride));
1437
1438 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1439 binding_instanced |= 1 << binding->binding;
1440
1441 *bindings_used |= 1 << binding->binding;
1442 step_rate[binding->binding] = 1;
1443 }
1444
1445 const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_state =
1446 vk_find_struct_const(info->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
1447 if (div_state) {
1448 for (uint32_t i = 0; i < div_state->vertexBindingDivisorCount; i++) {
1449 const VkVertexInputBindingDivisorDescriptionEXT *desc =
1450 &div_state->pVertexBindingDivisors[i];
1451 step_rate[desc->binding] = desc->divisor;
1452 }
1453 }
1454
1455 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1456
1457 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1458 const VkVertexInputAttributeDescription *attr =
1459 &info->pVertexAttributeDescriptions[i];
1460 uint32_t input_idx;
1461
1462 assert(*bindings_used & BIT(attr->binding));
1463
1464 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1465 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1466 break;
1467 }
1468
1469 /* attribute not used, skip it */
1470 if (input_idx == vs->inputs_count)
1471 continue;
1472
1473 const struct tu_native_format format = tu6_format_vtx(attr->format);
1474 tu_cs_emit_regs(cs,
1475 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1476 .idx = attr->binding,
1477 .offset = attr->offset,
1478 .instanced = binding_instanced & (1 << attr->binding),
1479 .format = format.fmt,
1480 .swap = format.swap,
1481 .unk30 = 1,
1482 ._float = !vk_format_is_int(attr->format)),
1483 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, step_rate[attr->binding]));
1484
1485 tu_cs_emit_regs(cs,
1486 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1487 .writemask = vs->inputs[input_idx].compmask,
1488 .regid = vs->inputs[input_idx].regid));
1489
1490 vfd_decode_idx++;
1491 }
1492
1493 tu_cs_emit_regs(cs,
1494 A6XX_VFD_CONTROL_0(
1495 .fetch_cnt = vfd_decode_idx, /* decode_cnt for binning pass ? */
1496 .decode_cnt = vfd_decode_idx));
1497 }
1498
1499 static uint32_t
1500 tu6_guardband_adj(uint32_t v)
1501 {
1502 if (v > 256)
1503 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1504 else
1505 return 511;
1506 }
1507
1508 void
1509 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1510 {
1511 float offsets[3];
1512 float scales[3];
1513 scales[0] = viewport->width / 2.0f;
1514 scales[1] = viewport->height / 2.0f;
1515 scales[2] = viewport->maxDepth - viewport->minDepth;
1516 offsets[0] = viewport->x + scales[0];
1517 offsets[1] = viewport->y + scales[1];
1518 offsets[2] = viewport->minDepth;
1519
1520 VkOffset2D min;
1521 VkOffset2D max;
1522 min.x = (int32_t) viewport->x;
1523 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1524 if (viewport->height >= 0.0f) {
1525 min.y = (int32_t) viewport->y;
1526 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1527 } else {
1528 min.y = (int32_t)(viewport->y + viewport->height);
1529 max.y = (int32_t) ceilf(viewport->y);
1530 }
1531 /* the spec allows viewport->height to be 0.0f */
1532 if (min.y == max.y)
1533 max.y++;
1534 assert(min.x >= 0 && min.x < max.x);
1535 assert(min.y >= 0 && min.y < max.y);
1536
1537 VkExtent2D guardband_adj;
1538 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1539 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1540
1541 tu_cs_emit_regs(cs,
1542 A6XX_GRAS_CL_VPORT_XOFFSET(0, offsets[0]),
1543 A6XX_GRAS_CL_VPORT_XSCALE(0, scales[0]),
1544 A6XX_GRAS_CL_VPORT_YOFFSET(0, offsets[1]),
1545 A6XX_GRAS_CL_VPORT_YSCALE(0, scales[1]),
1546 A6XX_GRAS_CL_VPORT_ZOFFSET(0, offsets[2]),
1547 A6XX_GRAS_CL_VPORT_ZSCALE(0, scales[2]));
1548
1549 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(0), 2);
1550 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(min.x) |
1551 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(min.y));
1552 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(max.x - 1) |
1553 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(max.y - 1));
1554
1555 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1556 tu_cs_emit(cs,
1557 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1558 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1559
1560 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1561 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1562
1563 tu_cs_emit_regs(cs,
1564 A6XX_GRAS_CL_Z_CLAMP_MIN(0, z_clamp_min),
1565 A6XX_GRAS_CL_Z_CLAMP_MAX(0, z_clamp_max));
1566
1567 tu_cs_emit_regs(cs,
1568 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1569 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1570 }
1571
1572 void
1573 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1574 {
1575 VkOffset2D min = scissor->offset;
1576 VkOffset2D max = {
1577 scissor->offset.x + scissor->extent.width,
1578 scissor->offset.y + scissor->extent.height,
1579 };
1580
1581 /* special case for empty scissor with max == 0 to avoid overflow */
1582 if (max.x == 0)
1583 min.x = max.x = 1;
1584 if (max.y == 0)
1585 min.y = max.y = 1;
1586
1587 /* avoid overflow with large scissor
1588 * note the max will be limited to min - 1, so that empty scissor works
1589 */
1590 uint32_t scissor_max = BITFIELD_MASK(15);
1591 min.x = MIN2(scissor_max, min.x);
1592 min.y = MIN2(scissor_max, min.y);
1593 max.x = MIN2(scissor_max, max.x);
1594 max.y = MIN2(scissor_max, max.y);
1595
1596 tu_cs_emit_regs(cs,
1597 A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0, .x = min.x, .y = min.y),
1598 A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0, .x = max.x - 1, .y = max.y - 1));
1599 }
1600
1601 void
1602 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1603 {
1604 if (!samp_loc) {
1605 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1606 tu_cs_emit(cs, 0);
1607
1608 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1609 tu_cs_emit(cs, 0);
1610
1611 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1612 tu_cs_emit(cs, 0);
1613 return;
1614 }
1615
1616 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1617 assert(samp_loc->sampleLocationGridSize.width == 1);
1618 assert(samp_loc->sampleLocationGridSize.height == 1);
1619
1620 uint32_t sample_config =
1621 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1622 uint32_t sample_locations = 0;
1623 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1624 sample_locations |=
1625 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1626 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1627 }
1628
1629 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1630 tu_cs_emit(cs, sample_config);
1631 tu_cs_emit(cs, sample_locations);
1632
1633 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1634 tu_cs_emit(cs, sample_config);
1635 tu_cs_emit(cs, sample_locations);
1636
1637 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1638 tu_cs_emit(cs, sample_config);
1639 tu_cs_emit(cs, sample_locations);
1640 }
1641
1642 static uint32_t
1643 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1644 VkSampleCountFlagBits samples)
1645 {
1646 uint32_t gras_su_cntl = 0;
1647
1648 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1649 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1650 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1651 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1652
1653 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1654 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1655
1656 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1657
1658 if (rast_info->depthBiasEnable)
1659 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1660
1661 if (samples > VK_SAMPLE_COUNT_1_BIT)
1662 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1663
1664 return gras_su_cntl;
1665 }
1666
1667 void
1668 tu6_emit_depth_bias(struct tu_cs *cs,
1669 float constant_factor,
1670 float clamp,
1671 float slope_factor)
1672 {
1673 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1674 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1675 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1676 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1677 }
1678
1679 static void
1680 tu6_emit_depth_control(struct tu_cs *cs,
1681 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1682 const VkPipelineRasterizationStateCreateInfo *rast_info)
1683 {
1684 uint32_t rb_depth_cntl = 0;
1685 if (ds_info->depthTestEnable) {
1686 rb_depth_cntl |=
1687 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1688 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1689 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
1690
1691 if (rast_info->depthClampEnable)
1692 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1693
1694 if (ds_info->depthWriteEnable)
1695 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1696 }
1697
1698 if (ds_info->depthBoundsTestEnable)
1699 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1700
1701 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1702 tu_cs_emit(cs, rb_depth_cntl);
1703 }
1704
1705 static void
1706 tu6_emit_stencil_control(struct tu_cs *cs,
1707 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1708 {
1709 uint32_t rb_stencil_control = 0;
1710 if (ds_info->stencilTestEnable) {
1711 const VkStencilOpState *front = &ds_info->front;
1712 const VkStencilOpState *back = &ds_info->back;
1713 rb_stencil_control |=
1714 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1715 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1716 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1717 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1718 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1719 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1720 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1721 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1722 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1723 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1724 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1725 }
1726
1727 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1728 tu_cs_emit(cs, rb_stencil_control);
1729 }
1730
1731 static uint32_t
1732 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1733 bool has_alpha)
1734 {
1735 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1736 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1737 has_alpha ? att->srcColorBlendFactor
1738 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1739 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1740 has_alpha ? att->dstColorBlendFactor
1741 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1742 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1743 const enum adreno_rb_blend_factor src_alpha_factor =
1744 tu6_blend_factor(att->srcAlphaBlendFactor);
1745 const enum adreno_rb_blend_factor dst_alpha_factor =
1746 tu6_blend_factor(att->dstAlphaBlendFactor);
1747
1748 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1749 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1750 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1751 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1752 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1753 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1754 }
1755
1756 static uint32_t
1757 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1758 uint32_t rb_mrt_control_rop,
1759 bool is_int,
1760 bool has_alpha)
1761 {
1762 uint32_t rb_mrt_control =
1763 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1764
1765 /* ignore blending and logic op for integer attachments */
1766 if (is_int) {
1767 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1768 return rb_mrt_control;
1769 }
1770
1771 rb_mrt_control |= rb_mrt_control_rop;
1772
1773 if (att->blendEnable) {
1774 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1775
1776 if (has_alpha)
1777 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1778 }
1779
1780 return rb_mrt_control;
1781 }
1782
1783 static void
1784 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1785 const VkPipelineColorBlendStateCreateInfo *blend_info,
1786 const VkFormat attachment_formats[MAX_RTS],
1787 uint32_t *blend_enable_mask)
1788 {
1789 *blend_enable_mask = 0;
1790
1791 bool rop_reads_dst = false;
1792 uint32_t rb_mrt_control_rop = 0;
1793 if (blend_info->logicOpEnable) {
1794 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1795 rb_mrt_control_rop =
1796 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1797 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1798 }
1799
1800 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1801 const VkPipelineColorBlendAttachmentState *att =
1802 &blend_info->pAttachments[i];
1803 const VkFormat format = attachment_formats[i];
1804
1805 uint32_t rb_mrt_control = 0;
1806 uint32_t rb_mrt_blend_control = 0;
1807 if (format != VK_FORMAT_UNDEFINED) {
1808 const bool is_int = vk_format_is_int(format);
1809 const bool has_alpha = vk_format_has_alpha(format);
1810
1811 rb_mrt_control =
1812 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1813 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1814
1815 if (att->blendEnable || rop_reads_dst)
1816 *blend_enable_mask |= 1 << i;
1817 }
1818
1819 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1820 tu_cs_emit(cs, rb_mrt_control);
1821 tu_cs_emit(cs, rb_mrt_blend_control);
1822 }
1823 }
1824
1825 static void
1826 tu6_emit_blend_control(struct tu_cs *cs,
1827 uint32_t blend_enable_mask,
1828 bool dual_src_blend,
1829 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1830 {
1831 const uint32_t sample_mask =
1832 msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
1833 : ((1 << msaa_info->rasterizationSamples) - 1);
1834
1835 tu_cs_emit_regs(cs,
1836 A6XX_SP_BLEND_CNTL(.enabled = blend_enable_mask,
1837 .dual_color_in_enable = dual_src_blend,
1838 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1839 .unk8 = true));
1840
1841 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1842 tu_cs_emit_regs(cs,
1843 A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
1844 .independent_blend = true,
1845 .sample_mask = sample_mask,
1846 .dual_color_in_enable = dual_src_blend,
1847 .alpha_to_coverage = msaa_info->alphaToCoverageEnable,
1848 .alpha_to_one = msaa_info->alphaToOneEnable));
1849 }
1850
1851 static VkResult
1852 tu_pipeline_allocate_cs(struct tu_device *dev,
1853 struct tu_pipeline *pipeline,
1854 struct tu_pipeline_builder *builder,
1855 struct ir3_shader_variant *compute)
1856 {
1857 uint32_t size = 2048 + tu6_load_state_size(pipeline, compute);
1858
1859 /* graphics case: */
1860 if (builder) {
1861 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1862 if (builder->variants[i])
1863 size += builder->variants[i]->info.sizedwords;
1864 }
1865
1866 size += builder->binning_variant->info.sizedwords;
1867 } else {
1868 size += compute->info.sizedwords;
1869 }
1870
1871 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, size);
1872
1873 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1874 * that LOAD_STATE can potentially take up a large amount of space so we
1875 * calculate its size explicitly.
1876 */
1877 return tu_cs_reserve_space(&pipeline->cs, size);
1878 }
1879
1880 static void
1881 tu_pipeline_shader_key_init(struct ir3_shader_key *key,
1882 const VkGraphicsPipelineCreateInfo *pipeline_info)
1883 {
1884 for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
1885 if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
1886 key->has_gs = true;
1887 break;
1888 }
1889 }
1890
1891 if (pipeline_info->pRasterizationState->rasterizerDiscardEnable)
1892 return;
1893
1894 const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
1895 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
1896 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1897 if (msaa_info->rasterizationSamples > 1 ||
1898 /* also set msaa key when sample location is not the default
1899 * since this affects varying interpolation */
1900 (sample_locations && sample_locations->sampleLocationsEnable)) {
1901 key->msaa = true;
1902 }
1903
1904 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1905 if (msaa_info->sampleShadingEnable)
1906 key->sample_shading = true;
1907
1908 /* We set this after we compile to NIR because we need the prim mode */
1909 key->tessellation = IR3_TESS_NONE;
1910 }
1911
1912 static uint32_t
1913 tu6_get_tessmode(struct tu_shader* shader)
1914 {
1915 uint32_t primitive_mode = shader->ir3_shader->nir->info.tess.primitive_mode;
1916 switch (primitive_mode) {
1917 case GL_ISOLINES:
1918 return IR3_TESS_ISOLINES;
1919 case GL_TRIANGLES:
1920 return IR3_TESS_TRIANGLES;
1921 case GL_QUADS:
1922 return IR3_TESS_QUADS;
1923 case GL_NONE:
1924 return IR3_TESS_NONE;
1925 default:
1926 unreachable("bad tessmode");
1927 }
1928 }
1929
1930 static uint64_t
1931 tu_upload_variant(struct tu_pipeline *pipeline,
1932 const struct ir3_shader_variant *variant)
1933 {
1934 struct tu_cs_memory memory;
1935
1936 if (!variant)
1937 return 0;
1938
1939 /* this expects to get enough alignment because shaders are allocated first
1940 * and sizedwords is always aligned correctly
1941 * note: an assert in tu6_emit_xs_config validates the alignment
1942 */
1943 tu_cs_alloc(&pipeline->cs, variant->info.sizedwords, 1, &memory);
1944
1945 memcpy(memory.map, variant->bin, sizeof(uint32_t) * variant->info.sizedwords);
1946 return memory.iova;
1947 }
1948
1949 static VkResult
1950 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
1951 struct tu_pipeline *pipeline)
1952 {
1953 const struct ir3_compiler *compiler = builder->device->compiler;
1954 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1955 NULL
1956 };
1957 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1958 gl_shader_stage stage =
1959 vk_to_mesa_shader_stage(builder->create_info->pStages[i].stage);
1960 stage_infos[stage] = &builder->create_info->pStages[i];
1961 }
1962
1963 struct ir3_shader_key key = {};
1964 tu_pipeline_shader_key_init(&key, builder->create_info);
1965
1966 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1967 stage < MESA_SHADER_STAGES; stage++) {
1968 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1969 if (!stage_info && stage != MESA_SHADER_FRAGMENT)
1970 continue;
1971
1972 struct tu_shader *shader =
1973 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1974 builder->alloc);
1975 if (!shader)
1976 return VK_ERROR_OUT_OF_HOST_MEMORY;
1977
1978 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
1979 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
1980 * the mode is specified in the tessellation control shader. */
1981 if ((stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_TESS_CTRL) &&
1982 key.tessellation == IR3_TESS_NONE) {
1983 key.tessellation = tu6_get_tessmode(shader);
1984 }
1985
1986 builder->shaders[stage] = shader;
1987 }
1988
1989 struct tu_shader *gs = builder->shaders[MESA_SHADER_GEOMETRY];
1990 key.layer_zero =
1991 !gs || !(gs->ir3_shader->nir->info.outputs_written & VARYING_SLOT_LAYER);
1992
1993 pipeline->tess.patch_type = key.tessellation;
1994
1995 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
1996 stage < MESA_SHADER_STAGES; stage++) {
1997 if (!builder->shaders[stage])
1998 continue;
1999
2000 bool created;
2001 builder->variants[stage] =
2002 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2003 &key, false, &created);
2004 if (!builder->variants[stage])
2005 return VK_ERROR_OUT_OF_HOST_MEMORY;
2006 }
2007
2008 uint32_t safe_constlens = ir3_trim_constlen(builder->variants, compiler);
2009
2010 key.safe_constlen = true;
2011
2012 for (gl_shader_stage stage = MESA_SHADER_VERTEX;
2013 stage < MESA_SHADER_STAGES; stage++) {
2014 if (!builder->shaders[stage])
2015 continue;
2016
2017 if (safe_constlens & (1 << stage)) {
2018 bool created;
2019 builder->variants[stage] =
2020 ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
2021 &key, false, &created);
2022 if (!builder->variants[stage])
2023 return VK_ERROR_OUT_OF_HOST_MEMORY;
2024 }
2025 }
2026
2027 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2028 struct ir3_shader_variant *variant;
2029
2030 if (vs->ir3_shader->stream_output.num_outputs ||
2031 !ir3_has_binning_vs(&key)) {
2032 variant = builder->variants[MESA_SHADER_VERTEX];
2033 } else {
2034 bool created;
2035 key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX));
2036 variant = ir3_shader_get_variant(vs->ir3_shader, &key,
2037 true, &created);
2038 if (!variant)
2039 return VK_ERROR_OUT_OF_HOST_MEMORY;
2040 }
2041
2042 builder->binning_variant = variant;
2043
2044 return VK_SUCCESS;
2045 }
2046
2047 static void
2048 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2049 struct tu_pipeline *pipeline)
2050 {
2051 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2052 builder->create_info->pDynamicState;
2053
2054 if (!dynamic_info)
2055 return;
2056
2057 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2058 VkDynamicState state = dynamic_info->pDynamicStates[i];
2059 switch (state) {
2060 case VK_DYNAMIC_STATE_VIEWPORT ... VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2061 pipeline->dynamic_state_mask |= BIT(state);
2062 break;
2063 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
2064 pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS);
2065 break;
2066 default:
2067 assert(!"unsupported dynamic state");
2068 break;
2069 }
2070 }
2071 }
2072
2073 static void
2074 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2075 struct tu_shader *shader,
2076 struct ir3_shader_variant *v)
2077 {
2078 link->const_state = *ir3_const_state(v);
2079 link->constlen = v->constlen;
2080 link->push_consts = shader->push_consts;
2081 }
2082
2083 static void
2084 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2085 struct tu_pipeline *pipeline)
2086 {
2087 struct tu_cs prog_cs;
2088 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2089 tu6_emit_program(&prog_cs, builder, false);
2090 pipeline->program.state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2091
2092 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2093 tu6_emit_program(&prog_cs, builder, true);
2094 pipeline->program.binning_state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2095
2096 VkShaderStageFlags stages = 0;
2097 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2098 stages |= builder->create_info->pStages[i].stage;
2099 }
2100 pipeline->active_stages = stages;
2101
2102 uint32_t desc_sets = 0;
2103 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2104 if (!builder->shaders[i])
2105 continue;
2106
2107 tu_pipeline_set_linkage(&pipeline->program.link[i],
2108 builder->shaders[i],
2109 builder->variants[i]);
2110 desc_sets |= builder->shaders[i]->active_desc_sets;
2111 }
2112 pipeline->active_desc_sets = desc_sets;
2113 }
2114
2115 static void
2116 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2117 struct tu_pipeline *pipeline)
2118 {
2119 const VkPipelineVertexInputStateCreateInfo *vi_info =
2120 builder->create_info->pVertexInputState;
2121 const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
2122 const struct ir3_shader_variant *bs = builder->binning_variant;
2123
2124 struct tu_cs vi_cs;
2125 tu_cs_begin_sub_stream(&pipeline->cs,
2126 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2127 tu6_emit_vertex_input(&vi_cs, vs, vi_info,
2128 &pipeline->vi.bindings_used);
2129 pipeline->vi.state = tu_cs_end_draw_state(&pipeline->cs, &vi_cs);
2130
2131 if (bs) {
2132 tu_cs_begin_sub_stream(&pipeline->cs,
2133 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2134 tu6_emit_vertex_input(
2135 &vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
2136 pipeline->vi.binning_state =
2137 tu_cs_end_draw_state(&pipeline->cs, &vi_cs);
2138 }
2139 }
2140
2141 static void
2142 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2143 struct tu_pipeline *pipeline)
2144 {
2145 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2146 builder->create_info->pInputAssemblyState;
2147
2148 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2149 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2150 }
2151
2152 static bool
2153 tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs,
2154 uint32_t id, uint32_t size)
2155 {
2156 assert(id < ARRAY_SIZE(pipeline->dynamic_state));
2157
2158 if (pipeline->dynamic_state_mask & BIT(id))
2159 return false;
2160
2161 pipeline->dynamic_state[id] = tu_cs_draw_state(&pipeline->cs, cs, size);
2162 return true;
2163 }
2164
2165 static void
2166 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder,
2167 struct tu_pipeline *pipeline)
2168 {
2169 const VkPipelineTessellationStateCreateInfo *tess_info =
2170 builder->create_info->pTessellationState;
2171
2172 if (!tess_info)
2173 return;
2174
2175 assert(pipeline->ia.primtype == DI_PT_PATCHES0);
2176 assert(tess_info->patchControlPoints <= 32);
2177 pipeline->ia.primtype += tess_info->patchControlPoints;
2178 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info =
2179 vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2180 pipeline->tess.upper_left_domain_origin = !domain_info ||
2181 domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
2182 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
2183 const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
2184 pipeline->tess.param_stride = hs->output_size * 4;
2185 pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1;
2186 pipeline->tess.ds_bo_regid = ds->const_state->offsets.primitive_param + 1;
2187 }
2188
2189 static void
2190 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2191 struct tu_pipeline *pipeline)
2192 {
2193 /* The spec says:
2194 *
2195 * pViewportState is a pointer to an instance of the
2196 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2197 * pipeline has rasterization disabled."
2198 *
2199 * We leave the relevant registers stale in that case.
2200 */
2201 if (builder->rasterizer_discard)
2202 return;
2203
2204 const VkPipelineViewportStateCreateInfo *vp_info =
2205 builder->create_info->pViewportState;
2206
2207 struct tu_cs cs;
2208
2209 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_VIEWPORT, 18))
2210 tu6_emit_viewport(&cs, vp_info->pViewports);
2211
2212 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_SCISSOR, 3))
2213 tu6_emit_scissor(&cs, vp_info->pScissors);
2214 }
2215
2216 static void
2217 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2218 struct tu_pipeline *pipeline)
2219 {
2220 const VkPipelineRasterizationStateCreateInfo *rast_info =
2221 builder->create_info->pRasterizationState;
2222
2223 enum a6xx_polygon_mode mode = tu6_polygon_mode(rast_info->polygonMode);
2224
2225 struct tu_cs cs;
2226 pipeline->rast_state = tu_cs_draw_state(&pipeline->cs, &cs, 9);
2227
2228 tu_cs_emit_regs(&cs,
2229 A6XX_GRAS_CL_CNTL(
2230 .znear_clip_disable = rast_info->depthClampEnable,
2231 .zfar_clip_disable = rast_info->depthClampEnable,
2232 .unk5 = rast_info->depthClampEnable,
2233 .zero_gb_scale_z = 1,
2234 .vp_clip_code_ignore = 1));
2235
2236 tu_cs_emit_regs(&cs,
2237 A6XX_VPC_POLYGON_MODE(mode));
2238
2239 tu_cs_emit_regs(&cs,
2240 A6XX_PC_POLYGON_MODE(mode));
2241
2242 /* move to hw ctx init? */
2243 tu_cs_emit_regs(&cs,
2244 A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
2245 A6XX_GRAS_SU_POINT_SIZE(1.0f));
2246
2247 pipeline->gras_su_cntl =
2248 tu6_gras_su_cntl(rast_info, builder->samples);
2249
2250 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_LINE_WIDTH, 2)) {
2251 pipeline->gras_su_cntl |=
2252 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info->lineWidth / 2.0f);
2253 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = pipeline->gras_su_cntl));
2254 }
2255
2256 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BIAS, 4)) {
2257 tu6_emit_depth_bias(&cs, rast_info->depthBiasConstantFactor,
2258 rast_info->depthBiasClamp,
2259 rast_info->depthBiasSlopeFactor);
2260 }
2261
2262 }
2263
2264 static void
2265 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2266 struct tu_pipeline *pipeline)
2267 {
2268 /* The spec says:
2269 *
2270 * pDepthStencilState is a pointer to an instance of the
2271 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2272 * the pipeline has rasterization disabled or if the subpass of the
2273 * render pass the pipeline is created against does not use a
2274 * depth/stencil attachment.
2275 *
2276 * Disable both depth and stencil tests if there is no ds attachment,
2277 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2278 * only the separate stencil attachment
2279 */
2280 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2281 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2282 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2283 ? builder->create_info->pDepthStencilState
2284 : &dummy_ds_info;
2285 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2286 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2287 ? ds_info : &dummy_ds_info;
2288
2289 struct tu_cs cs;
2290 pipeline->ds_state = tu_cs_draw_state(&pipeline->cs, &cs, 6);
2291
2292 /* move to hw ctx init? */
2293 tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
2294 tu6_emit_depth_control(&cs, ds_info_depth,
2295 builder->create_info->pRasterizationState);
2296 tu6_emit_stencil_control(&cs, ds_info);
2297
2298 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
2299 tu_cs_emit_regs(&cs,
2300 A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
2301 A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
2302 }
2303
2304 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
2305 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
2306 .bfmask = ds_info->back.compareMask & 0xff));
2307 }
2308
2309 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2)) {
2310 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.wrmask = ds_info->front.writeMask & 0xff,
2311 .bfwrmask = ds_info->back.writeMask & 0xff));
2312 }
2313
2314 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2)) {
2315 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.ref = ds_info->front.reference & 0xff,
2316 .bfref = ds_info->back.reference & 0xff));
2317 }
2318 }
2319
2320 static void
2321 tu_pipeline_builder_parse_multisample_and_color_blend(
2322 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2323 {
2324 /* The spec says:
2325 *
2326 * pMultisampleState is a pointer to an instance of the
2327 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2328 * has rasterization disabled.
2329 *
2330 * Also,
2331 *
2332 * pColorBlendState is a pointer to an instance of the
2333 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2334 * pipeline has rasterization disabled or if the subpass of the render
2335 * pass the pipeline is created against does not use any color
2336 * attachments.
2337 *
2338 * We leave the relevant registers stale when rasterization is disabled.
2339 */
2340 if (builder->rasterizer_discard)
2341 return;
2342
2343 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2344 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2345 builder->create_info->pMultisampleState;
2346 const VkPipelineColorBlendStateCreateInfo *blend_info =
2347 builder->use_color_attachments ? builder->create_info->pColorBlendState
2348 : &dummy_blend_info;
2349
2350 struct tu_cs cs;
2351 pipeline->blend_state =
2352 tu_cs_draw_state(&pipeline->cs, &cs, blend_info->attachmentCount * 3 + 4);
2353
2354 uint32_t blend_enable_mask;
2355 tu6_emit_rb_mrt_controls(&cs, blend_info,
2356 builder->color_attachment_formats,
2357 &blend_enable_mask);
2358
2359 tu6_emit_blend_control(&cs, blend_enable_mask,
2360 builder->use_dual_src_blend, msaa_info);
2361
2362 assert(cs.cur == cs.end); /* validate draw state size */
2363
2364 if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5)) {
2365 tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2366 tu_cs_emit_array(&cs, (const uint32_t *) blend_info->blendConstants, 4);
2367 }
2368
2369 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2370 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2371 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2372
2373 if (sample_locations && sample_locations->sampleLocationsEnable)
2374 samp_loc = &sample_locations->sampleLocationsInfo;
2375
2376 if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
2377 samp_loc ? 9 : 6)) {
2378 tu6_emit_sample_locations(&cs, samp_loc);
2379 }
2380 }
2381
2382 static void
2383 tu_pipeline_finish(struct tu_pipeline *pipeline,
2384 struct tu_device *dev,
2385 const VkAllocationCallbacks *alloc)
2386 {
2387 tu_cs_finish(&pipeline->cs);
2388 }
2389
2390 static VkResult
2391 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2392 struct tu_pipeline **pipeline)
2393 {
2394 VkResult result;
2395
2396 *pipeline = vk_object_zalloc(&builder->device->vk, builder->alloc,
2397 sizeof(**pipeline), VK_OBJECT_TYPE_PIPELINE);
2398 if (!*pipeline)
2399 return VK_ERROR_OUT_OF_HOST_MEMORY;
2400
2401 (*pipeline)->layout = builder->layout;
2402
2403 /* compile and upload shaders */
2404 result = tu_pipeline_builder_compile_shaders(builder, *pipeline);
2405 if (result != VK_SUCCESS) {
2406 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2407 return result;
2408 }
2409
2410 result = tu_pipeline_allocate_cs(builder->device, *pipeline, builder, NULL);
2411 if (result != VK_SUCCESS) {
2412 vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
2413 return result;
2414 }
2415
2416 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
2417 builder->shader_iova[i] = tu_upload_variant(*pipeline, builder->variants[i]);
2418
2419 builder->binning_vs_iova =
2420 tu_upload_variant(*pipeline, builder->binning_variant);
2421
2422 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2423 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2424 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2425 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2426 tu_pipeline_builder_parse_tessellation(builder, *pipeline);
2427 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2428 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2429 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2430 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2431 tu6_emit_load_state(*pipeline, false);
2432
2433 /* we should have reserved enough space upfront such that the CS never
2434 * grows
2435 */
2436 assert((*pipeline)->cs.bo_count == 1);
2437
2438 return VK_SUCCESS;
2439 }
2440
2441 static void
2442 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2443 {
2444 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2445 if (!builder->shaders[i])
2446 continue;
2447 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2448 }
2449 }
2450
2451 static void
2452 tu_pipeline_builder_init_graphics(
2453 struct tu_pipeline_builder *builder,
2454 struct tu_device *dev,
2455 struct tu_pipeline_cache *cache,
2456 const VkGraphicsPipelineCreateInfo *create_info,
2457 const VkAllocationCallbacks *alloc)
2458 {
2459 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2460
2461 *builder = (struct tu_pipeline_builder) {
2462 .device = dev,
2463 .cache = cache,
2464 .create_info = create_info,
2465 .alloc = alloc,
2466 .layout = layout,
2467 };
2468
2469 builder->rasterizer_discard =
2470 create_info->pRasterizationState->rasterizerDiscardEnable;
2471
2472 if (builder->rasterizer_discard) {
2473 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2474 } else {
2475 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2476
2477 const struct tu_render_pass *pass =
2478 tu_render_pass_from_handle(create_info->renderPass);
2479 const struct tu_subpass *subpass =
2480 &pass->subpasses[create_info->subpass];
2481
2482 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2483 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2484 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2485
2486 assert(subpass->color_count == 0 ||
2487 !create_info->pColorBlendState ||
2488 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2489 builder->color_attachment_count = subpass->color_count;
2490 for (uint32_t i = 0; i < subpass->color_count; i++) {
2491 const uint32_t a = subpass->color_attachments[i].attachment;
2492 if (a == VK_ATTACHMENT_UNUSED)
2493 continue;
2494
2495 builder->color_attachment_formats[i] = pass->attachments[a].format;
2496 builder->use_color_attachments = true;
2497 builder->render_components |= 0xf << (i * 4);
2498 }
2499
2500 if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
2501 builder->color_attachment_count++;
2502 builder->use_dual_src_blend = true;
2503 /* dual source blending has an extra fs output in the 2nd slot */
2504 if (subpass->color_attachments[0].attachment != VK_ATTACHMENT_UNUSED)
2505 builder->render_components |= 0xf << 4;
2506 }
2507 }
2508 }
2509
2510 static VkResult
2511 tu_graphics_pipeline_create(VkDevice device,
2512 VkPipelineCache pipelineCache,
2513 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2514 const VkAllocationCallbacks *pAllocator,
2515 VkPipeline *pPipeline)
2516 {
2517 TU_FROM_HANDLE(tu_device, dev, device);
2518 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2519
2520 struct tu_pipeline_builder builder;
2521 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2522 pCreateInfo, pAllocator);
2523
2524 struct tu_pipeline *pipeline = NULL;
2525 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2526 tu_pipeline_builder_finish(&builder);
2527
2528 if (result == VK_SUCCESS)
2529 *pPipeline = tu_pipeline_to_handle(pipeline);
2530 else
2531 *pPipeline = VK_NULL_HANDLE;
2532
2533 return result;
2534 }
2535
2536 VkResult
2537 tu_CreateGraphicsPipelines(VkDevice device,
2538 VkPipelineCache pipelineCache,
2539 uint32_t count,
2540 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2541 const VkAllocationCallbacks *pAllocator,
2542 VkPipeline *pPipelines)
2543 {
2544 VkResult final_result = VK_SUCCESS;
2545
2546 for (uint32_t i = 0; i < count; i++) {
2547 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2548 &pCreateInfos[i], pAllocator,
2549 &pPipelines[i]);
2550
2551 if (result != VK_SUCCESS)
2552 final_result = result;
2553 }
2554
2555 return final_result;
2556 }
2557
2558 static VkResult
2559 tu_compute_pipeline_create(VkDevice device,
2560 VkPipelineCache _cache,
2561 const VkComputePipelineCreateInfo *pCreateInfo,
2562 const VkAllocationCallbacks *pAllocator,
2563 VkPipeline *pPipeline)
2564 {
2565 TU_FROM_HANDLE(tu_device, dev, device);
2566 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2567 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2568 VkResult result;
2569
2570 struct tu_pipeline *pipeline;
2571
2572 *pPipeline = VK_NULL_HANDLE;
2573
2574 pipeline = vk_object_zalloc(&dev->vk, pAllocator, sizeof(*pipeline),
2575 VK_OBJECT_TYPE_PIPELINE);
2576 if (!pipeline)
2577 return VK_ERROR_OUT_OF_HOST_MEMORY;
2578
2579 pipeline->layout = layout;
2580
2581 struct ir3_shader_key key = {};
2582
2583 struct tu_shader *shader =
2584 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2585 if (!shader) {
2586 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2587 goto fail;
2588 }
2589
2590 pipeline->active_desc_sets = shader->active_desc_sets;
2591
2592 bool created;
2593 struct ir3_shader_variant *v =
2594 ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
2595 if (!v) {
2596 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2597 goto fail;
2598 }
2599
2600 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2601 shader, v);
2602
2603 result = tu_pipeline_allocate_cs(dev, pipeline, NULL, v);
2604 if (result != VK_SUCCESS)
2605 goto fail;
2606
2607 uint64_t shader_iova = tu_upload_variant(pipeline, v);
2608
2609 for (int i = 0; i < 3; i++)
2610 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2611
2612 struct tu_cs prog_cs;
2613 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2614 tu6_emit_cs_config(&prog_cs, shader, v, shader_iova);
2615 pipeline->program.state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
2616
2617 tu6_emit_load_state(pipeline, true);
2618
2619 *pPipeline = tu_pipeline_to_handle(pipeline);
2620 return VK_SUCCESS;
2621
2622 fail:
2623 if (shader)
2624 tu_shader_destroy(dev, shader, pAllocator);
2625
2626 vk_object_free(&dev->vk, pAllocator, pipeline);
2627
2628 return result;
2629 }
2630
2631 VkResult
2632 tu_CreateComputePipelines(VkDevice device,
2633 VkPipelineCache pipelineCache,
2634 uint32_t count,
2635 const VkComputePipelineCreateInfo *pCreateInfos,
2636 const VkAllocationCallbacks *pAllocator,
2637 VkPipeline *pPipelines)
2638 {
2639 VkResult final_result = VK_SUCCESS;
2640
2641 for (uint32_t i = 0; i < count; i++) {
2642 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2643 &pCreateInfos[i],
2644 pAllocator, &pPipelines[i]);
2645 if (result != VK_SUCCESS)
2646 final_result = result;
2647 }
2648
2649 return final_result;
2650 }
2651
2652 void
2653 tu_DestroyPipeline(VkDevice _device,
2654 VkPipeline _pipeline,
2655 const VkAllocationCallbacks *pAllocator)
2656 {
2657 TU_FROM_HANDLE(tu_device, dev, _device);
2658 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2659
2660 if (!_pipeline)
2661 return;
2662
2663 tu_pipeline_finish(pipeline, dev, pAllocator);
2664 vk_object_free(&dev->vk, pAllocator, pipeline);
2665 }