src/gallium/drivers/iris/iris_resource.h

   1 /*
   2  * Copyright 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_RESOURCE_H
  24 #define IRIS_RESOURCE_H
  25
  26 #include "pipe/p_state.h"
  27 #include "util/u_inlines.h"
  28 #include "intel/isl/isl.h"
  29
  30 struct iris_batch;
  31 struct iris_context;
  32
  33 #define IRIS_MAX_MIPLEVELS 15
  34
  35 struct iris_format_info {
  36    enum isl_format fmt;
  37    struct isl_swizzle swizzle;
  38 };
  39
  40 #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE  (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  41 #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  42 #define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  43
  44 enum gen9_astc5x5_wa_tex_type {
  45    GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
  46    GEN9_ASTC5X5_WA_TEX_TYPE_AUX     = 1 << 1,
  47 };
  48
  49 /**
  50  * Resources represent a GPU buffer object or image (mipmap tree).
  51  *
  52  * They contain the storage (BO) and layout information (ISL surface).
  53  */
  54 struct iris_resource {
  55    struct pipe_resource base;
  56    enum pipe_format internal_format;
  57
  58    /**
  59     * The ISL surface layout information for this resource.
  60     *
  61     * This is not filled out for PIPE_BUFFER resources, but is guaranteed
  62     * to be zeroed.  Note that this also guarantees that res->surf.tiling
  63     * will be ISL_TILING_LINEAR, so it's safe to check that.
  64     */
  65    struct isl_surf surf;
  66
  67    /** Backing storage for the resource */
  68    struct iris_bo *bo;
  69
  70    /**
  71     * A bitfield of PIPE_BIND_* indicating how this resource was bound
  72     * in the past.  Only meaningful for PIPE_BUFFER; used for flushing.
  73     */
  74    unsigned bind_history;
  75
  76    /**
  77     * Auxiliary buffer information (CCS, MCS, or HiZ).
  78     */
  79    struct {
  80       /** The surface layout for the auxiliary buffer. */
  81       struct isl_surf surf;
  82
  83       /** The buffer object containing the auxiliary data. */
  84       struct iris_bo *bo;
  85
  86       /** Offset into 'bo' where the auxiliary surface starts. */
  87       uint32_t offset;
  88
  89       /**
  90        * Fast clear color for this surface.  For depth surfaces, the clear
  91        * value is stored as a float32 in the red component.
  92        */
  93       union isl_color_value clear_color;
  94
  95       /** Buffer object containing the indirect clear color.  */
  96       struct iris_bo *clear_color_bo;
  97
  98       /** Offset into bo where the clear color can be found.  */
  99       uint64_t clear_color_offset;
 100
 101       /**
 102        * \brief The type of auxiliary compression used by this resource.
 103        *
 104        * This describes the type of auxiliary compression that is intended to
 105        * be used by this resource.  An aux usage of ISL_AUX_USAGE_NONE means
 106        * that auxiliary compression is permanently disabled.  An aux usage
 107        * other than ISL_AUX_USAGE_NONE does not imply that auxiliary
 108        * compression will always be enabled for this surface.
 109        */
 110       enum isl_aux_usage usage;
 111
 112       /**
 113        * A bitfield of ISL_AUX_* modes that might this resource might use.
 114        *
 115        * For example, a surface might use both CCS_E and CCS_D at times.
 116        */
 117       unsigned possible_usages;
 118
 119       /**
 120        * \brief Maps miptree slices to their current aux state.
 121        *
 122        * This two-dimensional array is indexed as [level][layer] and stores an
 123        * aux state for each slice.
 124        */
 125       enum isl_aux_state **state;
 126
 127       /**
 128        * If (1 << level) is set, HiZ is enabled for that miplevel.
 129        */
 130       uint16_t has_hiz;
 131    } aux;
 132
 133    /**
 134     * For external surfaces, this is DRM format modifier that was used to
 135     * create or import the surface.  For internal surfaces, this will always
 136     * be DRM_FORMAT_MOD_INVALID.
 137     */
 138    const struct isl_drm_modifier_info *mod_info;
 139 };
 140
 141 /**
 142  * A simple <resource, offset> tuple for storing a reference to a
 143  * piece of state stored in a GPU buffer object.
 144  */
 145 struct iris_state_ref {
 146    struct pipe_resource *res;
 147    uint32_t offset;
 148 };
 149
 150 /**
 151  * Gallium CSO for sampler views (texture views).
 152  *
 153  * In addition to the normal pipe_resource, this adds an ISL view
 154  * which may reinterpret the format or restrict levels/layers.
 155  *
 156  * These can also be linear texture buffers.
 157  */
 158 struct iris_sampler_view {
 159    struct pipe_sampler_view base;
 160    struct isl_view view;
 161
 162    union isl_color_value clear_color;
 163
 164    /* A short-cut (not a reference) to the actual resource being viewed.
 165     * Multi-planar (or depth+stencil) images may have multiple resources
 166     * chained together; this skips having to traverse base->texture->*.
 167     */
 168    struct iris_resource *res;
 169
 170    /** The resource (BO) holding our SURFACE_STATE. */
 171    struct iris_state_ref surface_state;
 172 };
 173
 174 /**
 175  * Gallium CSO for surfaces (framebuffer attachments).
 176  *
 177  * A view of a surface that can be bound to a color render target or
 178  * depth/stencil attachment.
 179  */
 180 struct iris_surface {
 181    struct pipe_surface base;
 182    struct isl_view view;
 183    union isl_color_value clear_color;
 184
 185    /** The resource (BO) holding our SURFACE_STATE. */
 186    struct iris_state_ref surface_state;
 187 };
 188
 189 /**
 190  * Transfer object - information about a buffer mapping.
 191  */
 192 struct iris_transfer {
 193    struct pipe_transfer base;
 194    struct pipe_debug_callback *dbg;
 195    void *buffer;
 196    void *ptr;
 197
 198    /** A linear staging resource for GPU-based copy_region transfers. */
 199    struct pipe_resource *staging;
 200    struct blorp_context *blorp;
 201    struct iris_batch *batch;
 202
 203    void (*unmap)(struct iris_transfer *);
 204 };
 205
 206 /**
 207  * Unwrap a pipe_resource to get the underlying iris_bo (for convenience).
 208  */
 209 static inline struct iris_bo *
 210 iris_resource_bo(struct pipe_resource *p_res)
 211 {
 212    struct iris_resource *res = (void *) p_res;
 213    return res->bo;
 214 }
 215
 216 struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
 217                                               enum pipe_format pf,
 218                                               isl_surf_usage_flags_t usage);
 219
 220 struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *);
 221
 222 void iris_get_depth_stencil_resources(struct pipe_resource *res,
 223                                       struct iris_resource **out_z,
 224                                       struct iris_resource **out_s);
 225 bool iris_resource_set_clear_color(struct iris_context *ice,
 226                                    struct iris_resource *res,
 227                                    union isl_color_value color);
 228 union isl_color_value
 229 iris_resource_get_clear_color(const struct iris_resource *res,
 230                               struct iris_bo **clear_color_bo,
 231                               uint64_t *clear_color_offset);
 232
 233 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
 234
 235 void iris_flush_and_dirty_for_history(struct iris_context *ice,
 236                                       struct iris_batch *batch,
 237                                       struct iris_resource *res);
 238
 239 unsigned iris_get_num_logical_layers(const struct iris_resource *res,
 240                                      unsigned level);
 241
 242 void iris_resource_disable_aux(struct iris_resource *res);
 243
 244 #define INTEL_REMAINING_LAYERS UINT32_MAX
 245 #define INTEL_REMAINING_LEVELS UINT32_MAX
 246
 247 void
 248 iris_hiz_exec(struct iris_context *ice,
 249               struct iris_batch *batch,
 250               struct iris_resource *res,
 251               unsigned int level, unsigned int start_layer,
 252               unsigned int num_layers, enum isl_aux_op op,
 253               bool update_clear_depth);
 254
 255 /**
 256  * Prepare a miptree for access
 257  *
 258  * This function should be called prior to any access to miptree in order to
 259  * perform any needed resolves.
 260  *
 261  * \param[in]  start_level    The first mip level to be accessed
 262  *
 263  * \param[in]  num_levels     The number of miplevels to be accessed or
 264  *                            INTEL_REMAINING_LEVELS to indicate every level
 265  *                            above start_level will be accessed
 266  *
 267  * \param[in]  start_layer    The first array slice or 3D layer to be accessed
 268  *
 269  * \param[in]  num_layers     The number of array slices or 3D layers be
 270  *                            accessed or INTEL_REMAINING_LAYERS to indicate
 271  *                            every layer above start_layer will be accessed
 272  *
 273  * \param[in]  aux_supported  Whether or not the access will support the
 274  *                            miptree's auxiliary compression format;  this
 275  *                            must be false for uncompressed miptrees
 276  *
 277  * \param[in]  fast_clear_supported Whether or not the access will support
 278  *                                  fast clears in the miptree's auxiliary
 279  *                                  compression format
 280  */
 281 void
 282 iris_resource_prepare_access(struct iris_context *ice,
 283                              struct iris_batch *batch,
 284                              struct iris_resource *res,
 285                              uint32_t start_level, uint32_t num_levels,
 286                              uint32_t start_layer, uint32_t num_layers,
 287                              enum isl_aux_usage aux_usage,
 288                              bool fast_clear_supported);
 289
 290 /**
 291  * Complete a write operation
 292  *
 293  * This function should be called after any operation writes to a miptree.
 294  * This will update the miptree's compression state so that future resolves
 295  * happen correctly.  Technically, this function can be called before the
 296  * write occurs but the caller must ensure that they don't interlace
 297  * iris_resource_prepare_access and iris_resource_finish_write calls to
 298  * overlapping layer/level ranges.
 299  *
 300  * \param[in]  level             The mip level that was written
 301  *
 302  * \param[in]  start_layer       The first array slice or 3D layer written
 303  *
 304  * \param[in]  num_layers        The number of array slices or 3D layers
 305  *                               written or INTEL_REMAINING_LAYERS to indicate
 306  *                               every layer above start_layer was written
 307  *
 308  * \param[in]  written_with_aux  Whether or not the write was done with
 309  *                               auxiliary compression enabled
 310  */
 311 void
 312 iris_resource_finish_write(struct iris_context *ice,
 313                            struct iris_resource *res, uint32_t level,
 314                            uint32_t start_layer, uint32_t num_layers,
 315                            enum isl_aux_usage aux_usage);
 316
 317 /** Get the auxiliary compression state of a miptree slice */
 318 enum isl_aux_state
 319 iris_resource_get_aux_state(const struct iris_resource *res,
 320                             uint32_t level, uint32_t layer);
 321
 322 /**
 323  * Set the auxiliary compression state of a miptree slice range
 324  *
 325  * This function directly sets the auxiliary compression state of a slice
 326  * range of a miptree.  It only modifies data structures and does not do any
 327  * resolves.  This should only be called by code which directly performs
 328  * compression operations such as fast clears and resolves.  Most code should
 329  * use iris_resource_prepare_access or iris_resource_finish_write.
 330  */
 331 void
 332 iris_resource_set_aux_state(struct iris_context *ice,
 333                             struct iris_resource *res, uint32_t level,
 334                             uint32_t start_layer, uint32_t num_layers,
 335                             enum isl_aux_state aux_state);
 336
 337 /**
 338  * Prepare a miptree for raw access
 339  *
 340  * This helper prepares the miptree for access that knows nothing about any
 341  * sort of compression whatsoever.  This is useful when mapping the surface or
 342  * using it with the blitter.
 343  */
 344 static inline void
 345 iris_resource_access_raw(struct iris_context *ice,
 346                          struct iris_batch *batch,
 347                          struct iris_resource *res,
 348                          uint32_t level, uint32_t layer,
 349                          uint32_t num_layers,
 350                          bool write)
 351 {
 352    iris_resource_prepare_access(ice, batch, res, level, 1, layer, num_layers,
 353                                 ISL_AUX_USAGE_NONE, false);
 354    if (write) {
 355       iris_resource_finish_write(ice, res, level, layer, num_layers,
 356                                  ISL_AUX_USAGE_NONE);
 357    }
 358 }
 359
 360 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
 361                                                    const struct iris_resource *res,
 362                                                    enum isl_format view_fmt,
 363                                                    enum gen9_astc5x5_wa_tex_type);
 364 void iris_resource_prepare_texture(struct iris_context *ice,
 365                                    struct iris_batch *batch,
 366                                    struct iris_resource *res,
 367                                    enum isl_format view_format,
 368                                    uint32_t start_level, uint32_t num_levels,
 369                                    uint32_t start_layer, uint32_t num_layers,
 370                                    enum gen9_astc5x5_wa_tex_type);
 371 void iris_resource_prepare_image(struct iris_context *ice,
 372                                  struct iris_batch *batch,
 373                                  struct iris_resource *res);
 374
 375 void iris_resource_check_level_layer(const struct iris_resource *res,
 376                                      uint32_t level, uint32_t layer);
 377
 378 bool iris_resource_level_has_hiz(const struct iris_resource *res,
 379                                  uint32_t level);
 380
 381 enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
 382                                                   struct iris_resource *res,
 383                                                   enum isl_format render_fmt,
 384                                                   bool blend_enabled,
 385                                                   bool draw_aux_disabled);
 386 void iris_resource_prepare_render(struct iris_context *ice,
 387                                   struct iris_batch *batch,
 388                                   struct iris_resource *res, uint32_t level,
 389                                   uint32_t start_layer, uint32_t layer_count,
 390                                   enum isl_aux_usage aux_usage);
 391 void iris_resource_finish_render(struct iris_context *ice,
 392                                  struct iris_resource *res, uint32_t level,
 393                                  uint32_t start_layer, uint32_t layer_count,
 394                                  enum isl_aux_usage aux_usage);
 395 void iris_resource_prepare_depth(struct iris_context *ice,
 396                                  struct iris_batch *batch,
 397                                  struct iris_resource *res, uint32_t level,
 398                                  uint32_t start_layer, uint32_t layer_count);
 399 void iris_resource_finish_depth(struct iris_context *ice,
 400                                 struct iris_resource *res, uint32_t level,
 401                                 uint32_t start_layer, uint32_t layer_count,
 402                                 bool depth_written);
 403 #endif