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vc4: Don't bother masking out the low 24 bits for integer multiplies
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "pipe/p_state.h"
27 #include "util/u_format.h"
28 #include "util/u_hash.h"
29 #include "util/u_memory.h"
30 #include "util/u_pack_color.h"
31 #include "util/format_srgb.h"
32 #include "util/ralloc.h"
33 #include "util/hash_table.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_info.h"
36 #include "tgsi/tgsi_lowering.h"
37
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41 #ifdef USE_VC4_SIMULATOR
42 #include "simpenrose/simpenrose.h"
43 #endif
44
45 struct vc4_key {
46 struct vc4_uncompiled_shader *shader_state;
47 struct {
48 enum pipe_format format;
49 unsigned compare_mode:1;
50 unsigned compare_func:3;
51 unsigned wrap_s:3;
52 unsigned wrap_t:3;
53 uint8_t swizzle[4];
54 } tex[VC4_MAX_TEXTURE_SAMPLERS];
55 uint8_t ucp_enables;
56 };
57
58 struct vc4_fs_key {
59 struct vc4_key base;
60 enum pipe_format color_format;
61 bool depth_enabled;
62 bool stencil_enabled;
63 bool stencil_twoside;
64 bool stencil_full_writemasks;
65 bool is_points;
66 bool is_lines;
67 bool alpha_test;
68 bool point_coord_upper_left;
69 bool light_twoside;
70 uint8_t alpha_test_func;
71 uint8_t logicop_func;
72 uint32_t point_sprite_mask;
73
74 struct pipe_rt_blend_state blend;
75 };
76
77 struct vc4_vs_key {
78 struct vc4_key base;
79
80 /**
81 * This is a proxy for the array of FS input semantics, which is
82 * larger than we would want to put in the key.
83 */
84 uint64_t compiled_fs_id;
85
86 enum pipe_format attr_formats[8];
87 bool is_coord;
88 bool per_vertex_point_size;
89 };
90
91 static void
92 resize_qreg_array(struct vc4_compile *c,
93 struct qreg **regs,
94 uint32_t *size,
95 uint32_t decl_size)
96 {
97 if (*size >= decl_size)
98 return;
99
100 uint32_t old_size = *size;
101 *size = MAX2(*size * 2, decl_size);
102 *regs = reralloc(c, *regs, struct qreg, *size);
103 if (!*regs) {
104 fprintf(stderr, "Malloc failure\n");
105 abort();
106 }
107
108 for (uint32_t i = old_size; i < *size; i++)
109 (*regs)[i] = c->undef;
110 }
111
112 static struct qreg
113 indirect_uniform_load(struct vc4_compile *c,
114 struct tgsi_full_src_register *src, int swiz)
115 {
116 struct tgsi_ind_register *indirect = &src->Indirect;
117 struct vc4_compiler_ubo_range *range = &c->ubo_ranges[indirect->ArrayID];
118 if (!range->used) {
119 range->used = true;
120 range->dst_offset = c->next_ubo_dst_offset;
121 c->next_ubo_dst_offset += range->size;
122 c->num_ubo_ranges++;
123 };
124
125 assert(src->Register.Indirect);
126 assert(indirect->File == TGSI_FILE_ADDRESS);
127
128 struct qreg addr_val = c->addr[indirect->Swizzle];
129 struct qreg indirect_offset =
130 qir_ADD(c, addr_val, qir_uniform_ui(c,
131 range->dst_offset +
132 (src->Register.Index * 16)+
133 swiz * 4));
134 indirect_offset = qir_MIN(c, indirect_offset, qir_uniform_ui(c, (range->dst_offset +
135 range->size - 4)));
136
137 qir_TEX_DIRECT(c, indirect_offset, qir_uniform(c, QUNIFORM_UBO_ADDR, 0));
138 struct qreg r4 = qir_TEX_RESULT(c);
139 c->num_texture_samples++;
140 return qir_MOV(c, r4);
141 }
142
143 static struct qreg
144 get_src(struct vc4_compile *c, unsigned tgsi_op,
145 struct tgsi_full_src_register *full_src, int i)
146 {
147 struct tgsi_src_register *src = &full_src->Register;
148 struct qreg r = c->undef;
149
150 uint32_t s = i;
151 switch (i) {
152 case TGSI_SWIZZLE_X:
153 s = src->SwizzleX;
154 break;
155 case TGSI_SWIZZLE_Y:
156 s = src->SwizzleY;
157 break;
158 case TGSI_SWIZZLE_Z:
159 s = src->SwizzleZ;
160 break;
161 case TGSI_SWIZZLE_W:
162 s = src->SwizzleW;
163 break;
164 default:
165 abort();
166 }
167
168 switch (src->File) {
169 case TGSI_FILE_NULL:
170 return r;
171 case TGSI_FILE_TEMPORARY:
172 r = c->temps[src->Index * 4 + s];
173 break;
174 case TGSI_FILE_IMMEDIATE:
175 r = c->consts[src->Index * 4 + s];
176 break;
177 case TGSI_FILE_CONSTANT:
178 if (src->Indirect) {
179 r = indirect_uniform_load(c, full_src, s);
180 } else {
181 r = qir_uniform(c, QUNIFORM_UNIFORM, src->Index * 4 + s);
182 }
183 break;
184 case TGSI_FILE_INPUT:
185 r = c->inputs[src->Index * 4 + s];
186 break;
187 case TGSI_FILE_SAMPLER:
188 case TGSI_FILE_SAMPLER_VIEW:
189 r = c->undef;
190 break;
191 default:
192 fprintf(stderr, "unknown src file %d\n", src->File);
193 abort();
194 }
195
196 if (src->Absolute)
197 r = qir_FMAXABS(c, r, r);
198
199 if (src->Negate) {
200 switch (tgsi_opcode_infer_src_type(tgsi_op)) {
201 case TGSI_TYPE_SIGNED:
202 case TGSI_TYPE_UNSIGNED:
203 r = qir_SUB(c, qir_uniform_ui(c, 0), r);
204 break;
205 default:
206 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);
207 break;
208 }
209 }
210
211 return r;
212 };
213
214
215 static void
216 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,
217 int i, struct qreg val)
218 {
219 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;
220
221 assert(!tgsi_dst->Indirect);
222
223 switch (tgsi_dst->File) {
224 case TGSI_FILE_TEMPORARY:
225 c->temps[tgsi_dst->Index * 4 + i] = val;
226 break;
227 case TGSI_FILE_OUTPUT:
228 c->outputs[tgsi_dst->Index * 4 + i] = val;
229 c->num_outputs = MAX2(c->num_outputs,
230 tgsi_dst->Index * 4 + i + 1);
231 break;
232 case TGSI_FILE_ADDRESS:
233 assert(tgsi_dst->Index == 0);
234 c->addr[i] = val;
235 break;
236 default:
237 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);
238 abort();
239 }
240 };
241
242 static struct qreg
243 get_swizzled_channel(struct vc4_compile *c,
244 struct qreg *srcs, int swiz)
245 {
246 switch (swiz) {
247 default:
248 case UTIL_FORMAT_SWIZZLE_NONE:
249 fprintf(stderr, "warning: unknown swizzle\n");
250 /* FALLTHROUGH */
251 case UTIL_FORMAT_SWIZZLE_0:
252 return qir_uniform_f(c, 0.0);
253 case UTIL_FORMAT_SWIZZLE_1:
254 return qir_uniform_f(c, 1.0);
255 case UTIL_FORMAT_SWIZZLE_X:
256 case UTIL_FORMAT_SWIZZLE_Y:
257 case UTIL_FORMAT_SWIZZLE_Z:
258 case UTIL_FORMAT_SWIZZLE_W:
259 return srcs[swiz];
260 }
261 }
262
263 static inline struct qreg
264 qir_SAT(struct vc4_compile *c, struct qreg val)
265 {
266 return qir_FMAX(c,
267 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
268 qir_uniform_f(c, 0.0));
269 }
270
271 static struct qreg
272 tgsi_to_qir_alu(struct vc4_compile *c,
273 struct tgsi_full_instruction *tgsi_inst,
274 enum qop op, struct qreg *src, int i)
275 {
276 struct qreg dst = qir_get_temp(c);
277 qir_emit(c, qir_inst4(op, dst,
278 src[0 * 4 + i],
279 src[1 * 4 + i],
280 src[2 * 4 + i],
281 c->undef));
282 return dst;
283 }
284
285 static struct qreg
286 tgsi_to_qir_scalar(struct vc4_compile *c,
287 struct tgsi_full_instruction *tgsi_inst,
288 enum qop op, struct qreg *src, int i)
289 {
290 struct qreg dst = qir_get_temp(c);
291 qir_emit(c, qir_inst(op, dst,
292 src[0 * 4 + 0],
293 c->undef));
294 return dst;
295 }
296
297 static struct qreg
298 tgsi_to_qir_rcp(struct vc4_compile *c,
299 struct tgsi_full_instruction *tgsi_inst,
300 enum qop op, struct qreg *src, int i)
301 {
302 struct qreg x = src[0 * 4 + 0];
303 struct qreg r = qir_RCP(c, x);
304
305 /* Apply a Newton-Raphson step to improve the accuracy. */
306 r = qir_FMUL(c, r, qir_FSUB(c,
307 qir_uniform_f(c, 2.0),
308 qir_FMUL(c, x, r)));
309
310 return r;
311 }
312
313 static struct qreg
314 tgsi_to_qir_rsq(struct vc4_compile *c,
315 struct tgsi_full_instruction *tgsi_inst,
316 enum qop op, struct qreg *src, int i)
317 {
318 struct qreg x = src[0 * 4 + 0];
319 struct qreg r = qir_RSQ(c, x);
320
321 /* Apply a Newton-Raphson step to improve the accuracy. */
322 r = qir_FMUL(c, r, qir_FSUB(c,
323 qir_uniform_f(c, 1.5),
324 qir_FMUL(c,
325 qir_uniform_f(c, 0.5),
326 qir_FMUL(c, x,
327 qir_FMUL(c, r, r)))));
328
329 return r;
330 }
331
332 static struct qreg
333 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)
334 {
335 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));
336 struct qreg high = qir_POW(c,
337 qir_FMUL(c,
338 qir_FADD(c,
339 srgb,
340 qir_uniform_f(c, 0.055)),
341 qir_uniform_f(c, 1.0 / 1.055)),
342 qir_uniform_f(c, 2.4));
343
344 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));
345 return qir_SEL_X_Y_NS(c, low, high);
346 }
347
348 static struct qreg
349 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)
350 {
351 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));
352 struct qreg high = qir_FSUB(c,
353 qir_FMUL(c,
354 qir_uniform_f(c, 1.055),
355 qir_POW(c,
356 linear,
357 qir_uniform_f(c, 0.41666))),
358 qir_uniform_f(c, 0.055));
359
360 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));
361 return qir_SEL_X_Y_NS(c, low, high);
362 }
363
364 static struct qreg
365 tgsi_to_qir_umul(struct vc4_compile *c,
366 struct tgsi_full_instruction *tgsi_inst,
367 enum qop op, struct qreg *src, int i)
368 {
369 struct qreg src0 = src[0 * 4 + i];
370 struct qreg src0_hi = qir_SHR(c, src0, qir_uniform_ui(c, 24));
371 struct qreg src1 = src[1 * 4 + i];
372 struct qreg src1_hi = qir_SHR(c, src1, qir_uniform_ui(c, 24));
373
374 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
375 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
376 struct qreg lolo = qir_MUL24(c, src0, src1);
377
378 return qir_ADD(c, lolo, qir_SHL(c,
379 qir_ADD(c, hilo, lohi),
380 qir_uniform_ui(c, 24)));
381 }
382
383 static struct qreg
384 tgsi_to_qir_umad(struct vc4_compile *c,
385 struct tgsi_full_instruction *tgsi_inst,
386 enum qop op, struct qreg *src, int i)
387 {
388 return qir_ADD(c, tgsi_to_qir_umul(c, NULL, 0, src, i), src[2 * 4 + i]);
389 }
390
391 static struct qreg
392 tgsi_to_qir_idiv(struct vc4_compile *c,
393 struct tgsi_full_instruction *tgsi_inst,
394 enum qop op, struct qreg *src, int i)
395 {
396 return qir_FTOI(c, qir_FMUL(c,
397 qir_ITOF(c, src[0 * 4 + i]),
398 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));
399 }
400
401 static struct qreg
402 tgsi_to_qir_ineg(struct vc4_compile *c,
403 struct tgsi_full_instruction *tgsi_inst,
404 enum qop op, struct qreg *src, int i)
405 {
406 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);
407 }
408
409 static struct qreg
410 tgsi_to_qir_seq(struct vc4_compile *c,
411 struct tgsi_full_instruction *tgsi_inst,
412 enum qop op, struct qreg *src, int i)
413 {
414 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
415 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));
416 }
417
418 static struct qreg
419 tgsi_to_qir_sne(struct vc4_compile *c,
420 struct tgsi_full_instruction *tgsi_inst,
421 enum qop op, struct qreg *src, int i)
422 {
423 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
424 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));
425 }
426
427 static struct qreg
428 tgsi_to_qir_slt(struct vc4_compile *c,
429 struct tgsi_full_instruction *tgsi_inst,
430 enum qop op, struct qreg *src, int i)
431 {
432 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
433 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));
434 }
435
436 static struct qreg
437 tgsi_to_qir_sge(struct vc4_compile *c,
438 struct tgsi_full_instruction *tgsi_inst,
439 enum qop op, struct qreg *src, int i)
440 {
441 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
442 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));
443 }
444
445 static struct qreg
446 tgsi_to_qir_fseq(struct vc4_compile *c,
447 struct tgsi_full_instruction *tgsi_inst,
448 enum qop op, struct qreg *src, int i)
449 {
450 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
451 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
452 }
453
454 static struct qreg
455 tgsi_to_qir_fsne(struct vc4_compile *c,
456 struct tgsi_full_instruction *tgsi_inst,
457 enum qop op, struct qreg *src, int i)
458 {
459 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
460 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
461 }
462
463 static struct qreg
464 tgsi_to_qir_fslt(struct vc4_compile *c,
465 struct tgsi_full_instruction *tgsi_inst,
466 enum qop op, struct qreg *src, int i)
467 {
468 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
469 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
470 }
471
472 static struct qreg
473 tgsi_to_qir_fsge(struct vc4_compile *c,
474 struct tgsi_full_instruction *tgsi_inst,
475 enum qop op, struct qreg *src, int i)
476 {
477 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));
478 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
479 }
480
481 static struct qreg
482 tgsi_to_qir_useq(struct vc4_compile *c,
483 struct tgsi_full_instruction *tgsi_inst,
484 enum qop op, struct qreg *src, int i)
485 {
486 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
487 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));
488 }
489
490 static struct qreg
491 tgsi_to_qir_usne(struct vc4_compile *c,
492 struct tgsi_full_instruction *tgsi_inst,
493 enum qop op, struct qreg *src, int i)
494 {
495 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
496 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));
497 }
498
499 static struct qreg
500 tgsi_to_qir_islt(struct vc4_compile *c,
501 struct tgsi_full_instruction *tgsi_inst,
502 enum qop op, struct qreg *src, int i)
503 {
504 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
505 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));
506 }
507
508 static struct qreg
509 tgsi_to_qir_isge(struct vc4_compile *c,
510 struct tgsi_full_instruction *tgsi_inst,
511 enum qop op, struct qreg *src, int i)
512 {
513 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));
514 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));
515 }
516
517 static struct qreg
518 tgsi_to_qir_cmp(struct vc4_compile *c,
519 struct tgsi_full_instruction *tgsi_inst,
520 enum qop op, struct qreg *src, int i)
521 {
522 qir_SF(c, src[0 * 4 + i]);
523 return qir_SEL_X_Y_NS(c,
524 src[1 * 4 + i],
525 src[2 * 4 + i]);
526 }
527
528 static struct qreg
529 tgsi_to_qir_ucmp(struct vc4_compile *c,
530 struct tgsi_full_instruction *tgsi_inst,
531 enum qop op, struct qreg *src, int i)
532 {
533 qir_SF(c, src[0 * 4 + i]);
534 return qir_SEL_X_Y_ZC(c,
535 src[1 * 4 + i],
536 src[2 * 4 + i]);
537 }
538
539 static struct qreg
540 tgsi_to_qir_mad(struct vc4_compile *c,
541 struct tgsi_full_instruction *tgsi_inst,
542 enum qop op, struct qreg *src, int i)
543 {
544 return qir_FADD(c,
545 qir_FMUL(c,
546 src[0 * 4 + i],
547 src[1 * 4 + i]),
548 src[2 * 4 + i]);
549 }
550
551 static struct qreg
552 tgsi_to_qir_lrp(struct vc4_compile *c,
553 struct tgsi_full_instruction *tgsi_inst,
554 enum qop op, struct qreg *src, int i)
555 {
556 struct qreg src0 = src[0 * 4 + i];
557 struct qreg src1 = src[1 * 4 + i];
558 struct qreg src2 = src[2 * 4 + i];
559
560 /* LRP is:
561 * src0 * src1 + (1 - src0) * src2.
562 * -> src0 * src1 + src2 - src0 * src2
563 * -> src2 + src0 * (src1 - src2)
564 */
565 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));
566
567 }
568
569 static void
570 tgsi_to_qir_tex(struct vc4_compile *c,
571 struct tgsi_full_instruction *tgsi_inst,
572 enum qop op, struct qreg *src)
573 {
574 assert(!tgsi_inst->Instruction.Saturate);
575
576 struct qreg s = src[0 * 4 + 0];
577 struct qreg t = src[0 * 4 + 1];
578 struct qreg r = src[0 * 4 + 2];
579 uint32_t unit = tgsi_inst->Src[1].Register.Index;
580 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;
581
582 struct qreg proj = c->undef;
583 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
584 proj = qir_RCP(c, src[0 * 4 + 3]);
585 s = qir_FMUL(c, s, proj);
586 t = qir_FMUL(c, t, proj);
587 }
588
589 struct qreg texture_u[] = {
590 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
591 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
592 qir_uniform(c, QUNIFORM_CONSTANT, 0),
593 qir_uniform(c, QUNIFORM_CONSTANT, 0),
594 };
595 uint32_t next_texture_u = 0;
596
597 /* There is no native support for GL texture rectangle coordinates, so
598 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
599 * 1]).
600 */
601 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||
602 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
603 s = qir_FMUL(c, s,
604 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
605 t = qir_FMUL(c, t,
606 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
607 }
608
609 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
610 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
611 is_txl) {
612 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
613 unit | (is_txl << 16));
614 }
615
616 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
617 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
618 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);
619 struct qreg rcp_ma = qir_RCP(c, ma);
620 s = qir_FMUL(c, s, rcp_ma);
621 t = qir_FMUL(c, t, rcp_ma);
622 r = qir_FMUL(c, r, rcp_ma);
623
624 qir_TEX_R(c, r, texture_u[next_texture_u++]);
625 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
626 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
627 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
628 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
629 qir_TEX_R(c, qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),
630 texture_u[next_texture_u++]);
631 }
632
633 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
634 s = qir_SAT(c, s);
635 }
636
637 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
638 t = qir_SAT(c, t);
639 }
640
641 qir_TEX_T(c, t, texture_u[next_texture_u++]);
642
643 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
644 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)
645 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);
646
647 qir_TEX_S(c, s, texture_u[next_texture_u++]);
648
649 c->num_texture_samples++;
650 struct qreg r4 = qir_TEX_RESULT(c);
651
652 enum pipe_format format = c->key->tex[unit].format;
653
654 struct qreg unpacked[4];
655 if (util_format_is_depth_or_stencil(format)) {
656 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,
657 qir_uniform_ui(c, 8)));
658 struct qreg normalized = qir_FMUL(c, depthf,
659 qir_uniform_f(c, 1.0f/0xffffff));
660
661 struct qreg depth_output;
662
663 struct qreg one = qir_uniform_f(c, 1.0f);
664 if (c->key->tex[unit].compare_mode) {
665 struct qreg compare = src[0 * 4 + 2];
666
667 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)
668 compare = qir_FMUL(c, compare, proj);
669
670 switch (c->key->tex[unit].compare_func) {
671 case PIPE_FUNC_NEVER:
672 depth_output = qir_uniform_f(c, 0.0f);
673 break;
674 case PIPE_FUNC_ALWAYS:
675 depth_output = one;
676 break;
677 case PIPE_FUNC_EQUAL:
678 qir_SF(c, qir_FSUB(c, compare, normalized));
679 depth_output = qir_SEL_X_0_ZS(c, one);
680 break;
681 case PIPE_FUNC_NOTEQUAL:
682 qir_SF(c, qir_FSUB(c, compare, normalized));
683 depth_output = qir_SEL_X_0_ZC(c, one);
684 break;
685 case PIPE_FUNC_GREATER:
686 qir_SF(c, qir_FSUB(c, compare, normalized));
687 depth_output = qir_SEL_X_0_NC(c, one);
688 break;
689 case PIPE_FUNC_GEQUAL:
690 qir_SF(c, qir_FSUB(c, normalized, compare));
691 depth_output = qir_SEL_X_0_NS(c, one);
692 break;
693 case PIPE_FUNC_LESS:
694 qir_SF(c, qir_FSUB(c, compare, normalized));
695 depth_output = qir_SEL_X_0_NS(c, one);
696 break;
697 case PIPE_FUNC_LEQUAL:
698 qir_SF(c, qir_FSUB(c, normalized, compare));
699 depth_output = qir_SEL_X_0_NC(c, one);
700 break;
701 }
702 } else {
703 depth_output = normalized;
704 }
705
706 for (int i = 0; i < 4; i++)
707 unpacked[i] = depth_output;
708 } else {
709 for (int i = 0; i < 4; i++)
710 unpacked[i] = qir_R4_UNPACK(c, r4, i);
711 }
712
713 const uint8_t *format_swiz = vc4_get_format_swizzle(format);
714 struct qreg texture_output[4];
715 for (int i = 0; i < 4; i++) {
716 texture_output[i] = get_swizzled_channel(c, unpacked,
717 format_swiz[i]);
718 }
719
720 if (util_format_is_srgb(format)) {
721 for (int i = 0; i < 3; i++)
722 texture_output[i] = qir_srgb_decode(c,
723 texture_output[i]);
724 }
725
726 for (int i = 0; i < 4; i++) {
727 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
728 continue;
729
730 update_dst(c, tgsi_inst, i,
731 get_swizzled_channel(c, texture_output,
732 c->key->tex[unit].swizzle[i]));
733 }
734 }
735
736 static struct qreg
737 tgsi_to_qir_trunc(struct vc4_compile *c,
738 struct tgsi_full_instruction *tgsi_inst,
739 enum qop op, struct qreg *src, int i)
740 {
741 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
742 }
743
744 /**
745 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
746 * to zero).
747 */
748 static struct qreg
749 tgsi_to_qir_frc(struct vc4_compile *c,
750 struct tgsi_full_instruction *tgsi_inst,
751 enum qop op, struct qreg *src, int i)
752 {
753 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
754 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);
755 qir_SF(c, diff);
756 return qir_SEL_X_Y_NS(c,
757 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),
758 diff);
759 }
760
761 /**
762 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
763 * zero).
764 */
765 static struct qreg
766 tgsi_to_qir_flr(struct vc4_compile *c,
767 struct tgsi_full_instruction *tgsi_inst,
768 enum qop op, struct qreg *src, int i)
769 {
770 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
771
772 /* This will be < 0 if we truncated and the truncation was of a value
773 * that was < 0 in the first place.
774 */
775 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));
776
777 return qir_SEL_X_Y_NS(c,
778 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),
779 trunc);
780 }
781
782 /**
783 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
784 * zero).
785 */
786 static struct qreg
787 tgsi_to_qir_ceil(struct vc4_compile *c,
788 struct tgsi_full_instruction *tgsi_inst,
789 enum qop op, struct qreg *src, int i)
790 {
791 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
792
793 /* This will be < 0 if we truncated and the truncation was of a value
794 * that was > 0 in the first place.
795 */
796 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));
797
798 return qir_SEL_X_Y_NS(c,
799 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),
800 trunc);
801 }
802
803 static struct qreg
804 tgsi_to_qir_abs(struct vc4_compile *c,
805 struct tgsi_full_instruction *tgsi_inst,
806 enum qop op, struct qreg *src, int i)
807 {
808 struct qreg arg = src[0 * 4 + i];
809 return qir_FMAXABS(c, arg, arg);
810 }
811
812 /* Note that this instruction replicates its result from the x channel */
813 static struct qreg
814 tgsi_to_qir_sin(struct vc4_compile *c,
815 struct tgsi_full_instruction *tgsi_inst,
816 enum qop op, struct qreg *src, int i)
817 {
818 float coeff[] = {
819 -2.0 * M_PI,
820 pow(2.0 * M_PI, 3) / (3 * 2 * 1),
821 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
822 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
823 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
824 };
825
826 struct qreg scaled_x =
827 qir_FMUL(c,
828 src[0 * 4 + 0],
829 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
830
831 struct qreg x = qir_FADD(c,
832 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
833 qir_uniform_f(c, -0.5));
834 struct qreg x2 = qir_FMUL(c, x, x);
835 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
836 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
837 x = qir_FMUL(c, x, x2);
838 sum = qir_FADD(c,
839 sum,
840 qir_FMUL(c,
841 x,
842 qir_uniform_f(c, coeff[i])));
843 }
844 return sum;
845 }
846
847 /* Note that this instruction replicates its result from the x channel */
848 static struct qreg
849 tgsi_to_qir_cos(struct vc4_compile *c,
850 struct tgsi_full_instruction *tgsi_inst,
851 enum qop op, struct qreg *src, int i)
852 {
853 float coeff[] = {
854 -1.0f,
855 pow(2.0 * M_PI, 2) / (2 * 1),
856 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
857 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
858 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
859 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
860 };
861
862 struct qreg scaled_x =
863 qir_FMUL(c, src[0 * 4 + 0],
864 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
865 struct qreg x_frac = qir_FADD(c,
866 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),
867 qir_uniform_f(c, -0.5));
868
869 struct qreg sum = qir_uniform_f(c, coeff[0]);
870 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
871 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
872 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
873 if (i != 1)
874 x = qir_FMUL(c, x, x2);
875
876 struct qreg mul = qir_FMUL(c,
877 x,
878 qir_uniform_f(c, coeff[i]));
879 if (i == 0)
880 sum = mul;
881 else
882 sum = qir_FADD(c, sum, mul);
883 }
884 return sum;
885 }
886
887 static struct qreg
888 tgsi_to_qir_clamp(struct vc4_compile *c,
889 struct tgsi_full_instruction *tgsi_inst,
890 enum qop op, struct qreg *src, int i)
891 {
892 return qir_FMAX(c, qir_FMIN(c,
893 src[0 * 4 + i],
894 src[2 * 4 + i]),
895 src[1 * 4 + i]);
896 }
897
898 static struct qreg
899 tgsi_to_qir_ssg(struct vc4_compile *c,
900 struct tgsi_full_instruction *tgsi_inst,
901 enum qop op, struct qreg *src, int i)
902 {
903 qir_SF(c, src[0 * 4 + i]);
904 return qir_SEL_X_Y_NC(c,
905 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),
906 qir_uniform_f(c, -1.0));
907 }
908
909 /* Compare to tgsi_to_qir_flr() for the floor logic. */
910 static struct qreg
911 tgsi_to_qir_arl(struct vc4_compile *c,
912 struct tgsi_full_instruction *tgsi_inst,
913 enum qop op, struct qreg *src, int i)
914 {
915 struct qreg trunc = qir_FTOI(c, src[0 * 4 + i]);
916 struct qreg scaled = qir_SHL(c, trunc, qir_uniform_ui(c, 4));
917
918 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], qir_ITOF(c, trunc)));
919
920 return qir_SEL_X_Y_NS(c, qir_SUB(c, scaled, qir_uniform_ui(c, 4)),
921 scaled);
922 }
923
924 static struct qreg
925 tgsi_to_qir_uarl(struct vc4_compile *c,
926 struct tgsi_full_instruction *tgsi_inst,
927 enum qop op, struct qreg *src, int i)
928 {
929 return qir_SHL(c, src[0 * 4 + i], qir_uniform_ui(c, 4));
930 }
931
932 static struct qreg
933 get_channel_from_vpm(struct vc4_compile *c,
934 struct qreg *vpm_reads,
935 uint8_t swiz,
936 const struct util_format_description *desc)
937 {
938 const struct util_format_channel_description *chan =
939 &desc->channel[swiz];
940 struct qreg temp;
941
942 if (swiz > UTIL_FORMAT_SWIZZLE_W)
943 return get_swizzled_channel(c, vpm_reads, swiz);
944 else if (chan->size == 32 &&
945 chan->type == UTIL_FORMAT_TYPE_FLOAT) {
946 return get_swizzled_channel(c, vpm_reads, swiz);
947 } else if (chan->size == 32 &&
948 chan->type == UTIL_FORMAT_TYPE_SIGNED) {
949 if (chan->normalized) {
950 return qir_FMUL(c,
951 qir_ITOF(c, vpm_reads[swiz]),
952 qir_uniform_f(c,
953 1.0 / 0x7fffffff));
954 } else {
955 return qir_ITOF(c, vpm_reads[swiz]);
956 }
957 } else if (chan->size == 8 &&
958 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
959 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
960 struct qreg vpm = vpm_reads[0];
961 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
962 temp = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));
963 if (chan->normalized) {
964 return qir_FSUB(c, qir_FMUL(c,
965 qir_UNPACK_8_F(c, temp, swiz),
966 qir_uniform_f(c, 2.0)),
967 qir_uniform_f(c, 1.0));
968 } else {
969 return qir_FADD(c,
970 qir_ITOF(c,
971 qir_UNPACK_8_I(c, temp,
972 swiz)),
973 qir_uniform_f(c, -128.0));
974 }
975 } else {
976 if (chan->normalized) {
977 return qir_UNPACK_8_F(c, vpm, swiz);
978 } else {
979 return qir_ITOF(c, qir_UNPACK_8_I(c, vpm, swiz));
980 }
981 }
982 } else if (chan->size == 16 &&
983 (chan->type == UTIL_FORMAT_TYPE_UNSIGNED ||
984 chan->type == UTIL_FORMAT_TYPE_SIGNED)) {
985 struct qreg vpm = vpm_reads[swiz / 2];
986
987 /* Note that UNPACK_16F eats a half float, not ints, so we use
988 * UNPACK_16_I for all of these.
989 */
990 if (chan->type == UTIL_FORMAT_TYPE_SIGNED) {
991 temp = qir_ITOF(c, qir_UNPACK_16_I(c, vpm, swiz % 2));
992 if (chan->normalized) {
993 return qir_FMUL(c, temp,
994 qir_uniform_f(c, 1/32768.0f));
995 } else {
996 return temp;
997 }
998 } else {
999 /* UNPACK_16I sign-extends, so we have to emit ANDs. */
1000 temp = vpm;
1001 if (swiz == 1 || swiz == 3)
1002 temp = qir_UNPACK_16_I(c, temp, 1);
1003 temp = qir_AND(c, temp, qir_uniform_ui(c, 0xffff));
1004 temp = qir_ITOF(c, temp);
1005
1006 if (chan->normalized) {
1007 return qir_FMUL(c, temp,
1008 qir_uniform_f(c, 1 / 65535.0));
1009 } else {
1010 return temp;
1011 }
1012 }
1013 } else {
1014 return c->undef;
1015 }
1016 }
1017
1018 static void
1019 emit_vertex_input(struct vc4_compile *c, int attr)
1020 {
1021 enum pipe_format format = c->vs_key->attr_formats[attr];
1022 uint32_t attr_size = util_format_get_blocksize(format);
1023 struct qreg vpm_reads[4];
1024
1025 c->vattr_sizes[attr] = align(attr_size, 4);
1026 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
1027 struct qreg vpm = { QFILE_VPM, attr * 4 + i };
1028 vpm_reads[i] = qir_MOV(c, vpm);
1029 c->num_inputs++;
1030 }
1031
1032 bool format_warned = false;
1033 const struct util_format_description *desc =
1034 util_format_description(format);
1035
1036 for (int i = 0; i < 4; i++) {
1037 uint8_t swiz = desc->swizzle[i];
1038 struct qreg result = get_channel_from_vpm(c, vpm_reads,
1039 swiz, desc);
1040
1041 if (result.file == QFILE_NULL) {
1042 if (!format_warned) {
1043 fprintf(stderr,
1044 "vtx element %d unsupported type: %s\n",
1045 attr, util_format_name(format));
1046 format_warned = true;
1047 }
1048 result = qir_uniform_f(c, 0.0);
1049 }
1050 c->inputs[attr * 4 + i] = result;
1051 }
1052 }
1053
1054 static void
1055 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)
1056 {
1057 if (c->discard.file == QFILE_NULL)
1058 c->discard = qir_uniform_f(c, 0.0);
1059 qir_SF(c, src[0 * 4 + i]);
1060 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1061 c->discard);
1062 }
1063
1064 static void
1065 emit_fragcoord_input(struct vc4_compile *c, int attr)
1066 {
1067 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);
1068 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);
1069 c->inputs[attr * 4 + 2] =
1070 qir_FMUL(c,
1071 qir_ITOF(c, qir_FRAG_Z(c)),
1072 qir_uniform_f(c, 1.0 / 0xffffff));
1073 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
1074 }
1075
1076 static void
1077 emit_point_coord_input(struct vc4_compile *c, int attr)
1078 {
1079 if (c->point_x.file == QFILE_NULL) {
1080 c->point_x = qir_uniform_f(c, 0.0);
1081 c->point_y = qir_uniform_f(c, 0.0);
1082 }
1083
1084 c->inputs[attr * 4 + 0] = c->point_x;
1085 if (c->fs_key->point_coord_upper_left) {
1086 c->inputs[attr * 4 + 1] = qir_FSUB(c,
1087 qir_uniform_f(c, 1.0),
1088 c->point_y);
1089 } else {
1090 c->inputs[attr * 4 + 1] = c->point_y;
1091 }
1092 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1093 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1094 }
1095
1096 static struct qreg
1097 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,
1098 uint8_t index, uint8_t swizzle)
1099 {
1100 uint32_t i = c->num_input_semantics++;
1101 struct qreg vary = {
1102 QFILE_VARY,
1103 i
1104 };
1105
1106 if (c->num_input_semantics >= c->input_semantics_array_size) {
1107 c->input_semantics_array_size =
1108 MAX2(4, c->input_semantics_array_size * 2);
1109
1110 c->input_semantics = reralloc(c, c->input_semantics,
1111 struct vc4_varying_semantic,
1112 c->input_semantics_array_size);
1113 }
1114
1115 c->input_semantics[i].semantic = semantic;
1116 c->input_semantics[i].index = index;
1117 c->input_semantics[i].swizzle = swizzle;
1118
1119 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
1120 }
1121
1122 static void
1123 emit_fragment_input(struct vc4_compile *c, int attr,
1124 struct tgsi_full_declaration *decl)
1125 {
1126 for (int i = 0; i < 4; i++) {
1127 c->inputs[attr * 4 + i] =
1128 emit_fragment_varying(c,
1129 decl->Semantic.Name,
1130 decl->Semantic.Index,
1131 i);
1132 c->num_inputs++;
1133 }
1134 }
1135
1136 static void
1137 emit_face_input(struct vc4_compile *c, int attr)
1138 {
1139 c->inputs[attr * 4 + 0] = qir_FSUB(c,
1140 qir_uniform_f(c, 1.0),
1141 qir_FMUL(c,
1142 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),
1143 qir_uniform_f(c, 2.0)));
1144 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);
1145 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);
1146 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);
1147 }
1148
1149 static void
1150 add_output(struct vc4_compile *c,
1151 uint32_t decl_offset,
1152 uint8_t semantic_name,
1153 uint8_t semantic_index,
1154 uint8_t semantic_swizzle)
1155 {
1156 uint32_t old_array_size = c->outputs_array_size;
1157 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
1158 decl_offset + 1);
1159
1160 if (old_array_size != c->outputs_array_size) {
1161 c->output_semantics = reralloc(c,
1162 c->output_semantics,
1163 struct vc4_varying_semantic,
1164 c->outputs_array_size);
1165 }
1166
1167 c->output_semantics[decl_offset].semantic = semantic_name;
1168 c->output_semantics[decl_offset].index = semantic_index;
1169 c->output_semantics[decl_offset].swizzle = semantic_swizzle;
1170 }
1171
1172 static void
1173 add_array_info(struct vc4_compile *c, uint32_t array_id,
1174 uint32_t start, uint32_t size)
1175 {
1176 if (array_id >= c->ubo_ranges_array_size) {
1177 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
1178 array_id + 1);
1179 c->ubo_ranges = reralloc(c, c->ubo_ranges,
1180 struct vc4_compiler_ubo_range,
1181 c->ubo_ranges_array_size);
1182 }
1183
1184 c->ubo_ranges[array_id].dst_offset = 0;
1185 c->ubo_ranges[array_id].src_offset = start;
1186 c->ubo_ranges[array_id].size = size;
1187 c->ubo_ranges[array_id].used = false;
1188 }
1189
1190 static void
1191 emit_tgsi_declaration(struct vc4_compile *c,
1192 struct tgsi_full_declaration *decl)
1193 {
1194 switch (decl->Declaration.File) {
1195 case TGSI_FILE_TEMPORARY: {
1196 uint32_t old_size = c->temps_array_size;
1197 resize_qreg_array(c, &c->temps, &c->temps_array_size,
1198 (decl->Range.Last + 1) * 4);
1199
1200 for (int i = old_size; i < c->temps_array_size; i++)
1201 c->temps[i] = qir_uniform_ui(c, 0);
1202 break;
1203 }
1204
1205 case TGSI_FILE_INPUT:
1206 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1207 (decl->Range.Last + 1) * 4);
1208
1209 for (int i = decl->Range.First;
1210 i <= decl->Range.Last;
1211 i++) {
1212 if (c->stage == QSTAGE_FRAG) {
1213 if (decl->Semantic.Name ==
1214 TGSI_SEMANTIC_POSITION) {
1215 emit_fragcoord_input(c, i);
1216 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
1217 emit_face_input(c, i);
1218 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
1219 (c->fs_key->point_sprite_mask &
1220 (1 << decl->Semantic.Index))) {
1221 emit_point_coord_input(c, i);
1222 } else {
1223 emit_fragment_input(c, i, decl);
1224 }
1225 } else {
1226 emit_vertex_input(c, i);
1227 }
1228 }
1229 break;
1230
1231 case TGSI_FILE_OUTPUT: {
1232 for (int i = 0; i < 4; i++) {
1233 add_output(c,
1234 decl->Range.First * 4 + i,
1235 decl->Semantic.Name,
1236 decl->Semantic.Index,
1237 i);
1238 }
1239
1240 switch (decl->Semantic.Name) {
1241 case TGSI_SEMANTIC_POSITION:
1242 c->output_position_index = decl->Range.First * 4;
1243 break;
1244 case TGSI_SEMANTIC_CLIPVERTEX:
1245 c->output_clipvertex_index = decl->Range.First * 4;
1246 break;
1247 case TGSI_SEMANTIC_COLOR:
1248 c->output_color_index = decl->Range.First * 4;
1249 break;
1250 case TGSI_SEMANTIC_PSIZE:
1251 c->output_point_size_index = decl->Range.First * 4;
1252 break;
1253 }
1254
1255 break;
1256
1257 case TGSI_FILE_CONSTANT:
1258 add_array_info(c,
1259 decl->Array.ArrayID,
1260 decl->Range.First * 16,
1261 (decl->Range.Last -
1262 decl->Range.First + 1) * 16);
1263 break;
1264 }
1265 }
1266 }
1267
1268 static void
1269 emit_tgsi_instruction(struct vc4_compile *c,
1270 struct tgsi_full_instruction *tgsi_inst)
1271 {
1272 static const struct {
1273 enum qop op;
1274 struct qreg (*func)(struct vc4_compile *c,
1275 struct tgsi_full_instruction *tgsi_inst,
1276 enum qop op,
1277 struct qreg *src, int i);
1278 } op_trans[] = {
1279 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },
1280 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },
1281 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },
1282 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },
1283 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },
1284 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },
1285 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },
1286 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },
1287 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },
1288 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },
1289 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },
1290 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },
1291 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },
1292 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },
1293 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },
1294 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },
1295 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },
1296 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },
1297 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },
1298
1299 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },
1300 [TGSI_OPCODE_UMAD] = { 0, tgsi_to_qir_umad },
1301 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },
1302 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },
1303
1304 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },
1305 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },
1306 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },
1307 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },
1308 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },
1309 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },
1310 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },
1311 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },
1312 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },
1313 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },
1314 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },
1315 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },
1316
1317 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },
1318 [TGSI_OPCODE_UCMP] = { 0, tgsi_to_qir_ucmp },
1319 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },
1320 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_rcp },
1321 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_rsq },
1322 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },
1323 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },
1324 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },
1325 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
1326 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },
1327 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
1328 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
1329 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
1330 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
1331 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },
1332 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },
1333 [TGSI_OPCODE_ARL] = { 0, tgsi_to_qir_arl },
1334 [TGSI_OPCODE_UARL] = { 0, tgsi_to_qir_uarl },
1335 };
1336 static int asdf = 0;
1337 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;
1338
1339 if (tgsi_op == TGSI_OPCODE_END)
1340 return;
1341
1342 struct qreg src_regs[12];
1343 for (int s = 0; s < 3; s++) {
1344 for (int i = 0; i < 4; i++) {
1345 src_regs[4 * s + i] =
1346 get_src(c, tgsi_inst->Instruction.Opcode,
1347 &tgsi_inst->Src[s], i);
1348 }
1349 }
1350
1351 switch (tgsi_op) {
1352 case TGSI_OPCODE_TEX:
1353 case TGSI_OPCODE_TXP:
1354 case TGSI_OPCODE_TXB:
1355 case TGSI_OPCODE_TXL:
1356 tgsi_to_qir_tex(c, tgsi_inst,
1357 op_trans[tgsi_op].op, src_regs);
1358 return;
1359 case TGSI_OPCODE_KILL:
1360 c->discard = qir_uniform_f(c, 1.0);
1361 return;
1362 case TGSI_OPCODE_KILL_IF:
1363 for (int i = 0; i < 4; i++)
1364 tgsi_to_qir_kill_if(c, src_regs, i);
1365 return;
1366 default:
1367 break;
1368 }
1369
1370 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {
1371 fprintf(stderr, "unknown tgsi inst: ");
1372 tgsi_dump_instruction(tgsi_inst, asdf++);
1373 fprintf(stderr, "\n");
1374 abort();
1375 }
1376
1377 for (int i = 0; i < 4; i++) {
1378 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))
1379 continue;
1380
1381 struct qreg result;
1382
1383 result = op_trans[tgsi_op].func(c, tgsi_inst,
1384 op_trans[tgsi_op].op,
1385 src_regs, i);
1386
1387 if (tgsi_inst->Instruction.Saturate) {
1388 float low = (tgsi_inst->Instruction.Saturate ==
1389 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);
1390 result = qir_FMAX(c,
1391 qir_FMIN(c,
1392 result,
1393 qir_uniform_f(c, 1.0)),
1394 qir_uniform_f(c, low));
1395 }
1396
1397 update_dst(c, tgsi_inst, i, result);
1398 }
1399 }
1400
1401 static void
1402 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)
1403 {
1404 for (int i = 0; i < 4; i++) {
1405 unsigned n = c->num_consts++;
1406 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);
1407 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);
1408 }
1409 }
1410
1411 static struct qreg
1412 vc4_blend_channel(struct vc4_compile *c,
1413 struct qreg *dst,
1414 struct qreg *src,
1415 struct qreg val,
1416 unsigned factor,
1417 int channel)
1418 {
1419 switch(factor) {
1420 case PIPE_BLENDFACTOR_ONE:
1421 return val;
1422 case PIPE_BLENDFACTOR_SRC_COLOR:
1423 return qir_FMUL(c, val, src[channel]);
1424 case PIPE_BLENDFACTOR_SRC_ALPHA:
1425 return qir_FMUL(c, val, src[3]);
1426 case PIPE_BLENDFACTOR_DST_ALPHA:
1427 return qir_FMUL(c, val, dst[3]);
1428 case PIPE_BLENDFACTOR_DST_COLOR:
1429 return qir_FMUL(c, val, dst[channel]);
1430 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
1431 if (channel != 3) {
1432 return qir_FMUL(c,
1433 val,
1434 qir_FMIN(c,
1435 src[3],
1436 qir_FSUB(c,
1437 qir_uniform_f(c, 1.0),
1438 dst[3])));
1439 } else {
1440 return val;
1441 }
1442 case PIPE_BLENDFACTOR_CONST_COLOR:
1443 return qir_FMUL(c, val,
1444 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR,
1445 channel));
1446 case PIPE_BLENDFACTOR_CONST_ALPHA:
1447 return qir_FMUL(c, val,
1448 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR, 3));
1449 case PIPE_BLENDFACTOR_ZERO:
1450 return qir_uniform_f(c, 0.0);
1451 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
1452 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1453 src[channel]));
1454 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
1455 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1456 src[3]));
1457 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
1458 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1459 dst[3]));
1460 case PIPE_BLENDFACTOR_INV_DST_COLOR:
1461 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),
1462 dst[channel]));
1463 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
1464 return qir_FMUL(c, val,
1465 qir_FSUB(c, qir_uniform_f(c, 1.0),
1466 qir_uniform(c,
1467 QUNIFORM_BLEND_CONST_COLOR,
1468 channel)));
1469 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
1470 return qir_FMUL(c, val,
1471 qir_FSUB(c, qir_uniform_f(c, 1.0),
1472 qir_uniform(c,
1473 QUNIFORM_BLEND_CONST_COLOR,
1474 3)));
1475
1476 default:
1477 case PIPE_BLENDFACTOR_SRC1_COLOR:
1478 case PIPE_BLENDFACTOR_SRC1_ALPHA:
1479 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
1480 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
1481 /* Unsupported. */
1482 fprintf(stderr, "Unknown blend factor %d\n", factor);
1483 return val;
1484 }
1485 }
1486
1487 static struct qreg
1488 vc4_blend_func(struct vc4_compile *c,
1489 struct qreg src, struct qreg dst,
1490 unsigned func)
1491 {
1492 switch (func) {
1493 case PIPE_BLEND_ADD:
1494 return qir_FADD(c, src, dst);
1495 case PIPE_BLEND_SUBTRACT:
1496 return qir_FSUB(c, src, dst);
1497 case PIPE_BLEND_REVERSE_SUBTRACT:
1498 return qir_FSUB(c, dst, src);
1499 case PIPE_BLEND_MIN:
1500 return qir_FMIN(c, src, dst);
1501 case PIPE_BLEND_MAX:
1502 return qir_FMAX(c, src, dst);
1503
1504 default:
1505 /* Unsupported. */
1506 fprintf(stderr, "Unknown blend func %d\n", func);
1507 return src;
1508
1509 }
1510 }
1511
1512 /**
1513 * Implements fixed function blending in shader code.
1514 *
1515 * VC4 doesn't have any hardware support for blending. Instead, you read the
1516 * current contents of the destination from the tile buffer after having
1517 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do
1518 * math using your output color and that destination value, and update the
1519 * output color appropriately.
1520 */
1521 static void
1522 vc4_blend(struct vc4_compile *c, struct qreg *result,
1523 struct qreg *dst_color, struct qreg *src_color)
1524 {
1525 struct pipe_rt_blend_state *blend = &c->fs_key->blend;
1526
1527 if (!blend->blend_enable) {
1528 for (int i = 0; i < 4; i++)
1529 result[i] = src_color[i];
1530 return;
1531 }
1532
1533 struct qreg clamped_src[4];
1534 struct qreg clamped_dst[4];
1535 for (int i = 0; i < 4; i++) {
1536 clamped_src[i] = qir_SAT(c, src_color[i]);
1537 clamped_dst[i] = qir_SAT(c, dst_color[i]);
1538 }
1539 src_color = clamped_src;
1540 dst_color = clamped_dst;
1541
1542 struct qreg src_blend[4], dst_blend[4];
1543 for (int i = 0; i < 3; i++) {
1544 src_blend[i] = vc4_blend_channel(c,
1545 dst_color, src_color,
1546 src_color[i],
1547 blend->rgb_src_factor, i);
1548 dst_blend[i] = vc4_blend_channel(c,
1549 dst_color, src_color,
1550 dst_color[i],
1551 blend->rgb_dst_factor, i);
1552 }
1553 src_blend[3] = vc4_blend_channel(c,
1554 dst_color, src_color,
1555 src_color[3],
1556 blend->alpha_src_factor, 3);
1557 dst_blend[3] = vc4_blend_channel(c,
1558 dst_color, src_color,
1559 dst_color[3],
1560 blend->alpha_dst_factor, 3);
1561
1562 for (int i = 0; i < 3; i++) {
1563 result[i] = vc4_blend_func(c,
1564 src_blend[i], dst_blend[i],
1565 blend->rgb_func);
1566 }
1567 result[3] = vc4_blend_func(c,
1568 src_blend[3], dst_blend[3],
1569 blend->alpha_func);
1570 }
1571
1572 static void
1573 clip_distance_discard(struct vc4_compile *c)
1574 {
1575 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {
1576 if (!(c->key->ucp_enables & (1 << i)))
1577 continue;
1578
1579 struct qreg dist = emit_fragment_varying(c,
1580 TGSI_SEMANTIC_CLIPDIST,
1581 i,
1582 TGSI_SWIZZLE_X);
1583
1584 qir_SF(c, dist);
1585
1586 if (c->discard.file == QFILE_NULL)
1587 c->discard = qir_uniform_f(c, 0.0);
1588
1589 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),
1590 c->discard);
1591 }
1592 }
1593
1594 static void
1595 alpha_test_discard(struct vc4_compile *c)
1596 {
1597 struct qreg src_alpha;
1598 struct qreg alpha_ref = qir_uniform(c, QUNIFORM_ALPHA_REF, 0);
1599
1600 if (!c->fs_key->alpha_test)
1601 return;
1602
1603 if (c->output_color_index != -1)
1604 src_alpha = c->outputs[c->output_color_index + 3];
1605 else
1606 src_alpha = qir_uniform_f(c, 1.0);
1607
1608 if (c->discard.file == QFILE_NULL)
1609 c->discard = qir_uniform_f(c, 0.0);
1610
1611 switch (c->fs_key->alpha_test_func) {
1612 case PIPE_FUNC_NEVER:
1613 c->discard = qir_uniform_f(c, 1.0);
1614 break;
1615 case PIPE_FUNC_ALWAYS:
1616 break;
1617 case PIPE_FUNC_EQUAL:
1618 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1619 c->discard = qir_SEL_X_Y_ZS(c, c->discard,
1620 qir_uniform_f(c, 1.0));
1621 break;
1622 case PIPE_FUNC_NOTEQUAL:
1623 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1624 c->discard = qir_SEL_X_Y_ZC(c, c->discard,
1625 qir_uniform_f(c, 1.0));
1626 break;
1627 case PIPE_FUNC_GREATER:
1628 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1629 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1630 qir_uniform_f(c, 1.0));
1631 break;
1632 case PIPE_FUNC_GEQUAL:
1633 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1634 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1635 qir_uniform_f(c, 1.0));
1636 break;
1637 case PIPE_FUNC_LESS:
1638 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));
1639 c->discard = qir_SEL_X_Y_NS(c, c->discard,
1640 qir_uniform_f(c, 1.0));
1641 break;
1642 case PIPE_FUNC_LEQUAL:
1643 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));
1644 c->discard = qir_SEL_X_Y_NC(c, c->discard,
1645 qir_uniform_f(c, 1.0));
1646 break;
1647 }
1648 }
1649
1650 static struct qreg
1651 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)
1652 {
1653 switch (c->fs_key->logicop_func) {
1654 case PIPE_LOGICOP_CLEAR:
1655 return qir_uniform_f(c, 0.0);
1656 case PIPE_LOGICOP_NOR:
1657 return qir_NOT(c, qir_OR(c, src, dst));
1658 case PIPE_LOGICOP_AND_INVERTED:
1659 return qir_AND(c, qir_NOT(c, src), dst);
1660 case PIPE_LOGICOP_COPY_INVERTED:
1661 return qir_NOT(c, src);
1662 case PIPE_LOGICOP_AND_REVERSE:
1663 return qir_AND(c, src, qir_NOT(c, dst));
1664 case PIPE_LOGICOP_INVERT:
1665 return qir_NOT(c, dst);
1666 case PIPE_LOGICOP_XOR:
1667 return qir_XOR(c, src, dst);
1668 case PIPE_LOGICOP_NAND:
1669 return qir_NOT(c, qir_AND(c, src, dst));
1670 case PIPE_LOGICOP_AND:
1671 return qir_AND(c, src, dst);
1672 case PIPE_LOGICOP_EQUIV:
1673 return qir_NOT(c, qir_XOR(c, src, dst));
1674 case PIPE_LOGICOP_NOOP:
1675 return dst;
1676 case PIPE_LOGICOP_OR_INVERTED:
1677 return qir_OR(c, qir_NOT(c, src), dst);
1678 case PIPE_LOGICOP_OR_REVERSE:
1679 return qir_OR(c, src, qir_NOT(c, dst));
1680 case PIPE_LOGICOP_OR:
1681 return qir_OR(c, src, dst);
1682 case PIPE_LOGICOP_SET:
1683 return qir_uniform_ui(c, ~0);
1684 case PIPE_LOGICOP_COPY:
1685 default:
1686 return src;
1687 }
1688 }
1689
1690 static void
1691 emit_frag_end(struct vc4_compile *c)
1692 {
1693 clip_distance_discard(c);
1694 alpha_test_discard(c);
1695
1696 enum pipe_format color_format = c->fs_key->color_format;
1697 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);
1698 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };
1699 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1700 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };
1701 struct qreg packed_dst_color = c->undef;
1702
1703 if (c->fs_key->blend.blend_enable ||
1704 c->fs_key->blend.colormask != 0xf ||
1705 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1706 struct qreg r4 = qir_TLB_COLOR_READ(c);
1707 for (int i = 0; i < 4; i++)
1708 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);
1709 for (int i = 0; i < 4; i++) {
1710 dst_color[i] = get_swizzled_channel(c,
1711 tlb_read_color,
1712 format_swiz[i]);
1713 if (util_format_is_srgb(color_format) && i != 3) {
1714 linear_dst_color[i] =
1715 qir_srgb_decode(c, dst_color[i]);
1716 } else {
1717 linear_dst_color[i] = dst_color[i];
1718 }
1719 }
1720
1721 /* Save the packed value for logic ops. Can't reuse r4
1722 * becuase other things might smash it (like sRGB)
1723 */
1724 packed_dst_color = qir_MOV(c, r4);
1725 }
1726
1727 struct qreg blend_color[4];
1728 struct qreg undef_array[4] = {
1729 c->undef, c->undef, c->undef, c->undef
1730 };
1731 vc4_blend(c, blend_color, linear_dst_color,
1732 (c->output_color_index != -1 ?
1733 c->outputs + c->output_color_index :
1734 undef_array));
1735
1736 if (util_format_is_srgb(color_format)) {
1737 for (int i = 0; i < 3; i++)
1738 blend_color[i] = qir_srgb_encode(c, blend_color[i]);
1739 }
1740
1741 /* Debug: Sometimes you're getting a black output and just want to see
1742 * if the FS is getting executed at all. Spam magenta into the color
1743 * output.
1744 */
1745 if (0) {
1746 blend_color[0] = qir_uniform_f(c, 1.0);
1747 blend_color[1] = qir_uniform_f(c, 0.0);
1748 blend_color[2] = qir_uniform_f(c, 1.0);
1749 blend_color[3] = qir_uniform_f(c, 0.5);
1750 }
1751
1752 struct qreg swizzled_outputs[4];
1753 for (int i = 0; i < 4; i++) {
1754 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,
1755 format_swiz[i]);
1756 }
1757
1758 if (c->discard.file != QFILE_NULL)
1759 qir_TLB_DISCARD_SETUP(c, c->discard);
1760
1761 if (c->fs_key->stencil_enabled) {
1762 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 0));
1763 if (c->fs_key->stencil_twoside) {
1764 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 1));
1765 }
1766 if (c->fs_key->stencil_full_writemasks) {
1767 qir_TLB_STENCIL_SETUP(c, qir_uniform(c, QUNIFORM_STENCIL, 2));
1768 }
1769 }
1770
1771 if (c->fs_key->depth_enabled) {
1772 struct qreg z;
1773 if (c->output_position_index != -1) {
1774 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],
1775 qir_uniform_f(c, 0xffffff)));
1776 } else {
1777 z = qir_FRAG_Z(c);
1778 }
1779 qir_TLB_Z_WRITE(c, z);
1780 }
1781
1782 struct qreg packed_color = c->undef;
1783 for (int i = 0; i < 4; i++) {
1784 if (swizzled_outputs[i].file == QFILE_NULL)
1785 continue;
1786 if (packed_color.file == QFILE_NULL) {
1787 packed_color = qir_PACK_8888_F(c, swizzled_outputs[i]);
1788 } else {
1789 packed_color = qir_PACK_8_F(c,
1790 packed_color,
1791 swizzled_outputs[i],
1792 i);
1793 }
1794 }
1795
1796 if (packed_color.file == QFILE_NULL)
1797 packed_color = qir_uniform_ui(c, 0);
1798
1799 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {
1800 packed_color = vc4_logicop(c, packed_color, packed_dst_color);
1801 }
1802
1803 /* If the bit isn't set in the color mask, then just return the
1804 * original dst color, instead.
1805 */
1806 uint32_t colormask = 0xffffffff;
1807 for (int i = 0; i < 4; i++) {
1808 if (format_swiz[i] < 4 &&
1809 !(c->fs_key->blend.colormask & (1 << format_swiz[i]))) {
1810 colormask &= ~(0xff << (i * 8));
1811 }
1812 }
1813 if (colormask != 0xffffffff) {
1814 packed_color = qir_OR(c,
1815 qir_AND(c, packed_color,
1816 qir_uniform_ui(c, colormask)),
1817 qir_AND(c, packed_dst_color,
1818 qir_uniform_ui(c, ~colormask)));
1819 }
1820
1821 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,
1822 packed_color, c->undef));
1823 }
1824
1825 static void
1826 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1827 {
1828 struct qreg xyi[2];
1829
1830 for (int i = 0; i < 2; i++) {
1831 struct qreg scale =
1832 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1833
1834 xyi[i] = qir_FTOI(c, qir_FMUL(c,
1835 qir_FMUL(c,
1836 c->outputs[c->output_position_index + i],
1837 scale),
1838 rcp_w));
1839 }
1840
1841 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
1842 }
1843
1844 static void
1845 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1846 {
1847 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1848 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1849
1850 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1851 c->outputs[c->output_position_index + 2],
1852 zscale),
1853 rcp_w),
1854 zoffset));
1855 }
1856
1857 static void
1858 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1859 {
1860 qir_VPM_WRITE(c, rcp_w);
1861 }
1862
1863 static void
1864 emit_point_size_write(struct vc4_compile *c)
1865 {
1866 struct qreg point_size;
1867
1868 if (c->output_point_size_index != -1)
1869 point_size = c->outputs[c->output_point_size_index + 3];
1870 else
1871 point_size = qir_uniform_f(c, 1.0);
1872
1873 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1874 * BCM21553).
1875 */
1876 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1877
1878 qir_VPM_WRITE(c, point_size);
1879 }
1880
1881 /**
1882 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1883 *
1884 * The simulator insists that there be at least one vertex attribute, so
1885 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1886 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1887 * to consume it here.
1888 */
1889 static void
1890 emit_stub_vpm_read(struct vc4_compile *c)
1891 {
1892 if (c->num_inputs)
1893 return;
1894
1895 c->vattr_sizes[0] = 4;
1896 struct qreg vpm = { QFILE_VPM, 0 };
1897 (void)qir_MOV(c, vpm);
1898 c->num_inputs++;
1899 }
1900
1901 static void
1902 emit_ucp_clipdistance(struct vc4_compile *c)
1903 {
1904 unsigned cv;
1905 if (c->output_clipvertex_index != -1)
1906 cv = c->output_clipvertex_index;
1907 else if (c->output_position_index != -1)
1908 cv = c->output_position_index;
1909 else
1910 return;
1911
1912 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {
1913 if (!(c->key->ucp_enables & (1 << plane)))
1914 continue;
1915
1916 /* Pick the next outputs[] that hasn't been written to, since
1917 * there are no other program writes left to be processed at
1918 * this point. If something had been declared but not written
1919 * (like a w component), we'll just smash over the top of it.
1920 */
1921 uint32_t output_index = c->num_outputs++;
1922 add_output(c, output_index,
1923 TGSI_SEMANTIC_CLIPDIST,
1924 plane,
1925 TGSI_SWIZZLE_X);
1926
1927
1928 struct qreg dist = qir_uniform_f(c, 0.0);
1929 for (int i = 0; i < 4; i++) {
1930 struct qreg pos_chan = c->outputs[cv + i];
1931 struct qreg ucp =
1932 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1933 plane * 4 + i);
1934 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));
1935 }
1936
1937 c->outputs[output_index] = dist;
1938 }
1939 }
1940
1941 static void
1942 emit_vert_end(struct vc4_compile *c,
1943 struct vc4_varying_semantic *fs_inputs,
1944 uint32_t num_fs_inputs)
1945 {
1946 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1947
1948 emit_stub_vpm_read(c);
1949 emit_ucp_clipdistance(c);
1950
1951 emit_scaled_viewport_write(c, rcp_w);
1952 emit_zs_write(c, rcp_w);
1953 emit_rcp_wc_write(c, rcp_w);
1954 if (c->vs_key->per_vertex_point_size)
1955 emit_point_size_write(c);
1956
1957 for (int i = 0; i < num_fs_inputs; i++) {
1958 struct vc4_varying_semantic *input = &fs_inputs[i];
1959 int j;
1960
1961 for (j = 0; j < c->num_outputs; j++) {
1962 struct vc4_varying_semantic *output =
1963 &c->output_semantics[j];
1964
1965 if (input->semantic == output->semantic &&
1966 input->index == output->index &&
1967 input->swizzle == output->swizzle) {
1968 qir_VPM_WRITE(c, c->outputs[j]);
1969 break;
1970 }
1971 }
1972 /* Emit padding if we didn't find a declared VS output for
1973 * this FS input.
1974 */
1975 if (j == c->num_outputs)
1976 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1977 }
1978 }
1979
1980 static void
1981 emit_coord_end(struct vc4_compile *c)
1982 {
1983 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);
1984
1985 emit_stub_vpm_read(c);
1986
1987 for (int i = 0; i < 4; i++)
1988 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1989
1990 emit_scaled_viewport_write(c, rcp_w);
1991 emit_zs_write(c, rcp_w);
1992 emit_rcp_wc_write(c, rcp_w);
1993 if (c->vs_key->per_vertex_point_size)
1994 emit_point_size_write(c);
1995 }
1996
1997 static struct vc4_compile *
1998 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,
1999 struct vc4_key *key)
2000 {
2001 struct vc4_compile *c = qir_compile_init();
2002 int ret;
2003
2004 c->stage = stage;
2005 for (int i = 0; i < 4; i++)
2006 c->addr[i] = qir_uniform_f(c, 0.0);
2007
2008 c->shader_state = &key->shader_state->base;
2009 c->program_id = key->shader_state->program_id;
2010 c->variant_id = key->shader_state->compiled_variant_count++;
2011
2012 c->key = key;
2013 switch (stage) {
2014 case QSTAGE_FRAG:
2015 c->fs_key = (struct vc4_fs_key *)key;
2016 if (c->fs_key->is_points) {
2017 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);
2018 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);
2019 } else if (c->fs_key->is_lines) {
2020 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);
2021 }
2022 break;
2023 case QSTAGE_VERT:
2024 c->vs_key = (struct vc4_vs_key *)key;
2025 break;
2026 case QSTAGE_COORD:
2027 c->vs_key = (struct vc4_vs_key *)key;
2028 break;
2029 }
2030
2031 const struct tgsi_token *tokens = key->shader_state->base.tokens;
2032 if (c->fs_key && c->fs_key->light_twoside) {
2033 if (!key->shader_state->twoside_tokens) {
2034 const struct tgsi_lowering_config lowering_config = {
2035 .color_two_side = true,
2036 };
2037 struct tgsi_shader_info info;
2038 key->shader_state->twoside_tokens =
2039 tgsi_transform_lowering(&lowering_config,
2040 key->shader_state->base.tokens,
2041 &info);
2042
2043 /* If no transformation occurred, then NULL is
2044 * returned and we just use our original tokens.
2045 */
2046 if (!key->shader_state->twoside_tokens) {
2047 key->shader_state->twoside_tokens =
2048 key->shader_state->base.tokens;
2049 }
2050 }
2051 tokens = key->shader_state->twoside_tokens;
2052 }
2053
2054 ret = tgsi_parse_init(&c->parser, tokens);
2055 assert(ret == TGSI_PARSE_OK);
2056
2057 if (vc4_debug & VC4_DEBUG_TGSI) {
2058 fprintf(stderr, "%s prog %d/%d TGSI:\n",
2059 qir_get_stage_name(c->stage),
2060 c->program_id, c->variant_id);
2061 tgsi_dump(tokens, 0);
2062 }
2063
2064 while (!tgsi_parse_end_of_tokens(&c->parser)) {
2065 tgsi_parse_token(&c->parser);
2066
2067 switch (c->parser.FullToken.Token.Type) {
2068 case TGSI_TOKEN_TYPE_DECLARATION:
2069 emit_tgsi_declaration(c,
2070 &c->parser.FullToken.FullDeclaration);
2071 break;
2072
2073 case TGSI_TOKEN_TYPE_INSTRUCTION:
2074 emit_tgsi_instruction(c,
2075 &c->parser.FullToken.FullInstruction);
2076 break;
2077
2078 case TGSI_TOKEN_TYPE_IMMEDIATE:
2079 parse_tgsi_immediate(c,
2080 &c->parser.FullToken.FullImmediate);
2081 break;
2082 }
2083 }
2084
2085 switch (stage) {
2086 case QSTAGE_FRAG:
2087 emit_frag_end(c);
2088 break;
2089 case QSTAGE_VERT:
2090 emit_vert_end(c,
2091 vc4->prog.fs->input_semantics,
2092 vc4->prog.fs->num_inputs);
2093 break;
2094 case QSTAGE_COORD:
2095 emit_coord_end(c);
2096 break;
2097 }
2098
2099 tgsi_parse_free(&c->parser);
2100 if (vc4_debug & VC4_DEBUG_QIR) {
2101 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2102 qir_get_stage_name(c->stage),
2103 c->program_id, c->variant_id);
2104 qir_dump(c);
2105 }
2106
2107 qir_optimize(c);
2108 qir_lower_uniforms(c);
2109
2110 if (vc4_debug & VC4_DEBUG_QIR) {
2111 fprintf(stderr, "%s prog %d/%d QIR:\n",
2112 qir_get_stage_name(c->stage),
2113 c->program_id, c->variant_id);
2114 qir_dump(c);
2115 }
2116 qir_reorder_uniforms(c);
2117 vc4_generate_code(vc4, c);
2118
2119 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2120 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2121 qir_get_stage_name(c->stage),
2122 c->program_id, c->variant_id,
2123 c->qpu_inst_count);
2124 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2125 qir_get_stage_name(c->stage),
2126 c->program_id, c->variant_id,
2127 c->num_uniforms);
2128 }
2129
2130 return c;
2131 }
2132
2133 static void *
2134 vc4_shader_state_create(struct pipe_context *pctx,
2135 const struct pipe_shader_state *cso)
2136 {
2137 struct vc4_context *vc4 = vc4_context(pctx);
2138 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2139 if (!so)
2140 return NULL;
2141
2142 const struct tgsi_lowering_config lowering_config = {
2143 .lower_DST = true,
2144 .lower_XPD = true,
2145 .lower_SCS = true,
2146 .lower_POW = true,
2147 .lower_LIT = true,
2148 .lower_EXP = true,
2149 .lower_LOG = true,
2150 .lower_DP4 = true,
2151 .lower_DP3 = true,
2152 .lower_DPH = true,
2153 .lower_DP2 = true,
2154 .lower_DP2A = true,
2155 };
2156
2157 struct tgsi_shader_info info;
2158 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);
2159 if (!so->base.tokens)
2160 so->base.tokens = tgsi_dup_tokens(cso->tokens);
2161 so->program_id = vc4->next_uncompiled_program_id++;
2162
2163 return so;
2164 }
2165
2166 static void
2167 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2168 struct vc4_compile *c)
2169 {
2170 int count = c->num_uniforms;
2171 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2172
2173 uinfo->count = count;
2174 uinfo->data = ralloc_array(shader, uint32_t, count);
2175 memcpy(uinfo->data, c->uniform_data,
2176 count * sizeof(*uinfo->data));
2177 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2178 memcpy(uinfo->contents, c->uniform_contents,
2179 count * sizeof(*uinfo->contents));
2180 uinfo->num_texture_samples = c->num_texture_samples;
2181 }
2182
2183 static struct vc4_compiled_shader *
2184 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2185 struct vc4_key *key)
2186 {
2187 struct hash_table *ht;
2188 uint32_t key_size;
2189 if (stage == QSTAGE_FRAG) {
2190 ht = vc4->fs_cache;
2191 key_size = sizeof(struct vc4_fs_key);
2192 } else {
2193 ht = vc4->vs_cache;
2194 key_size = sizeof(struct vc4_vs_key);
2195 }
2196
2197 struct vc4_compiled_shader *shader;
2198 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2199 if (entry)
2200 return entry->data;
2201
2202 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);
2203 shader = rzalloc(NULL, struct vc4_compiled_shader);
2204
2205 shader->program_id = vc4->next_compiled_program_id++;
2206 if (stage == QSTAGE_FRAG) {
2207 bool input_live[c->num_input_semantics];
2208 struct simple_node *node;
2209
2210 memset(input_live, 0, sizeof(input_live));
2211 foreach(node, &c->instructions) {
2212 struct qinst *inst = (struct qinst *)node;
2213 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
2214 if (inst->src[i].file == QFILE_VARY)
2215 input_live[inst->src[i].index] = true;
2216 }
2217 }
2218
2219 shader->input_semantics = ralloc_array(shader,
2220 struct vc4_varying_semantic,
2221 c->num_input_semantics);
2222
2223 for (int i = 0; i < c->num_input_semantics; i++) {
2224 struct vc4_varying_semantic *sem = &c->input_semantics[i];
2225
2226 if (!input_live[i])
2227 continue;
2228
2229 /* Skip non-VS-output inputs. */
2230 if (sem->semantic == (uint8_t)~0)
2231 continue;
2232
2233 if (sem->semantic == TGSI_SEMANTIC_COLOR ||
2234 sem->semantic == TGSI_SEMANTIC_BCOLOR) {
2235 shader->color_inputs |= (1 << shader->num_inputs);
2236 }
2237
2238 shader->input_semantics[shader->num_inputs] = *sem;
2239 shader->num_inputs++;
2240 }
2241 } else {
2242 shader->num_inputs = c->num_inputs;
2243
2244 shader->vattr_offsets[0] = 0;
2245 for (int i = 0; i < 8; i++) {
2246 shader->vattr_offsets[i + 1] =
2247 shader->vattr_offsets[i] + c->vattr_sizes[i];
2248
2249 if (c->vattr_sizes[i])
2250 shader->vattrs_live |= (1 << i);
2251 }
2252 }
2253
2254 copy_uniform_state_to_shader(shader, c);
2255 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,
2256 c->qpu_inst_count * sizeof(uint64_t),
2257 "code");
2258
2259 /* Copy the compiler UBO range state to the compiled shader, dropping
2260 * out arrays that were never referenced by an indirect load.
2261 *
2262 * (Note that QIR dead code elimination of an array access still
2263 * leaves that array alive, though)
2264 */
2265 if (c->num_ubo_ranges) {
2266 shader->num_ubo_ranges = c->num_ubo_ranges;
2267 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,
2268 c->num_ubo_ranges);
2269 uint32_t j = 0;
2270 for (int i = 0; i < c->ubo_ranges_array_size; i++) {
2271 struct vc4_compiler_ubo_range *range =
2272 &c->ubo_ranges[i];
2273 if (!range->used)
2274 continue;
2275
2276 shader->ubo_ranges[j].dst_offset = range->dst_offset;
2277 shader->ubo_ranges[j].src_offset = range->src_offset;
2278 shader->ubo_ranges[j].size = range->size;
2279 shader->ubo_size += c->ubo_ranges[i].size;
2280 j++;
2281 }
2282 }
2283
2284 qir_compile_destroy(c);
2285
2286 struct vc4_key *dup_key;
2287 dup_key = ralloc_size(shader, key_size);
2288 memcpy(dup_key, key, key_size);
2289 _mesa_hash_table_insert(ht, dup_key, shader);
2290
2291 return shader;
2292 }
2293
2294 static void
2295 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2296 struct vc4_texture_stateobj *texstate)
2297 {
2298 for (int i = 0; i < texstate->num_textures; i++) {
2299 struct pipe_sampler_view *sampler = texstate->textures[i];
2300 struct pipe_sampler_state *sampler_state =
2301 texstate->samplers[i];
2302
2303 if (sampler) {
2304 key->tex[i].format = sampler->format;
2305 key->tex[i].swizzle[0] = sampler->swizzle_r;
2306 key->tex[i].swizzle[1] = sampler->swizzle_g;
2307 key->tex[i].swizzle[2] = sampler->swizzle_b;
2308 key->tex[i].swizzle[3] = sampler->swizzle_a;
2309 key->tex[i].compare_mode = sampler_state->compare_mode;
2310 key->tex[i].compare_func = sampler_state->compare_func;
2311 key->tex[i].wrap_s = sampler_state->wrap_s;
2312 key->tex[i].wrap_t = sampler_state->wrap_t;
2313 }
2314 }
2315
2316 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2317 }
2318
2319 static void
2320 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2321 {
2322 struct vc4_fs_key local_key;
2323 struct vc4_fs_key *key = &local_key;
2324
2325 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2326 VC4_DIRTY_BLEND |
2327 VC4_DIRTY_FRAMEBUFFER |
2328 VC4_DIRTY_ZSA |
2329 VC4_DIRTY_RASTERIZER |
2330 VC4_DIRTY_FRAGTEX |
2331 VC4_DIRTY_TEXSTATE |
2332 VC4_DIRTY_UNCOMPILED_FS))) {
2333 return;
2334 }
2335
2336 memset(key, 0, sizeof(*key));
2337 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2338 key->base.shader_state = vc4->prog.bind_fs;
2339 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2340 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2341 prim_mode <= PIPE_PRIM_LINE_STRIP);
2342 key->blend = vc4->blend->rt[0];
2343 if (vc4->blend->logicop_enable) {
2344 key->logicop_func = vc4->blend->logicop_func;
2345 } else {
2346 key->logicop_func = PIPE_LOGICOP_COPY;
2347 }
2348 if (vc4->framebuffer.cbufs[0])
2349 key->color_format = vc4->framebuffer.cbufs[0]->format;
2350
2351 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2352 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2353 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2354 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2355 key->stencil_enabled);
2356 if (vc4->zsa->base.alpha.enabled) {
2357 key->alpha_test = true;
2358 key->alpha_test_func = vc4->zsa->base.alpha.func;
2359 }
2360
2361 if (key->is_points) {
2362 key->point_sprite_mask =
2363 vc4->rasterizer->base.sprite_coord_enable;
2364 key->point_coord_upper_left =
2365 (vc4->rasterizer->base.sprite_coord_mode ==
2366 PIPE_SPRITE_COORD_UPPER_LEFT);
2367 }
2368
2369 key->light_twoside = vc4->rasterizer->base.light_twoside;
2370
2371 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2372 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2373 if (vc4->prog.fs == old_fs)
2374 return;
2375
2376 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2377 if (vc4->rasterizer->base.flatshade &&
2378 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {
2379 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2380 }
2381 }
2382
2383 static void
2384 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2385 {
2386 struct vc4_vs_key local_key;
2387 struct vc4_vs_key *key = &local_key;
2388
2389 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2390 VC4_DIRTY_RASTERIZER |
2391 VC4_DIRTY_VERTTEX |
2392 VC4_DIRTY_TEXSTATE |
2393 VC4_DIRTY_VTXSTATE |
2394 VC4_DIRTY_UNCOMPILED_VS |
2395 VC4_DIRTY_COMPILED_FS))) {
2396 return;
2397 }
2398
2399 memset(key, 0, sizeof(*key));
2400 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2401 key->base.shader_state = vc4->prog.bind_vs;
2402 key->compiled_fs_id = vc4->prog.fs->program_id;
2403
2404 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2405 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2406
2407 key->per_vertex_point_size =
2408 (prim_mode == PIPE_PRIM_POINTS &&
2409 vc4->rasterizer->base.point_size_per_vertex);
2410
2411 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2412 key->is_coord = true;
2413 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2414 }
2415
2416 void
2417 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2418 {
2419 vc4_update_compiled_fs(vc4, prim_mode);
2420 vc4_update_compiled_vs(vc4, prim_mode);
2421 }
2422
2423 static uint32_t
2424 fs_cache_hash(const void *key)
2425 {
2426 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2427 }
2428
2429 static uint32_t
2430 vs_cache_hash(const void *key)
2431 {
2432 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2433 }
2434
2435 static bool
2436 fs_cache_compare(const void *key1, const void *key2)
2437 {
2438 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2439 }
2440
2441 static bool
2442 vs_cache_compare(const void *key1, const void *key2)
2443 {
2444 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2445 }
2446
2447 static void
2448 delete_from_cache_if_matches(struct hash_table *ht,
2449 struct hash_entry *entry,
2450 struct vc4_uncompiled_shader *so)
2451 {
2452 const struct vc4_key *key = entry->key;
2453
2454 if (key->shader_state == so) {
2455 struct vc4_compiled_shader *shader = entry->data;
2456 _mesa_hash_table_remove(ht, entry);
2457 vc4_bo_unreference(&shader->bo);
2458 ralloc_free(shader);
2459 }
2460 }
2461
2462 static void
2463 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2464 {
2465 struct vc4_context *vc4 = vc4_context(pctx);
2466 struct vc4_uncompiled_shader *so = hwcso;
2467
2468 struct hash_entry *entry;
2469 hash_table_foreach(vc4->fs_cache, entry)
2470 delete_from_cache_if_matches(vc4->fs_cache, entry, so);
2471 hash_table_foreach(vc4->vs_cache, entry)
2472 delete_from_cache_if_matches(vc4->vs_cache, entry, so);
2473
2474 if (so->twoside_tokens != so->base.tokens)
2475 free((void *)so->twoside_tokens);
2476 free((void *)so->base.tokens);
2477 free(so);
2478 }
2479
2480 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
2481 {
2482 switch (p_wrap) {
2483 case PIPE_TEX_WRAP_REPEAT:
2484 return 0;
2485 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2486 return 1;
2487 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2488 return 2;
2489 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2490 return 3;
2491 case PIPE_TEX_WRAP_CLAMP:
2492 return (using_nearest ? 1 : 3);
2493 default:
2494 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
2495 assert(!"not reached");
2496 return 0;
2497 }
2498 }
2499
2500 static void
2501 write_texture_p0(struct vc4_context *vc4,
2502 struct vc4_texture_stateobj *texstate,
2503 uint32_t unit)
2504 {
2505 struct pipe_sampler_view *texture = texstate->textures[unit];
2506 struct vc4_resource *rsc = vc4_resource(texture->texture);
2507
2508 cl_reloc(vc4, &vc4->uniforms, rsc->bo,
2509 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
2510 VC4_SET_FIELD(texture->u.tex.last_level -
2511 texture->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |
2512 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,
2513 VC4_TEX_P0_CMMODE) |
2514 VC4_SET_FIELD(rsc->vc4_format & 15, VC4_TEX_P0_TYPE));
2515 }
2516
2517 static void
2518 write_texture_p1(struct vc4_context *vc4,
2519 struct vc4_texture_stateobj *texstate,
2520 uint32_t unit)
2521 {
2522 struct pipe_sampler_view *texture = texstate->textures[unit];
2523 struct vc4_resource *rsc = vc4_resource(texture->texture);
2524 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2525 static const uint8_t minfilter_map[6] = {
2526 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
2527 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
2528 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
2529 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
2530 VC4_TEX_P1_MINFILT_NEAREST,
2531 VC4_TEX_P1_MINFILT_LINEAR,
2532 };
2533 static const uint32_t magfilter_map[] = {
2534 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
2535 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
2536 };
2537
2538 bool either_nearest =
2539 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
2540 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
2541
2542 cl_aligned_u32(&vc4->uniforms,
2543 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
2544 VC4_SET_FIELD(texture->texture->height0 & 2047,
2545 VC4_TEX_P1_HEIGHT) |
2546 VC4_SET_FIELD(texture->texture->width0 & 2047,
2547 VC4_TEX_P1_WIDTH) |
2548 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],
2549 VC4_TEX_P1_MAGFILT) |
2550 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +
2551 sampler->min_img_filter],
2552 VC4_TEX_P1_MINFILT) |
2553 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),
2554 VC4_TEX_P1_WRAP_S) |
2555 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),
2556 VC4_TEX_P1_WRAP_T));
2557 }
2558
2559 static void
2560 write_texture_p2(struct vc4_context *vc4,
2561 struct vc4_texture_stateobj *texstate,
2562 uint32_t data)
2563 {
2564 uint32_t unit = data & 0xffff;
2565 struct pipe_sampler_view *texture = texstate->textures[unit];
2566 struct vc4_resource *rsc = vc4_resource(texture->texture);
2567
2568 cl_aligned_u32(&vc4->uniforms,
2569 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,
2570 VC4_TEX_P2_PTYPE) |
2571 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |
2572 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));
2573 }
2574
2575
2576 #define SWIZ(x,y,z,w) { \
2577 UTIL_FORMAT_SWIZZLE_##x, \
2578 UTIL_FORMAT_SWIZZLE_##y, \
2579 UTIL_FORMAT_SWIZZLE_##z, \
2580 UTIL_FORMAT_SWIZZLE_##w \
2581 }
2582
2583 static void
2584 write_texture_border_color(struct vc4_context *vc4,
2585 struct vc4_texture_stateobj *texstate,
2586 uint32_t unit)
2587 {
2588 struct pipe_sampler_state *sampler = texstate->samplers[unit];
2589 struct pipe_sampler_view *texture = texstate->textures[unit];
2590 struct vc4_resource *rsc = vc4_resource(texture->texture);
2591 union util_color uc;
2592
2593 const struct util_format_description *tex_format_desc =
2594 util_format_description(texture->format);
2595
2596 float border_color[4];
2597 for (int i = 0; i < 4; i++)
2598 border_color[i] = sampler->border_color.f[i];
2599 if (util_format_is_srgb(texture->format)) {
2600 for (int i = 0; i < 3; i++)
2601 border_color[i] =
2602 util_format_linear_to_srgb_float(border_color[i]);
2603 }
2604
2605 /* Turn the border color into the layout of channels that it would
2606 * have when stored as texture contents.
2607 */
2608 float storage_color[4];
2609 util_format_unswizzle_4f(storage_color,
2610 border_color,
2611 tex_format_desc->swizzle);
2612
2613 /* Now, pack so that when the vc4_format-sampled texture contents are
2614 * replaced with our border color, the vc4_get_format_swizzle()
2615 * swizzling will get the right channels.
2616 */
2617 if (util_format_is_depth_or_stencil(texture->format)) {
2618 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,
2619 sampler->border_color.f[0]) << 8;
2620 } else {
2621 switch (rsc->vc4_format) {
2622 default:
2623 case VC4_TEXTURE_TYPE_RGBA8888:
2624 util_pack_color(storage_color,
2625 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);
2626 break;
2627 case VC4_TEXTURE_TYPE_RGBA4444:
2628 util_pack_color(storage_color,
2629 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);
2630 break;
2631 case VC4_TEXTURE_TYPE_RGB565:
2632 util_pack_color(storage_color,
2633 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2634 break;
2635 case VC4_TEXTURE_TYPE_ALPHA:
2636 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;
2637 break;
2638 case VC4_TEXTURE_TYPE_LUMALPHA:
2639 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |
2640 (float_to_ubyte(storage_color[0]) << 0));
2641 break;
2642 }
2643 }
2644
2645 cl_aligned_u32(&vc4->uniforms, uc.ui[0]);
2646 }
2647
2648 static uint32_t
2649 get_texrect_scale(struct vc4_texture_stateobj *texstate,
2650 enum quniform_contents contents,
2651 uint32_t data)
2652 {
2653 struct pipe_sampler_view *texture = texstate->textures[data];
2654 uint32_t dim;
2655
2656 if (contents == QUNIFORM_TEXRECT_SCALE_X)
2657 dim = texture->texture->width0;
2658 else
2659 dim = texture->texture->height0;
2660
2661 return fui(1.0f / dim);
2662 }
2663
2664 static struct vc4_bo *
2665 vc4_upload_ubo(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2666 const uint32_t *gallium_uniforms)
2667 {
2668 if (!shader->ubo_size)
2669 return NULL;
2670
2671 struct vc4_bo *ubo = vc4_bo_alloc(vc4->screen, shader->ubo_size, "ubo");
2672 uint32_t *data = vc4_bo_map(ubo);
2673 for (uint32_t i = 0; i < shader->num_ubo_ranges; i++) {
2674 memcpy(data + shader->ubo_ranges[i].dst_offset,
2675 gallium_uniforms + shader->ubo_ranges[i].src_offset,
2676 shader->ubo_ranges[i].size);
2677 }
2678
2679 return ubo;
2680 }
2681
2682 void
2683 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,
2684 struct vc4_constbuf_stateobj *cb,
2685 struct vc4_texture_stateobj *texstate)
2686 {
2687 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2688 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;
2689 struct vc4_bo *ubo = vc4_upload_ubo(vc4, shader, gallium_uniforms);
2690
2691 cl_ensure_space(&vc4->uniforms, (uinfo->count +
2692 uinfo->num_texture_samples) * 4);
2693
2694 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);
2695
2696 for (int i = 0; i < uinfo->count; i++) {
2697
2698 switch (uinfo->contents[i]) {
2699 case QUNIFORM_CONSTANT:
2700 cl_aligned_u32(&vc4->uniforms, uinfo->data[i]);
2701 break;
2702 case QUNIFORM_UNIFORM:
2703 cl_aligned_u32(&vc4->uniforms,
2704 gallium_uniforms[uinfo->data[i]]);
2705 break;
2706 case QUNIFORM_VIEWPORT_X_SCALE:
2707 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);
2708 break;
2709 case QUNIFORM_VIEWPORT_Y_SCALE:
2710 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);
2711 break;
2712
2713 case QUNIFORM_VIEWPORT_Z_OFFSET:
2714 cl_aligned_f(&vc4->uniforms, vc4->viewport.translate[2]);
2715 break;
2716 case QUNIFORM_VIEWPORT_Z_SCALE:
2717 cl_aligned_f(&vc4->uniforms, vc4->viewport.scale[2]);
2718 break;
2719
2720 case QUNIFORM_USER_CLIP_PLANE:
2721 cl_aligned_f(&vc4->uniforms,
2722 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);
2723 break;
2724
2725 case QUNIFORM_TEXTURE_CONFIG_P0:
2726 write_texture_p0(vc4, texstate, uinfo->data[i]);
2727 break;
2728
2729 case QUNIFORM_TEXTURE_CONFIG_P1:
2730 write_texture_p1(vc4, texstate, uinfo->data[i]);
2731 break;
2732
2733 case QUNIFORM_TEXTURE_CONFIG_P2:
2734 write_texture_p2(vc4, texstate, uinfo->data[i]);
2735 break;
2736
2737 case QUNIFORM_UBO_ADDR:
2738 cl_aligned_reloc(vc4, &vc4->uniforms, ubo, 0);
2739 break;
2740
2741 case QUNIFORM_TEXTURE_BORDER_COLOR:
2742 write_texture_border_color(vc4, texstate, uinfo->data[i]);
2743 break;
2744
2745 case QUNIFORM_TEXRECT_SCALE_X:
2746 case QUNIFORM_TEXRECT_SCALE_Y:
2747 cl_aligned_u32(&vc4->uniforms,
2748 get_texrect_scale(texstate,
2749 uinfo->contents[i],
2750 uinfo->data[i]));
2751 break;
2752
2753 case QUNIFORM_BLEND_CONST_COLOR:
2754 cl_aligned_f(&vc4->uniforms,
2755 CLAMP(vc4->blend_color.color[uinfo->data[i]], 0, 1));
2756 break;
2757
2758 case QUNIFORM_STENCIL:
2759 cl_aligned_u32(&vc4->uniforms,
2760 vc4->zsa->stencil_uniforms[uinfo->data[i]] |
2761 (uinfo->data[i] <= 1 ?
2762 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :
2763 0));
2764 break;
2765
2766 case QUNIFORM_ALPHA_REF:
2767 cl_aligned_f(&vc4->uniforms,
2768 vc4->zsa->base.alpha.ref_value);
2769 break;
2770 }
2771 #if 0
2772 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);
2773 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",
2774 shader, i, written_val, uif(written_val));
2775 #endif
2776 }
2777 }
2778
2779 static void
2780 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2781 {
2782 struct vc4_context *vc4 = vc4_context(pctx);
2783 vc4->prog.bind_fs = hwcso;
2784 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2785 }
2786
2787 static void
2788 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2789 {
2790 struct vc4_context *vc4 = vc4_context(pctx);
2791 vc4->prog.bind_vs = hwcso;
2792 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2793 }
2794
2795 void
2796 vc4_program_init(struct pipe_context *pctx)
2797 {
2798 struct vc4_context *vc4 = vc4_context(pctx);
2799
2800 pctx->create_vs_state = vc4_shader_state_create;
2801 pctx->delete_vs_state = vc4_shader_state_delete;
2802
2803 pctx->create_fs_state = vc4_shader_state_create;
2804 pctx->delete_fs_state = vc4_shader_state_delete;
2805
2806 pctx->bind_fs_state = vc4_fp_state_bind;
2807 pctx->bind_vs_state = vc4_vp_state_bind;
2808
2809 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2810 fs_cache_compare);
2811 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2812 vs_cache_compare);
2813 }
2814
2815 void
2816 vc4_program_fini(struct pipe_context *pctx)
2817 {
2818 struct vc4_context *vc4 = vc4_context(pctx);
2819
2820 struct hash_entry *entry;
2821 hash_table_foreach(vc4->fs_cache, entry) {
2822 struct vc4_compiled_shader *shader = entry->data;
2823 vc4_bo_unreference(&shader->bo);
2824 ralloc_free(shader);
2825 _mesa_hash_table_remove(vc4->fs_cache, entry);
2826 }
2827
2828 hash_table_foreach(vc4->vs_cache, entry) {
2829 struct vc4_compiled_shader *shader = entry->data;
2830 vc4_bo_unreference(&shader->bo);
2831 ralloc_free(shader);
2832 _mesa_hash_table_remove(vc4->vs_cache, entry);
2833 }
2834 }