src/ieee754/cordic/test/test_pipe.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Passive
   3 from nmigen.test.utils import FHDLTestCase
   4
   5 from ieee754.cordic.sin_cos_pipeline import CordicBasePipe
   6 from ieee754.cordic.pipe_data import CordicPipeSpec
   7 from python_sin_cos import run_cordic
   8 import unittest
   9 import math
  10 import random
  11
  12
  13 class SinCosTestCase(FHDLTestCase):
  14     def run_test(self, inputs, outputs, fracbits=8):
  15         m = Module()
  16         pspec = CordicPipeSpec(fracbits=fracbits)
  17         m.submodules.dut = dut = CordicBasePipe(pspec)
  18
  19         z = Signal(dut.p.data_i.z0.shape())
  20         z_valid = Signal()
  21         ready = Signal()
  22         x = Signal(dut.n.data_o.x.shape())
  23         y = Signal(dut.n.data_o.y.shape())
  24
  25         m.d.comb += [
  26             dut.p.data_i.z0.eq(z),
  27             dut.p.valid_i.eq(z_valid),
  28             dut.n.ready_i.eq(ready),
  29             x.eq(dut.n.data_o.x),
  30             y.eq(dut.n.data_o.y)]
  31
  32         sim = Simulator(m)
  33         sim.add_clock(1e-6)
  34
  35         def writer_process():
  36             yield Passive()
  37             for val in inputs:
  38                 yield z.eq(val)
  39                 yield z_valid.eq(1)
  40                 yield ready.eq(1)
  41                 yield
  42
  43         def reader_process():
  44             while True:
  45                 yield
  46                 vld = yield dut.n.valid_o
  47                 if vld:
  48                     try:
  49                         (sin, cos) = outputs.__next__()
  50                         result = yield x
  51                         msg = "cos: {}, expected {}".format(result, cos)
  52                         assert result == cos, msg
  53                         result = yield y
  54                         msg = "sin: {}, expected {}".format(result, sin)
  55                         assert result == sin, msg
  56
  57                     except StopIteration:
  58                         break
  59
  60
  61         sim.add_sync_process(writer_process)
  62         sim.add_sync_process(reader_process)
  63         with sim.write_vcd("pipeline.vcd", "pipeline.gtkw", traces=[
  64                 z, x, y]):
  65             sim.run()
  66
  67
  68     def test_rand(self):
  69         fracbits = 16
  70         M = (1 << fracbits)
  71         ZMAX = int(round(M * math.pi/2))
  72         inputs = []
  73         outputs = []
  74         for i in range(50):
  75             z = random.randrange(-ZMAX, ZMAX-1)
  76             (sin, cos) = run_cordic(z, fracbits=fracbits, log=False)
  77             inputs.append(z)
  78             outputs.append((sin, cos))
  79         self.run_test(iter(inputs), iter(outputs), fracbits=fracbits)
  80
  81
  82
  83 if __name__ == "__main__":
  84     unittest.main()