3a656459afece9735f0aa78e926f6661d0bfe104
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Elaboratable
6 from nmigen
.cli
import main
, verilog
8 from ieee754
.fpcommon
.fpbase
import FPNumBase
, FPNumBaseRecord
9 from ieee754
.fpcommon
.fpbase
import FPState
10 from ieee754
.fpcommon
.getop
import FPPipeContext
11 from .postnormalise
import FPNorm1Data
16 def __init__(self
, pspec
):
18 self
.z
= FPNumBaseRecord(width
, False, name
="z")
19 self
.ctx
= FPPipeContext(pspec
)
20 self
.muxid
= self
.ctx
.muxid
21 # pipeline bypass [data comes from specialcases]
22 self
.out_do_z
= Signal(reset_less
=True)
23 self
.oz
= Signal(width
, reset_less
=True)
26 ret
= [self
.z
.eq(i
.z
), self
.out_do_z
.eq(i
.out_do_z
), self
.oz
.eq(i
.oz
),
31 class FPRoundMod(Elaboratable
):
33 def __init__(self
, pspec
):
36 self
.out_z
= self
.ospec()
39 return FPNorm1Data(self
.pspec
)
42 return FPRoundData(self
.pspec
)
47 def setup(self
, m
, i
):
48 m
.submodules
.roundz
= self
49 m
.d
.comb
+= self
.i
.eq(i
)
51 def elaborate(self
, platform
):
53 m
.d
.comb
+= self
.out_z
.eq(self
.i
) # copies muxid, z, out_do_z
54 with m
.If(~self
.i
.out_do_z
): # bypass wasn't enabled
55 with m
.If(self
.i
.roundz
):
56 m
.d
.comb
+= self
.out_z
.z
.m
.eq(self
.i
.z
.m
+ 1) # mantissa up
57 with m
.If(self
.i
.z
.m
== self
.i
.z
.m1s
): # all 1s
59 m
.d
.comb
+= self
.out_z
.z
.e
.eq(self
.i
.z
.e
+ 1)
64 class FPRound(FPState
):
66 def __init__(self
, width
, id_wid
):
67 FPState
.__init
__(self
, "round")
68 self
.mod
= FPRoundMod(width
)
69 self
.out_z
= self
.ospec()
72 return self
.mod
.ispec()
75 return self
.mod
.ospec()
77 def setup(self
, m
, i
):
78 """ links module to inputs and outputs
83 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
84 m
.d
.sync
+= self
.out_z
.ctx
.eq(self
.mod
.o
.ctx
)
87 m
.next
= "corrections"