6b00762a33664eb508c8081b09aff7f5325cac2a
1 """IEEE754 Floating Point Multiplier Pipeline
3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.cli
import main
, verilog
10 from nmutil
.pipemodbase
import PipeModBase
11 from ieee754
.fpcommon
.fpbase
import FPNumBaseRecord
12 from ieee754
.fpcommon
.denorm
import FPSCData
13 from ieee754
.fpcommon
.getop
import FPPipeContext
14 from ieee754
.fpmul
.datastructs
import FPMulStage0Data
17 class FPMulStage0Mod(PipeModBase
):
19 def __init__(self
, pspec
):
20 super().__init
__(pspec
, "mul0")
23 return FPSCData(self
.pspec
, False)
26 return FPMulStage0Data(self
.pspec
)
28 def elaborate(self
, platform
):
32 # store intermediate tests (and zero-extended mantissas)
33 am0
= Signal(len(self
.i
.a
.m
)+1, reset_less
=True)
34 bm0
= Signal(len(self
.i
.b
.m
)+1, reset_less
=True)
35 comb
+= [ am0
.eq(Cat(self
.i
.a
.m
, 0)),
36 bm0
.eq(Cat(self
.i
.b
.m
, 0))
38 # same-sign (both negative or both positive) mul mantissas
39 comb
+= [self
.o
.z
.e
.eq(self
.i
.a
.e
+ self
.i
.b
.e
+ 1),
40 self
.o
.product
.eq(am0
* bm0
* 4),
41 self
.o
.z
.s
.eq(self
.i
.a
.s ^ self
.i
.b
.s
)
44 comb
+= self
.o
.oz
.eq(self
.i
.oz
)
45 comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
46 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)