82b881ca8bc03209674e537343ea23dc1fe50b98
1 """IEEE754 Floating Point Multiplier Pipeline
3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4 Copyright (C) 2019 Jake Lifshay
6 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=77
10 * scnorm - FPMulSpecialCasesDeNorm
11 * mulstages - FPMulstages
12 * normpack - FPNormToPack
14 scnorm - FPDIVSpecialCasesDeNorm ispec FPBaseData
17 StageChain: FPMULSpecialCasesMod,
21 mulstages - FPMulStages ispec FPSCData
22 --------- ospec FPPostCalcData
24 StageChain: FPMulStage0Mod
27 normpack - FPNormToPack ispec FPPostCalcData
28 -------- ospec FPPackData
30 StageChain: Norm1ModSingle,
35 This is the *current* stack. FPMulStage0Mod is where the actual
36 mantissa multiply takes place, which in the case of FP64 is a
37 single (massive) combinatorial block. This can be fixed by using
38 a multi-stage fixed-point multiplier pipeline, which was implemented
39 in #60: http://bugs.libre-riscv.org/show_bug.cgi?id=60
43 from nmigen
import Module
44 from nmigen
.cli
import main
, verilog
46 from nmutil
.singlepipe
import ControlBase
47 from nmutil
.concurrentunit
import ReservationStations
, num_bits
49 from ieee754
.fpcommon
.basedata
import FPBaseData
50 from ieee754
.fpcommon
.denorm
import FPSCData
51 from ieee754
.fpcommon
.pack
import FPPackData
52 from ieee754
.fpcommon
.normtopack
import FPNormToPack
53 from .specialcases
import FPMulSpecialCasesDeNorm
54 from .mulstages
import FPMulStages
55 from ieee754
.pipeline
import PipelineSpec
58 class FPMULBasePipe(ControlBase
):
59 def __init__(self
, pspec
):
60 ControlBase
.__init
__(self
)
61 self
.pipe1
= FPMulSpecialCasesDeNorm(pspec
)
62 self
.pipe2
= FPMulStages(pspec
)
63 self
.pipe3
= FPNormToPack(pspec
)
65 self
._eqs
= self
.connect([self
.pipe1
, self
.pipe2
, self
.pipe3
])
67 def elaborate(self
, platform
):
68 m
= ControlBase
.elaborate(self
, platform
)
69 m
.submodules
.scnorm
= self
.pipe1
70 m
.submodules
.mulstages
= self
.pipe2
71 m
.submodules
.normpack
= self
.pipe3
76 class FPMULMuxInOut(ReservationStations
):
77 """ Reservation-Station version of FPMUL pipeline.
79 * fan-in on inputs (an array of FPBaseData: a,b,mid)
80 * 2-stage multiplier pipeline
81 * fan-out on outputs (an array of FPPackData: z,mid)
83 Fan-in and Fan-out are combinatorial.
86 def __init__(self
, width
, num_rows
, op_wid
=0):
87 self
.id_wid
= num_bits(num_rows
)
89 self
.pspec
= PipelineSpec(width
, self
.id_wid
, self
.op_wid
)
90 self
.alu
= FPMULBasePipe(self
.pspec
)
91 ReservationStations
.__init
__(self
, num_rows
)