fec43fabeae7351a224528d6848f3ad32e0827f6
1 # IEEE Floating Point Multiplier
3 from nmigen
import Module
, Signal
, Cat
, Const
4 from nmigen
.cli
import main
, verilog
7 from ieee754
.fpcommon
.fpbase
import FPNumDecode
8 from nmutil
.singlepipe
import SimpleHandshake
, StageChain
10 from ieee754
.fpcommon
.fpbase
import FPState
, FPID
11 from ieee754
.fpcommon
.getop
import FPADDBaseData
12 from ieee754
.fpcommon
.denorm
import (FPSCData
, FPAddDeNormMod
)
15 class FPMulSpecialCasesMod
:
16 """ special cases: NaNs, infs, zeros, denormalised
17 see "Special Operations"
18 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
21 def __init__(self
, width
, id_wid
):
28 return FPADDBaseData(self
.width
, self
.id_wid
)
31 return FPSCData(self
.width
, self
.id_wid
)
33 def setup(self
, m
, i
):
34 """ links module to inputs and outputs
36 m
.submodules
.specialcases
= self
37 m
.d
.comb
+= self
.i
.eq(i
)
42 def elaborate(self
, platform
):
45 m
.submodules
.sc_out_z
= self
.o
.z
47 # decode: XXX really should move to separate stage
48 a1
= FPNumDecode(None, self
.width
)
49 b1
= FPNumDecode(None, self
.width
)
50 m
.submodules
.sc_decode_a
= a1
51 m
.submodules
.sc_decode_b
= b1
52 m
.d
.comb
+= [a1
.v
.eq(self
.i
.a
),
58 s_nomatch
= Signal(reset_less
=True)
59 m
.d
.comb
+= s_nomatch
.eq(a1
.s
!= b1
.s
)
61 m_match
= Signal(reset_less
=True)
62 m
.d
.comb
+= m_match
.eq(a1
.m
== b1
.m
)
64 e_match
= Signal(reset_less
=True)
65 m
.d
.comb
+= e_match
.eq(a1
.e
== b1
.e
)
67 aeqmb
= Signal(reset_less
=True)
68 m
.d
.comb
+= aeqmb
.eq(s_nomatch
& m_match
& e_match
)
70 obz
= Signal(reset_less
=True)
71 m
.d
.comb
+= obz
.eq(a1
.is_zero
& b1
.is_zero
)
73 sabx
= Signal(reset_less
=True) # sign a xor b (sabx, get it?)
74 m
.d
.comb
+= sabx
.eq(a1
.s ^ b1
.s
)
76 # if a is NaN or b is NaN return NaN
78 m
.d
.comb
+= self
.o
.out_do_z
.eq(1)
79 m
.d
.comb
+= self
.o
.z
.nan(1)
81 # if a is inf return inf (or NaN)
82 with m
.Elif(a1
.is_inf
):
83 m
.d
.comb
+= self
.o
.out_do_z
.eq(1)
84 m
.d
.comb
+= self
.o
.z
.inf(sabx
)
85 # b is zero return NaN
86 with m
.If(b1
.is_zero
):
87 m
.d
.comb
+= self
.o
.z
.nan(1)
89 # if b is inf return inf (or NaN)
90 with m
.Elif(b1
.is_inf
):
91 m
.d
.comb
+= self
.o
.out_do_z
.eq(1)
92 m
.d
.comb
+= self
.o
.z
.inf(sabx
)
93 # a is zero return NaN
94 with m
.If(a1
.is_zero
):
95 m
.d
.comb
+= self
.o
.z
.nan(1)
97 # if a is zero or b zero return signed-a/b
99 m
.d
.comb
+= self
.o
.out_do_z
.eq(1)
100 m
.d
.comb
+= self
.o
.z
.zero(sabx
)
102 # Denormalised Number checks next, so pass a/b data through
104 m
.d
.comb
+= self
.o
.out_do_z
.eq(0)
106 m
.d
.comb
+= self
.o
.oz
.eq(self
.o
.z
.v
)
107 m
.d
.comb
+= self
.o
.mid
.eq(self
.i
.mid
)
112 class FPMulSpecialCases(FPState
):
113 """ special cases: NaNs, infs, zeros, denormalised
114 NOTE: some of these are unique to add. see "Special Operations"
115 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
118 def __init__(self
, width
, id_wid
):
119 FPState
.__init
__(self
, "special_cases")
120 self
.mod
= FPAddSpecialCasesMod(width
)
121 self
.out_z
= self
.mod
.ospec()
122 self
.out_do_z
= Signal(reset_less
=True)
124 def setup(self
, m
, i
):
125 """ links module to inputs and outputs
127 self
.mod
.setup(m
, i
, self
.out_do_z
)
128 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
) # only take the output
129 m
.d
.sync
+= self
.out_z
.mid
.eq(self
.mod
.o
.mid
) # (and mid)
133 with m
.If(self
.out_do_z
):
136 m
.next
= "denormalise"
139 class FPMulSpecialCasesDeNorm(FPState
, SimpleHandshake
):
140 """ special cases: NaNs, infs, zeros, denormalised
143 def __init__(self
, width
, id_wid
):
144 FPState
.__init
__(self
, "special_cases")
147 SimpleHandshake
.__init
__(self
, self
) # pipe is its own stage
148 self
.out
= self
.ospec()
151 return FPADDBaseData(self
.width
, self
.id_wid
) # SpecialCases ispec
154 return FPSCData(self
.width
, self
.id_wid
) # DeNorm ospec
156 def setup(self
, m
, i
):
157 """ links module to inputs and outputs
159 smod
= FPMulSpecialCasesMod(self
.width
, self
.id_wid
)
160 dmod
= FPAddDeNormMod(self
.width
, self
.id_wid
)
162 chain
= StageChain([smod
, dmod
])
165 # only needed for break-out (early-out)
166 # self.out_do_z = smod.o.out_do_z
170 def process(self
, i
):
174 # for break-out (early-out)
175 #with m.If(self.out_do_z):
178 m
.d
.sync
+= self
.out
.eq(self
.process(None))