src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use PartitionedSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 #from ieee754.part_cmp.equal_ortree import PartitionedEq
  21 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  22 from ieee754.part_mul_add.partpoints import make_partition
  23 from operator import or_, xor, and_, not_
  24
  25 from nmigen import (Signal,
  26                     )
  27
  28 def getsig(op1):
  29     if isinstance(op1, PartitionedSignal):
  30         op1 = op1.sig
  31     return op1
  32
  33 def applyop(op1, op2, op):
  34     return op(getsig(op1), getsig(op2))
  35
  36
  37 class PartitionedSignal:
  38     def __init__(self, mask, *args, **kwargs):
  39         self.sig = Signal(*args, **kwargs)
  40         width = self.sig.shape()[0] # get signal width
  41         self.partpoints = make_partition(mask, width) # create partition points
  42         self.modnames = {}
  43         for name in ['add', 'eq', 'gt', 'ge']:
  44             self.modnames[name] = 0
  45
  46     def set_module(self, m):
  47         self.m = m
  48
  49     def get_modname(self, category):
  50         self.modnames[category] += 1
  51         return "%s%d" % (category, self.modnames[category])
  52
  53     def eq(self, val):
  54         return self.sig.eq(getsig(val))
  55
  56     # unary ops that do not require partitioning
  57
  58     def __invert__(self):
  59         return ~self.sig
  60
  61     # unary ops that require partitioning
  62
  63     def __neg__(self):
  64         # TODO use PartitionedAdder for this, with a "neg" mode?
  65         return Operator("-", [self])
  66
  67     # binary ops that don't require partitioning
  68
  69     def __and__(self, other):
  70         return applyop(self, other, and_)
  71
  72     def __rand__(self, other):
  73         return applyop(other, self, and_)
  74
  75     def __or__(self, other):
  76         return applyop(self, other, or_)
  77
  78     def __ror__(self, other):
  79         return applyop(other, self, or_)
  80
  81     def __xor__(self, other):
  82         return applyop(self, other, xor)
  83
  84     def __rxor__(self, other):
  85         return applyop(other, self, xor)
  86
  87     # binary ops that need partitioning
  88
  89     # TODO: detect if the 2nd operand is a Const, a Signal or a
  90     # PartitionedSignal.  if it's a Const or a Signal, a global shift
  91     # can occur.  if it's a PartitionedSignal, that's much more interesting.
  92     def __lshift__(self, other):
  93         return Operator("<<", [self, other])
  94     def __rlshift__(self, other):
  95         return Operator("<<", [other, self])
  96     def __rshift__(self, other):
  97         return Operator(">>", [self, other])
  98     def __rrshift__(self, other):
  99         return Operator(">>", [other, self])
 100
 101     def add_op(self, op1, op2):
 102         op1 = getsig(op1)
 103         op2 = getsig(op2)
 104         shape = op1.shape()
 105         pa = PartitionedAdder(shape[0], self.partpoints)
 106         setattr(self.m.submodules, self.get_modname('add'), pa)
 107         comb = self.m.d.comb
 108         comb += pa.a.eq(op1)
 109         comb += pa.b.eq(op2)
 110         return pa.output
 111
 112     def __add__(self, other):
 113         return self.add_op(self, other)
 114
 115     def addc(self, other, carry):
 116         shape = self.sig.shape()
 117         pa = PartitionedAdder(shape[0], self.partpoints)
 118         setattr(self.m.submodules, self.get_modname('add'), pa)
 119         comb = self.m.d.comb
 120         comb += pa.a.eq(self.sig)
 121         comb += pa.carry_in.eq(carry)
 122         if isinstance(other, PartitionedSignal):
 123             comb += pa.b.eq(other.sig)
 124         else:
 125             comb += pa.b.eq(other)
 126         return (pa.output, pa.carry_out)
 127
 128     def __radd__(self, other):
 129         return self.add_op(other, self)
 130
 131     def __sub__(self, other):
 132         return self.sub_op(self, other) # TODO, subop
 133     def __rsub__(self, other):
 134         return self.sub_op(other, self) # TODO, subop
 135
 136     def __mul__(self, other):
 137         return Operator("*", [self, other])
 138     def __rmul__(self, other):
 139         return Operator("*", [other, self])
 140
 141     def __check_divisor(self):
 142         width, signed = self.shape()
 143         if signed:
 144             # Python's division semantics and Verilog's division semantics
 145             # differ for negative divisors (Python uses div/mod, Verilog
 146             # uses quo/rem); for now, avoid the issue
 147             # completely by prohibiting such division operations.
 148             raise NotImplementedError(
 149                     "Division by a signed value is not supported")
 150     def __mod__(self, other):
 151         other = Value.cast(other)
 152         other.__check_divisor()
 153         return Operator("%", [self, other])
 154     def __rmod__(self, other):
 155         self.__check_divisor()
 156         return Operator("%", [other, self])
 157     def __floordiv__(self, other):
 158         other = Value.cast(other)
 159         other.__check_divisor()
 160         return Operator("//", [self, other])
 161     def __rfloordiv__(self, other):
 162         self.__check_divisor()
 163         return Operator("//", [other, self])
 164
 165     def __lshift__(self, other):
 166         return Operator("<<", [self, other])
 167     def __rlshift__(self, other):
 168         return Operator("<<", [other, self])
 169     def __rshift__(self, other):
 170         return Operator(">>", [self, other])
 171
 172     # binary comparison ops that need partitioning
 173
 174     def _compare(self, width, op1, op2, opname, optype):
 175         #print (opname, op1, op2)
 176         pa = PartitionedEqGtGe(width, self.partpoints)
 177         setattr(self.m.submodules, self.get_modname(opname), pa)
 178         comb = self.m.d.comb
 179         comb += pa.opcode.eq(optype) # set opcode
 180         if isinstance(op1, PartitionedSignal):
 181             comb += pa.a.eq(op1.sig)
 182         else:
 183             comb += pa.a.eq(op1)
 184         if isinstance(op2, PartitionedSignal):
 185             comb += pa.b.eq(op2.sig)
 186         else:
 187             comb += pa.b.eq(op2)
 188         return pa.output
 189
 190     def __eq__(self, other):
 191         width = self.sig.shape()[0]
 192         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 193
 194     def __ne__(self, other):
 195         width = self.sig.shape()[0]
 196         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 197         ne = Signal(eq.width)
 198         self.m.d.comb += ne.eq(~eq)
 199         return ne
 200
 201     def __gt__(self, other):
 202         width = self.sig.shape()[0]
 203         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 204
 205     def __lt__(self, other):
 206         width = self.sig.shape()[0]
 207         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 208
 209     def __ge__(self, other):
 210         width = self.sig.shape()[0]
 211         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 212
 213     def __le__(self, other):
 214         width = self.sig.shape()[0]
 215         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 216
 217     # useful operators
 218
 219     def bool(self):
 220         """Conversion to boolean.
 221
 222         Returns
 223         -------
 224         Value, out
 225             ``1`` if any bits are set, ``0`` otherwise.
 226         """
 227         return Operator("b", [self])
 228
 229     def any(self):
 230         """Check if any bits are ``1``.
 231
 232         Returns
 233         -------
 234         Value, out
 235             ``1`` if any bits are set, ``0`` otherwise.
 236         """
 237         return Operator("r|", [self])
 238
 239     def all(self):
 240         """Check if all bits are ``1``.
 241
 242         Returns
 243         -------
 244         Value, out
 245             ``1`` if all bits are set, ``0`` otherwise.
 246         """
 247         return Operator("r&", [self])
 248
 249     def xor(self):
 250         """Compute pairwise exclusive-or of every bit.
 251
 252         Returns
 253         -------
 254         Value, out
 255             ``1`` if an odd number of bits are set, ``0`` if an
 256                   even number of bits are set.
 257         """
 258         return Operator("r^", [self])
 259
 260     def implies(premise, conclusion):
 261         """Implication.
 262
 263         Returns
 264         -------
 265         Value, out
 266             ``0`` if ``premise`` is true and ``conclusion`` is not,
 267             ``1`` otherwise.
 268         """
 269         return ~premise | conclusion
 270
 271