src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use SimdSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  21 from ieee754.part_bits.xor import PartitionedXOR
  22 from ieee754.part_bits.bool import PartitionedBool
  23 from ieee754.part_bits.all import PartitionedAll
  24 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
  25 from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
  26 from ieee754.part_mul_add.partpoints import make_partition2, PartitionPoints
  27 from ieee754.part_mux.part_mux import PMux
  28 from ieee754.part_ass.passign import PAssign
  29 from ieee754.part_cat.pcat import PCat
  30 from ieee754.part_repl.prepl import PRepl
  31 from ieee754.part.simd_scope import SimdScope
  32 from ieee754.part.layout_experiment import layout
  33 from operator import or_, xor, and_, not_
  34
  35 from nmigen import (Signal, Const, Cat)
  36 from nmigen.hdl.ast import UserValue, Shape
  37
  38
  39 def getsig(op1):
  40     if isinstance(op1, SimdSignal):
  41         op1 = op1.sig
  42     return op1
  43
  44
  45 def applyop(op1, op2, op):
  46     if isinstance(op1, SimdSignal):
  47         result = SimdSignal.like(op1)
  48     else:
  49         result = SimdSignal.like(op2)
  50     result.m.d.comb += result.sig.eq(op(getsig(op1), getsig(op2)))
  51     return result
  52
  53
  54 global modnames
  55 modnames = {}
  56 # for sub-modules to be created on-demand. Mux is done slightly
  57 # differently (has its own global)
  58 for name in ['add', 'eq', 'gt', 'ge', 'ls', 'xor', 'bool', 'all']:
  59     modnames[name] = 0
  60
  61
  62 def get_runlengths(pbit, size):
  63     res = []
  64     count = 1
  65     # identify where the 1s are, which indicates "start of a new partition"
  66     # we want a list of the lengths of all partitions
  67     for i in range(size):
  68         if pbit & (1 << i):  # it's a 1: ends old partition, starts new
  69             res.append(count)  # add partition
  70             count = 1  # start again
  71         else:
  72             count += 1
  73     # end reached, add whatever is left. could have done this by creating
  74     # "fake" extra bit on the partitions, but hey
  75     res.append(count)
  76
  77     return res
  78
  79
  80 # Prototype https://bugs.libre-soc.org/show_bug.cgi?id=713#c53
  81 # this provides a "compatibility" layer with existing SimdSignal
  82 # behaviour.  the idea is that this interface defines which "combinations"
  83 # of partition selections are relevant, and as an added bonus it says
  84 # which partition lanes are completely irrelevant (padding, blank).
  85 class PartType:  # TODO decide name
  86     def __init__(self, psig):
  87         self.psig = psig
  88
  89     def get_mask(self):
  90         return list(self.psig.partpoints.values())
  91
  92     def get_switch(self):
  93         return Cat(self.get_mask())
  94
  95     def get_cases(self):
  96         return range(1 << len(self.get_mask()))
  97
  98     def get_num_elements(self, pbit):
  99         keys = list(self.psig.partpoints.keys())
 100         return len(get_runlengths(pbit, len(keys)))
 101
 102     def get_el_range(self, pbit, el_num):
 103         """based on the element number and the current elwid/pbit (case)
 104         return the range start/end of the element within its underlying signal
 105         this function is not at all designed to be efficient.
 106         """
 107         keys = list(self.psig.partpoints.keys())
 108         runs = get_runlengths(pbit, len(keys))
 109         keys = [0] + keys + [len(self.psig.sig)]
 110         y = 0
 111         for i in range(el_num):
 112             numparts = runs[i]
 113             y += numparts
 114         numparts = runs[el_num]
 115         return range(keys[y], keys[y+numparts])
 116
 117     @property
 118     def blanklanes(self):
 119         return 0
 120
 121
 122 # this one would be an elwidth version
 123 # see https://bugs.libre-soc.org/show_bug.cgi?id=713#c34
 124 # it requires an "adapter" which is the layout() function
 125 # where the PartitionPoints was *created* by the layout()
 126 # function and this class then "understands" the relationship
 127 # between elwidth and the PartitionPoints that were created
 128 # by layout()
 129 class ElwidPartType:  # TODO decide name
 130     def __init__(self, psig):
 131         self.psig = psig
 132
 133     def get_mask(self):
 134         return list(self.psig._shape.partpoints.values())  # i think
 135
 136     def get_switch(self):
 137         return self.psig.scope.elwid       # switch on elwid: match get_cases()
 138
 139     def get_cases(self):
 140         return self.psig._shape.bitp.keys()  # all possible values of elwid
 141
 142     @property
 143     def blanklanes(self):
 144         return self.psig.shape.blankmask
 145
 146
 147 # declares priority of the SimdShape
 148 PRIORITY_FIXED = 0b01
 149 PRIORITY_ELWID = 0b10
 150 PRIORITY_BOTH  = 0b11
 151
 152 class SimdShape(Shape):
 153     """a SIMD variant of Shape. supports:
 154     * fixed overall width with variable (maxed-out) element lengths
 155     * fixed element widths with overall size auto-determined
 156     * both fixed overall width and fixed element widths
 157
 158     Documentation / Analysis:
 159     https://libre-soc.org/3d_gpu/architecture/dynamic_simd/shape/
 160
 161     naming is preserved to be compatible with Shape(): the (calculated *or*
 162     given) fixed_width is *explicitly* passed through as Shape.width
 163     in order to ensure downcasting works as expected.
 164
 165     a mode flag records what behaviour is required for arithmetic operators.
 166     see wiki documentation: it's... complicated.
 167     """
 168
 169     def __init__(self, scope, width=None,  # this is actually widths_at_elwid
 170                  signed=False,
 171                  fixed_width=None):  # fixed overall width
 172         # record the mode and scope
 173         self.scope = scope
 174         widths_at_elwid = width
 175         self.mode_flag = 0
 176         # when both of these are set it creates mode_flag=PRIORITY_BOTH
 177         # otherwise creates a priority of either FIXED width or ELWIDs
 178         if fixed_width is not None:
 179             self.mode_flag |= PRIORITY_FIXED
 180         if widths_at_elwid is not None:
 181             self.mode_flag |= PRIORITY_ELWID
 182
 183         print("SimdShape width", width, "fixed_width", fixed_width)
 184         # this check is done inside layout but do it again here anyway
 185         assert fixed_width != None or widths_at_elwid != None, \
 186             "both width (widths_at_elwid) and fixed_width cannot be None"
 187         (pp, bitp, lpoints, bmask, fixed_width, lane_shapes, part_wid) = \
 188             layout(scope.elwid,
 189                    scope.vec_el_counts,
 190                    widths_at_elwid,
 191                    fixed_width)
 192         self.partpoints = pp
 193         self.bitp = bitp        # binary values for partpoints at each elwidth
 194         self.lpoints = lpoints  # layout ranges
 195         self.blankmask = bmask  # blanking mask (partitions always padding)
 196         self.partwid = part_wid  # smallest alignment start point for elements
 197         self.lane_shapes = lane_shapes
 198
 199         # pass through the calculated width to Shape() so that when/if
 200         # objects using this Shape are downcast, they know exactly how to
 201         # get *all* bits and need know absolutely nothing about SIMD at all
 202         Shape.__init__(self, fixed_width, signed)
 203
 204     def __mul__(self, other):
 205         if isinstance(other, int):
 206             # for integer multiply, by a nice coincidence it does not
 207             # matter if the LHS is PRIORITY_FIXED or PRIORITY_ELWID.
 208             # however the priority has to be preserved.
 209             fixed_width = None
 210             lane_shapes = None
 211
 212             # first, check if fixed_width is needed (if originally,
 213             # self was constructed with a fixed_width=None we must
 214             # *return* another SimdShape with a fixed_width=None)
 215             if self.mode_flag & PRIORITY_FIXED:
 216                 fixed_width = self.width * other
 217
 218             # likewise for lane elwidths: if, originally, self was constructed
 219             # with [widths_at_elwidth==lane_shapes==]width not None,
 220             # the return result also has to set up explicit lane_shapes
 221             if self.mode_flag & PRIORITY_ELWID:
 222                 lane_shapes = {k: v * other for k, v in self.lane_shapes}
 223
 224             # wheww, got everything.
 225             return SimdShape(self.scope,              # same scope
 226                              width=lane_shapes,       # widths_at_elwid
 227                              signed=self.signed,      # same sign? hmmm XXX
 228                              fixed_width=fixed_width) # overall width
 229         else:
 230             raise NotImplementedError(
 231                 f"Multiplying a SimdShape by {type(other)} isn't implemented")
 232
 233             # TODO (and go over examples, sigh).  this is deliberately *after*
 234             # the raise NotImplementedError because it needs review.
 235
 236             # also probably TODO: potentially the other argument could be
 237             # a Shape() not a SimdShape().  sigh.
 238
 239             # for SimdShape-to-SimdShape multiply, the rules are slightly
 240             # different: both sides have to be PRIORITY_FIXED for a
 241             # PRIORITY_FIXED result to be returned.  if either (or both)
 242             # of the LHS and RHS were given elwidths (lane_shapes != None)
 243             # then tough luck: the return result is still PRIORITY_ELWID.
 244             # TODO: review that.  it *might* be the case (again, due to
 245             # a coincidence of multiply, that when PRIORITY_BOTH is set
 246             # it is possible to return a PRIORITY_BOTH result. but..
 247             # it is unlikely)
 248
 249             fixed_width = None
 250             lane_shapes = None
 251
 252             # first, check if this is fixed_width mode.  this is *only*
 253             # possible if *both* LHS *and* RHS are PRIORITY_FIXED.
 254             if (self.mode_flag == PRIORITY_FIXED and
 255                 other.mode_flag == PRIORITY_FIXED):
 256                 fixed_width = self.width * other.width
 257             else:
 258                 # (XXX assume other is SimdShape) - when PRIORITY_ELWID
 259                 # the result *has* to be a PRIORITY_ELWID (FIXED is *IGNORED*)
 260                 # use *either* the computed *or* the given lane_shapes
 261                 lane_shapes = {k: v * other.lane_shapes[k] \
 262                                   for k, v in self.lane_shapes}
 263
 264             # wheww, got everything.
 265             return SimdShape(self.scope,              # same scope
 266                              width=lane_shapes,       # widths_at_elwid
 267                              signed=self.signed,      # same sign? hmmm XXX
 268                              fixed_width=fixed_width) # overall width
 269
 270
 271     def __rmul__(self, other):
 272         return self.__mul__(other)
 273
 274     def __add__(self, other):
 275         if isinstance(other, int):
 276             lane_shapes = {k: v + other for k, v in self.lane_shapes}
 277             return SimdShape(self.scope, lane_shapes, signed=self.signed)
 278         elif isinstance(other, SimdShape):
 279             assert other.scope is self.scope, "scope mismatch"
 280             o = other.lane_shapes
 281             lane_shapes = {k: v + o[k] for k, v in self.lane_shapes}
 282             # XXX not correct, we need a width-hint, not an overwrite
 283             # lane_shapes argument...
 284             return SimdShape(self.scope, lane_shapes, signed=self.signed,
 285                              fixed_width=self.width + other.width)
 286         else:
 287             raise NotImplementedError(
 288                 f"Adding a SimdShape to {type(other)} isn't implemented")
 289
 290     def __radd__(self, other):
 291         return self.__add__(other)
 292
 293
 294 class SimdSignal(UserValue):
 295     # XXX ################################################### XXX
 296     # XXX Keep these functions in the same order as ast.Value XXX
 297     # XXX ################################################### XXX
 298     def __init__(self, mask, shape=None, *args,
 299                  src_loc_at=0, fixed_width=None, **kwargs):
 300         super().__init__(src_loc_at=src_loc_at)
 301         print("SimdSignal shape", shape)
 302         # create partition points
 303         if isinstance(mask, SimdScope):  # mask parameter is a SimdScope
 304             self.scope = mask
 305             self.ptype = ElwidPartType(self)
 306             # adapt shape to a SimdShape
 307             if not isinstance(shape, SimdShape):
 308                 shape = SimdShape(self.scope, shape, fixed_width=fixed_width)
 309             self._shape = shape
 310             self.sig = Signal(shape, *args, **kwargs)
 311             # get partpoints from SimdShape
 312             self.partpoints = shape.partpoints
 313         else:
 314             self.sig = Signal(shape, *args, **kwargs)
 315             width = len(self.sig)  # get signal width
 316             if isinstance(mask, PartitionPoints):
 317                 self.partpoints = mask
 318             else:
 319                 self.partpoints = make_partition2(mask, width)
 320             self.ptype = PartType(self)
 321
 322     def set_module(self, m):
 323         self.m = m
 324
 325     def get_modname(self, category):
 326         modnames[category] += 1
 327         return "%s_%d" % (category, modnames[category])
 328
 329     @staticmethod
 330     def like(other, *args, **kwargs):
 331         """Builds a new SimdSignal with the same PartitionPoints and
 332         Signal properties as the other"""
 333         result = SimdSignal(PartitionPoints(other.partpoints))
 334         result.sig = Signal.like(other.sig, *args, **kwargs)
 335         result.m = other.m
 336         return result
 337
 338     def lower(self):
 339         return self.sig
 340
 341     # nmigen-redirected constructs (Mux, Cat, Switch, Assign)
 342
 343     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=716
 344     # def __Part__(self, offset, width, stride=1, *, src_loc_at=0):
 345         raise NotImplementedError("TODO: implement as "
 346                                   "(self>>(offset*stride)[:width]")
 347     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=716
 348
 349     def __Slice__(self, start, stop, *, src_loc_at=0):
 350         # NO.  Swizzled shall NOT be deployed, it violates
 351         # Project Development Practices
 352         raise NotImplementedError("TODO: need PartitionedSlice")
 353
 354     def __Repl__(self, count, *, src_loc_at=0):
 355         return PRepl(self.m, self, count, self.ptype)
 356
 357     def __Cat__(self, *args, src_loc_at=0):
 358         print("partsig cat", self, args)
 359         # TODO: need SwizzledSimdValue-aware Cat
 360         args = [self] + list(args)
 361         for sig in args:
 362             assert isinstance(sig, SimdSignal), \
 363                 "All SimdSignal.__Cat__ arguments must be " \
 364                 "a SimdSignal. %s is not." % repr(sig)
 365         return PCat(self.m, args, self.ptype)
 366
 367     def __Mux__(self, val1, val2):
 368         # print ("partsig mux", self, val1, val2)
 369         assert len(val1) == len(val2), \
 370             "SimdSignal width sources must be the same " \
 371             "val1 == %d, val2 == %d" % (len(val1), len(val2))
 372         return PMux(self.m, self.partpoints, self, val1, val2, self.ptype)
 373
 374     def __Assign__(self, val, *, src_loc_at=0):
 375         print("partsig assign", self, val)
 376         # this is a truly awful hack, outlined here:
 377         # https://bugs.libre-soc.org/show_bug.cgi?id=731#c13
 378         # during the period between constructing Simd-aware sub-modules
 379         # and the elaborate() being called on them there is a window of
 380         # opportunity to indicate which of those submodules is LHS and
 381         # which is RHS. manic laughter is permitted.  *gibber*.
 382         if hasattr(self, "_hack_submodule"):
 383             self._hack_submodule.set_lhs_mode(True)
 384         if hasattr(val, "_hack_submodule"):
 385             val._hack_submodule.set_lhs_mode(False)
 386         return PAssign(self.m, self, val, self.ptype)
 387
 388     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=458
 389     # def __Switch__(self, cases, *, src_loc=None, src_loc_at=0,
 390     #                               case_src_locs={}):
 391
 392     # no override needed, Value.__bool__ sufficient
 393     # def __bool__(self):
 394
 395     # unary ops that do not require partitioning
 396
 397     def __invert__(self):
 398         result = SimdSignal.like(self)
 399         self.m.d.comb += result.sig.eq(~self.sig)
 400         return result
 401
 402     # unary ops that require partitioning
 403
 404     def __neg__(self):
 405         z = Const(0, len(self.sig))
 406         result, _ = self.sub_op(z, self)
 407         return result
 408
 409     # binary ops that need partitioning
 410
 411     def add_op(self, op1, op2, carry):
 412         op1 = getsig(op1)
 413         op2 = getsig(op2)
 414         pa = PartitionedAdder(len(op1), self.partpoints)
 415         setattr(self.m.submodules, self.get_modname('add'), pa)
 416         comb = self.m.d.comb
 417         comb += pa.a.eq(op1)
 418         comb += pa.b.eq(op2)
 419         comb += pa.carry_in.eq(carry)
 420         result = SimdSignal.like(self)
 421         comb += result.sig.eq(pa.output)
 422         return result, pa.carry_out
 423
 424     def sub_op(self, op1, op2, carry=~0):
 425         op1 = getsig(op1)
 426         op2 = getsig(op2)
 427         pa = PartitionedAdder(len(op1), self.partpoints)
 428         setattr(self.m.submodules, self.get_modname('add'), pa)
 429         comb = self.m.d.comb
 430         comb += pa.a.eq(op1)
 431         comb += pa.b.eq(~op2)
 432         comb += pa.carry_in.eq(carry)
 433         result = SimdSignal.like(self)
 434         comb += result.sig.eq(pa.output)
 435         return result, pa.carry_out
 436
 437     def __add__(self, other):
 438         result, _ = self.add_op(self, other, carry=0)
 439         return result
 440
 441     def __radd__(self, other):
 442         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 443         result, _ = self.add_op(other, self)
 444         return result
 445
 446     def __sub__(self, other):
 447         result, _ = self.sub_op(self, other)
 448         return result
 449
 450     def __rsub__(self, other):
 451         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 452         result, _ = self.sub_op(other, self)
 453         return result
 454
 455     def __mul__(self, other):
 456         raise NotImplementedError  # too complicated at the moment
 457         return Operator("*", [self, other])
 458
 459     def __rmul__(self, other):
 460         raise NotImplementedError  # too complicated at the moment
 461         return Operator("*", [other, self])
 462
 463     # not needed: same as Value.__check_divisor
 464     # def __check_divisor(self):
 465
 466     def __mod__(self, other):
 467         raise NotImplementedError
 468         other = Value.cast(other)
 469         other.__check_divisor()
 470         return Operator("%", [self, other])
 471
 472     def __rmod__(self, other):
 473         raise NotImplementedError
 474         self.__check_divisor()
 475         return Operator("%", [other, self])
 476
 477     def __floordiv__(self, other):
 478         raise NotImplementedError
 479         other = Value.cast(other)
 480         other.__check_divisor()
 481         return Operator("//", [self, other])
 482
 483     def __rfloordiv__(self, other):
 484         raise NotImplementedError
 485         self.__check_divisor()
 486         return Operator("//", [other, self])
 487
 488     # not needed: same as Value.__check_shamt
 489     # def __check_shamt(self):
 490
 491     # TODO: detect if the 2nd operand is a Const, a Signal or a
 492     # SimdSignal.  if it's a Const or a Signal, a global shift
 493     # can occur.  if it's a SimdSignal, that's much more interesting.
 494     def ls_op(self, op1, op2, carry, shr_flag=0):
 495         op1 = getsig(op1)
 496         if isinstance(op2, Const) or isinstance(op2, Signal):
 497             scalar = True
 498             pa = PartitionedScalarShift(len(op1), self.partpoints)
 499         else:
 500             scalar = False
 501             op2 = getsig(op2)
 502             pa = PartitionedDynamicShift(len(op1), self.partpoints)
 503         # else:
 504         #   TODO: case where the *shifter* is a SimdSignal but
 505         #   the thing *being* Shifted is a scalar (Signal, expression)
 506         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 507         setattr(self.m.submodules, self.get_modname('ls'), pa)
 508         comb = self.m.d.comb
 509         if scalar:
 510             comb += pa.data.eq(op1)
 511             comb += pa.shifter.eq(op2)
 512             comb += pa.shift_right.eq(shr_flag)
 513         else:
 514             comb += pa.a.eq(op1)
 515             comb += pa.b.eq(op2)
 516             comb += pa.shift_right.eq(shr_flag)
 517         # XXX TODO: carry-in, carry-out (for arithmetic shift)
 518         #comb += pa.carry_in.eq(carry)
 519         return (pa.output, 0)
 520
 521     def __lshift__(self, other):
 522         z = Const(0, len(self.partpoints)+1)
 523         result, _ = self.ls_op(self, other, carry=z)  # TODO, carry
 524         return result
 525
 526     def __rlshift__(self, other):
 527         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 528         raise NotImplementedError
 529         return Operator("<<", [other, self])
 530
 531     def __rshift__(self, other):
 532         z = Const(0, len(self.partpoints)+1)
 533         result, _ = self.ls_op(self, other, carry=z, shr_flag=1)  # TODO, carry
 534         return result
 535
 536     def __rrshift__(self, other):
 537         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 538         raise NotImplementedError
 539         return Operator(">>", [other, self])
 540
 541     # binary ops that don't require partitioning
 542
 543     def __and__(self, other):
 544         return applyop(self, other, and_)
 545
 546     def __rand__(self, other):
 547         return applyop(other, self, and_)
 548
 549     def __or__(self, other):
 550         return applyop(self, other, or_)
 551
 552     def __ror__(self, other):
 553         return applyop(other, self, or_)
 554
 555     def __xor__(self, other):
 556         return applyop(self, other, xor)
 557
 558     def __rxor__(self, other):
 559         return applyop(other, self, xor)
 560
 561     # binary comparison ops that need partitioning
 562
 563     def _compare(self, width, op1, op2, opname, optype):
 564         # print (opname, op1, op2)
 565         pa = PartitionedEqGtGe(width, self.partpoints)
 566         setattr(self.m.submodules, self.get_modname(opname), pa)
 567         comb = self.m.d.comb
 568         comb += pa.opcode.eq(optype)  # set opcode
 569         if isinstance(op1, SimdSignal):
 570             comb += pa.a.eq(op1.sig)
 571         else:
 572             comb += pa.a.eq(op1)
 573         if isinstance(op2, SimdSignal):
 574             comb += pa.b.eq(op2.sig)
 575         else:
 576             comb += pa.b.eq(op2)
 577         return pa.output
 578
 579     def __eq__(self, other):
 580         width = len(self.sig)
 581         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 582
 583     def __ne__(self, other):
 584         width = len(self.sig)
 585         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 586         ne = Signal(eq.width)
 587         self.m.d.comb += ne.eq(~eq)
 588         return ne
 589
 590     def __lt__(self, other):
 591         width = len(self.sig)
 592         # swap operands, use gt to do lt
 593         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 594
 595     def __le__(self, other):
 596         width = len(self.sig)
 597         # swap operands, use ge to do le
 598         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 599
 600     def __gt__(self, other):
 601         width = len(self.sig)
 602         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 603
 604     def __ge__(self, other):
 605         width = len(self.sig)
 606         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 607
 608     # no override needed: Value.__abs__ is general enough it does the job
 609     # def __abs__(self):
 610
 611     def __len__(self):
 612         return len(self.sig)
 613
 614     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=716
 615     # def __getitem__(self, key):
 616
 617     def __new_sign(self, signed):
 618         # XXX NO - SimdShape not Shape
 619         print("XXX requires SimdShape not Shape")
 620         shape = Shape(len(self), signed=signed)
 621         result = SimdSignal.like(self, shape=shape)
 622         self.m.d.comb += result.sig.eq(self.sig)
 623         return result
 624
 625     # http://bugs.libre-riscv.org/show_bug.cgi?id=719
 626     def as_unsigned(self):
 627         return self.__new_sign(False)
 628
 629     def as_signed(self):
 630         return self.__new_sign(True)
 631
 632     # useful operators
 633
 634     def bool(self):
 635         """Conversion to boolean.
 636
 637         Returns
 638         -------
 639         Value, out
 640             ``1`` if any bits are set, ``0`` otherwise.
 641         """
 642         width = len(self.sig)
 643         pa = PartitionedBool(width, self.partpoints)
 644         setattr(self.m.submodules, self.get_modname("bool"), pa)
 645         self.m.d.comb += pa.a.eq(self.sig)
 646         return pa.output
 647
 648     def any(self):
 649         """Check if any bits are ``1``.
 650
 651         Returns
 652         -------
 653         Value, out
 654             ``1`` if any bits are set, ``0`` otherwise.
 655         """
 656         return self != Const(0)  # leverage the __ne__ operator here
 657         return Operator("r|", [self])
 658
 659     def all(self):
 660         """Check if all bits are ``1``.
 661
 662         Returns
 663         -------
 664         Value, out
 665             ``1`` if all bits are set, ``0`` otherwise.
 666         """
 667         # something wrong with PartitionedAll, but self == Const(-1)"
 668         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=176#c17
 669         #width = len(self.sig)
 670         #pa = PartitionedAll(width, self.partpoints)
 671         #setattr(self.m.submodules, self.get_modname("all"), pa)
 672         #self.m.d.comb += pa.a.eq(self.sig)
 673         # return pa.output
 674         return self == Const(-1)  # leverage the __eq__ operator here
 675
 676     def xor(self):
 677         """Compute pairwise exclusive-or of every bit.
 678
 679         Returns
 680         -------
 681         Value, out
 682             ``1`` if an odd number of bits are set, ``0`` if an
 683                   even number of bits are set.
 684         """
 685         width = len(self.sig)
 686         pa = PartitionedXOR(width, self.partpoints)
 687         setattr(self.m.submodules, self.get_modname("xor"), pa)
 688         self.m.d.comb += pa.a.eq(self.sig)
 689         return pa.output
 690
 691     # not needed: Value.implies does the job
 692     # def implies(premise, conclusion):
 693
 694     # TODO. contains a Value.cast which means an override is needed (on both)
 695     # def bit_select(self, offset, width):
 696     # def word_select(self, offset, width):
 697
 698     # not needed: Value.matches, amazingly, should do the job
 699     # def matches(self, *patterns):
 700
 701     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=713
 702     def shape(self):
 703         return self.sig.shape()