src/ieee754/part/test/minitest_partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 mini demo test of Cat and Assign
   8 """
   9
  10 from nmigen import Signal, Module, Elaboratable, Cat, Const, signed
  11 from nmigen.back.pysim import Simulator, Settle
  12 from nmutil.extend import ext
  13
  14 from ieee754.part_mul_add.partpoints import PartitionPoints
  15 from ieee754.part.partsig import SimdSignal
  16
  17
  18 if __name__ == "__main__":
  19     from ieee754.part.test.test_partsig import create_simulator
  20     m = Module()
  21     mask = Signal(3)
  22     a = SimdSignal(mask, 16)
  23     b = SimdSignal(mask, 16)
  24     o = SimdSignal(mask, 32)
  25     a1 = SimdSignal(mask, 16)
  26     b1 = SimdSignal(mask, 16)
  27     omask = (1<<len(o)) - 1
  28     a.set_module(m)
  29     b.set_module(m)
  30     o.set_module(m)
  31     a1.set_module(m)
  32     b1.set_module(m)
  33
  34     # RHS Cat
  35     m.d.comb += o.eq(Cat(a, b))
  36     # LHS Cat
  37     m.d.comb += Cat(a1, b1).eq(o)
  38
  39     sim = create_simulator(m, [], "minitest")
  40
  41     def process():
  42         yield mask.eq(0b000)
  43         yield a.sig.eq(0x0123)
  44         yield b.sig.eq(0x4567)
  45         yield Settle()
  46         out = yield o.sig
  47         print("out 000", bin(out&omask), hex(out&omask))
  48         yield mask.eq(0b010)
  49         yield Settle()
  50         out = yield o.sig
  51         print("out 010", bin(out&omask), hex(out&omask))
  52         yield mask.eq(0b110)
  53         yield Settle()
  54         out = yield o.sig
  55         print("out 110", bin(out&omask), hex(out&omask))
  56         yield mask.eq(0b111)
  57         yield Settle()
  58         out = yield o.sig
  59         print("out 111", bin(out&omask), hex(out&omask))
  60
  61     sim.add_process(process)
  62     with sim.write_vcd("partition_minitest.vcd", "partition_partition_ass.gtkw",
  63                         traces=[]):
  64         sim.run()
  65